JP2003287559A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve test throughput by performing screening without reducing the number of mounting devices even in the case of different semiconductor devices of pin arrangement. <P>SOLUTION: An intermediate board 3 is provided at an IC socket 1 mounted to a burn-in board. The intermediate board 3 is made of a flexible wiring board where a wiring pattern is formed on both the sides of an insulating tape film. A pad where the external terminal of the semiconductor device is connected is formed on the surface of the middle board 3, and a pin for conversion where a pad 2c of a socket lower substrate 2 is connected is formed on the rear surface. The pad and conversion pin are connected via the wiring pattern and through holes, and pin arrangement can be easily changed by the intermediate pin board 3 even in the case of the semiconductor device having different pin arrangement, thus eliminating the need for a pin board or the like for converting the pin arrangement being packaged on the burn-in board. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique effective when applied to improving throughput in a burn-in test.

[0002]

2. Description of the Related Art Semiconductor devices are screened before shipment for the purpose of selecting good products and defective products that satisfy specifications. This screening is performed by a burn-in device in which the semiconductor device is automatically inserted into an IC socket mounted on the burn-in board and mounted on the burn-in board, and a burn-in board mounted with a large number of semiconductor devices is housed in a burn-in chamber. Done.

For example, for a semiconductor device of small quantity and a large amount of products such as ASIC, manufacturing a burn-in board for each product increases the cost. The pin board is used to absorb the difference in pin arrangement.

The burn-in board is mounted with a common pin board for changing common wiring and an individual pin board provided for each semiconductor device and changing the pin arrangement of each semiconductor device.

An example in which the test technique for this type of semiconductor device is described in detail is as follows:
March 30, published by Press Journal Co., Ltd., Shinji Matsushita (ed.), "Monthly Semiconductor Director World"
d special issue ULSI test technology "P73 to P75, and this document describes a burn-in test technology in a memory.

[0006]

However, the present inventor has found that the burn-in board using the above pinboard has the following problems.

That is, since the pin board is mounted on the burn-in board, the area for mounting the semiconductor device is reduced, and the throughput of the burn-in test is reduced.

It is an object of the present invention to provide a method of manufacturing a semiconductor device that can perform screening without reducing the number of mounted semiconductor devices even if the semiconductor device has a different pin arrangement and improve the throughput in the burn-in test. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the method of manufacturing a semiconductor device of the present invention comprises a step of preparing a semiconductor device for screening, and an inspection in which a socket equipped with a wiring conversion board for converting a connection destination of an external terminal of the semiconductor device is mounted. The method comprises the steps of preparing a wiring board for use, mounting the semiconductor device in a socket of the wiring board for inspection, and screening the semiconductor device mounted on the wiring board for inspection.

The method of manufacturing a semiconductor device according to the present invention is
A step of preparing a semiconductor device to be screened, a test wiring board having a socket mounted with a wiring conversion board on which a protection resistance of the semiconductor device is formed while converting a connection destination of an external terminal of the semiconductor device. The method includes a step of preparing, a step of mounting a semiconductor device in a socket of an inspection wiring board, and a step of screening a semiconductor device mounted on the inspection wiring board.

Further, in the method for manufacturing a semiconductor device of the present invention, a step of preparing a semiconductor device to be screened, a connection destination of an external terminal of the semiconductor device is converted, and a wiring conversion board having a bypass capacitor is formed. Having a step of preparing an inspection wiring board on which the provided socket is mounted, a step of mounting a semiconductor device in the socket of the inspection wiring board, and a step of screening the semiconductor device mounted on the inspection wiring board Is.

The method of manufacturing a semiconductor device according to the present invention is
A step of preparing a semiconductor device to be screened and converting a connection destination of an external terminal of the semiconductor device and mounting a socket provided with a wiring conversion board in which at least one of a pull-down resistor and a pull-up resistor is formed are mounted. The method includes the steps of preparing an inspection wiring board, mounting the semiconductor device in a socket of the inspection wiring board, and screening the semiconductor device mounted on the inspection wiring board.

Further, in the method for manufacturing a semiconductor device of the present invention, the step of preparing a semiconductor device to be screened, the connection destination of the external terminal of the semiconductor device is changed, and the protection resistor, bypass capacitor, and pull-down of the semiconductor device are used. A step of preparing an inspection wiring board in which a socket having a wiring conversion board in which at least one of a resistor and a pull-up resistor is formed by a thin film technique is mounted, and a semiconductor device is attached to the socket of the inspection wiring board. And a step of screening the semiconductor device mounted on the inspection wiring board.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

(Embodiment 1) FIG. 1 is an explanatory view showing the structure of an IC socket according to Embodiment 1 of the present invention, and FIG.
1 is a top view of the intermediate board provided in the IC socket of FIG. 1, FIG. 3 is a sectional view of the intermediate board provided in the IC socket of FIG. 1, and FIG. 4 is a socket provided in the IC socket of FIG. 6 is an explanatory view showing an outline of a test signal transmission path when the lower substrate and the semiconductor device are connected via an intermediate board; FIG. 5 is a sectional view of the semiconductor device mounted in the IC socket of FIG. 1; 6 is a flowchart showing a manufacturing process in the semiconductor device of FIG.

In the first embodiment, the IC socket (socket) 1 is one of surface mount packages B.
A socket for mounting the GA type semiconductor device 7 (FIG. 4), which is mounted on a burn-in board (inspection wiring board) of a burn-in device for screening.

As shown in FIG. 1, the IC socket 1 includes a socket lower base body 2, an intermediate board (wiring conversion board) 3,
It is composed of an alignment adapter 4 and a socket upper base 5. The socket lower base 2 includes a lower base 2a, external pins 2b, and pads 2c.

The lower base 2a is a base on which the external pins 2b and the pads 2c are arranged and fixed, and is made of a glass fiber-containing plastic material such as PES (polyether sulfone) or PEI (polyether imide).

On the back surface (mounting surface) of the lower base 2a, there are arranged external pins 2b which are connecting pins for electrically connecting the external terminals of the semiconductor device 7 and the burn-in board. In addition, in the vicinity of the peripheral portion of the surface of the lower base 2a,
Pads 2c are arranged. The external pins 2b are connected to the pads 2c, respectively.

An intermediate board 3 is mounted on the socket lower base body 2. The intermediate board 3 is a board for changing the pin arrangement of the semiconductor device 7, and arbitrarily converts the connection destination of the external terminal of the semiconductor device 7 mounted in the IC socket 1.

An alignment adapter 4 is mounted on the intermediate board 3. The alignment adapter 4 is provided with a quadrilateral insertion hole into which the semiconductor device 7 is inserted. The insertion hole serves as a guide for positioning the package of the semiconductor device 7.

On the upper part of the alignment adapter 4, a socket upper base 5 is provided. Socket upper base 5
Consists of an upper base 5a and a movable lid 5b. Similarly, the upper base 5a is also provided with a quadrangular insertion hole into which the semiconductor device 7 is inserted.

On one side having the movable lid 5b, the fixing claw 5 is provided.
b ₁ is provided, and is rotatably attached to the upper base 5 a by a shaft provided on one side facing the fixing claw 5 b ₁ .

When mounting the semiconductor device 7 on the IC socket 1, the movable lid 5b is brought into close contact with the upper base 5a, and the upper base 5a and the movable lid 5b are fixed by the fixing claws 5b ₁ .

Further, these alignment adapters 4,
Similarly to the socket lower base body 2, the socket upper base body 5 is also made of a glass fiber-containing plastic material such as PES or PEI.

Socket lower base 2, intermediate board 3, alignment adapter 4, and socket upper base 5
Screw holes 6 are formed in each of the two corners,
It has an integral structure screwed by a screw inserted into the screw hole.

The intermediate board 3 is shown in FIGS.
Will be explained.

The intermediate board 3 is composed of a flexible wiring board having wiring patterns 3b formed on both sides of an insulating tape film 3a such as polyimide with an adhesive material. The wiring patterns 3b formed on both sides of the intermediate board 3 are
They are connected to each other through the through holes 3c.

Surface of the intermediate board 3 (semiconductor device mounting surface)
A pad 3d to which an external terminal of the semiconductor device 7 is connected is provided on one end of the wiring pattern 3b formed on the.

Furthermore, at one end of the wiring pattern 3b formed on the back surface of the intermediate board 3, conversion pins 3e to which the pads 2c of the socket lower base 2 are connected are formed. The connection destinations of the pad 3d and the conversion pin 3e are arbitrarily changed by the wiring pattern 3b and the through hole 3c.

The intermediate board 3 allows the pin arrangement to be easily changed even for semiconductor devices having different pin arrangements, so that a pin board for pin arrangement conversion mounted on the burn-in board is unnecessary. can do.

FIG. 4 is an explanatory view showing an outline of a test signal transmission path when the semiconductor device 7 and the socket lower base body 2 are connected via the intermediate board 3.

As shown in the figure, the connection destination between the external pin 2b and the external terminal of the semiconductor device 7 can be arbitrarily changed. Therefore, by changing the intermediate board 3, the arrangement of the external terminal is different. However, it is possible to deal flexibly.

The structure of the semiconductor device 7 will be described.

As shown in FIG. 5, the semiconductor device 7 is provided with a wiring board 8 made of a polyimide resin material or the like. Electrodes and wiring patterns are formed on the main surface of the wiring board 8.

Bump electrodes and a wiring pattern are formed on the back surface of the wiring board 8, and the electrodes and the bump electrodes are electrically connected by the wiring pattern and through holes, respectively.

A solder resist is formed on the entire surface of the wiring board 8 except the electrodes and bump electrodes. This solder resist is, for example, melanin, epoxy,
It is made of acrylic and polystyrene, and prevents wiring patterns that do not require soldering from contacting molten solder.

The electrodes are formed in an array at an equal pitch, and the bump electrodes are formed near the periphery of the wiring board 8. A semiconductor chip 9 is bonded to a central portion of the main surface of the wiring board 8 with a resin material 10 interposed therebetween.

A plurality of chip electrodes are formed on the semiconductor chip 9, and these chip electrodes and the electrodes of the wiring board 8 are connected via the solder bumps 11 made of spherical solder.

Further, the electrodes for bumps on the wiring board 8 are also
Solder bumps (external terminals) 12 made of spherical solder are formed, and these solder bumps 12 serve as external terminals of the semiconductor device 7.

Next, the semiconductor device 7 according to the present embodiment.
The manufacturing process will be described with reference to the flowchart of FIG.

First, after a semiconductor element or the like is formed on a semiconductor wafer by a general wafer process (step S101), a wafer test of the semiconductor wafer is performed to select a good product and a defective product of each semiconductor chip 9 ( Step S102).

Then, the semiconductor wafer is cut along the dicing line to separate individual semiconductor chips 9 (step S103), and in the processing of step S102,
The defective semiconductor chip 9 is discarded (step S
104).

Thereafter, solder bumps 11 are formed on the electrodes formed on the semiconductor chip 9 (step S10).
5) The wiring board 8 on which the semiconductor chip 9 is mounted is prepared. The semiconductor chip 9 is mounted on the main surface of the wiring board 8, and the electrodes of the wiring board 8 and the chip electrodes of the semiconductor chip 9 are connected via the solder bumps 11 (step S106).

In the gap between the semiconductor chip 9 and the wiring board 8,
A resin material 10 such as an epoxy resin for the purpose of electrical insulation protection and stress relaxation is injected (step S107).
The solder bumps 12 are respectively formed on the bump electrodes of the wiring substrate 8 in which the resin material 10 is injected by, for example, a printing method or a transfer method (step S108).

The semiconductor device 7 on which the solder bumps 12 are formed is subjected to a burn-in test for screening initial defects and the like (step S109).

In step S108, the semiconductor device 7 to be screened and the IC socket 1 provided with the intermediate board 3 for changing the pin arrangement of the semiconductor device 7 are prepared.

Then, the semiconductor device 7 is mounted in the IC socket 1. The semiconductor device 7 is mounted by a robot that automatically mounts an inserter or the like. The semiconductor device 7 mounted on the chip tray or the like is picked up by a vacuum chuck or the like, conveyed to a predetermined IC socket 1, and after the positioning of the IC socket 1 to be mounted is recognized, the semiconductor device 7 is mounted on the IC socket 1. It is installed.

After that, the n burn-in boards on which the large number of IC sockets 1 with the semiconductor device 7 mounted are mounted in the burn-in chamber, and screening is performed by the burn-in device.

When the screening is completed, the semiconductor devices 7 are taken out from the IC sockets 1, respectively, and the defective semiconductor devices 7 are discarded (step S110).
Then, a final test that guarantees the functions and electrical functions of the semiconductor device is performed by an LSI tester or the like (step S111).

The semiconductor device 7 which has become defective by this final test is discarded (step S112). As a result, the semiconductor device 7 is completed, and the semiconductor device 7 as a product is shipped (step S113).

Therefore, according to the first embodiment, by providing the intermediate board 3 in the IC socket 1, the burn-in board can be used in common even when mounting semiconductor devices having different pin arrangements. , Burn-in test cost can be reduced.

Further, the pin arrangement can be changed even in a semiconductor device having a different pin arrangement by simply converting the intermediate board 3 of the IC socket 1. Therefore, the pin for converting the pin arrangement mounted on the burn-in board can be changed. A board or the like becomes unnecessary, and the test throughput per burn-in board can be improved.

(Embodiment 2) FIG. 7 is a top view of an intermediate board provided in an IC socket according to Embodiment 2 of the present invention, and FIG. 8 is a sectional view of resistors formed on the intermediate board of FIG. 9 is a cross-sectional view of the bypass capacitor formed on the intermediate board of FIG. 7.

[0057] In this embodiment 2, IC sockets (socket) 1, similarly to the first embodiment, the socket lower substrate 2, an intermediate board (wiring conversion board) 3 _1, the alignment adapter 4, and the socket upper substrate 5 and is different in that a bypass capacitor C for stabilizing the power supply and a resistor (protection resistor) R for protecting the input / output element are formed on the intermediate board 3 ₁ .

As shown in FIG. 7, the intermediate board 3 ₁ is composed of a flexible wiring board having wiring patterns 3b formed on both sides of an insulating tape film 3a such as polyimide with an adhesive material. These wiring patterns 3b are connected via the through holes 3c.

A resistor R is connected to an arbitrary wiring pattern 3b, and a bypass capacitor C is connected between adjacent wiring patterns 3b.

A pad 3d to which an external terminal of the semiconductor device 7 (FIG.) Is connected is provided at one end of the wiring pattern 3b formed on the surface (semiconductor device mounting surface) of the intermediate board 3 ₁ . .

Further, the conversion pin 3e (FIG. 4) to which the pad 2c of the socket lower base body 2 is connected to one end of the wiring pattern 3b formed on the back surface of the intermediate board 3 ₁ .
Are formed.

The connection destinations of the pad 3d and the conversion pin 3e are arbitrarily changed by the wiring pattern 3b and the through hole 3c.

The resistor R and the bypass capacitor C formed on the intermediate board 3 ₁ will be described.

FIG. 8 is a sectional view of the resistor R formed on the intermediate board 3 ₁ . The resistor R is made of a metal material such as chrome (Cr).

The resistor R is formed by forming a resistance layer of chrome by the CVD method or plating, and then removing unnecessary portions by etching or the like to form a thin film resistor.

Then, a metal material such as copper (Cu) is formed by plating or a CVD method to form a good conductor, and unnecessary portions are removed by etching or the like to form the wiring pattern 3b.

In this etching, it is necessary to use an etcher having a large etching rate ratio of copper and chrome.

Here, the resistor R is formed as a protective resistor for the semiconductor device 7, but not only the protective resistor,
The resistor R may be formed as a pull-down resistor connected between an external terminal of the semiconductor device 7 and a reference potential and a pull-up resistor connected between an external terminal of the semiconductor device 7 and a power supply voltage. .

Further, FIG. 9 is a sectional view of the bypass capacitor C formed on the intermediate board 3 ₁ . The bypass capacitor C is connected, for example, between the wiring pattern 3b to which the reference potential (VSS) is connected and the wiring pattern 3b to which the power supply voltage (VCC) is connected.

As shown in the figure, the bypass capacitor C has a structure in which a dielectric layer C ₂ made of silicon nitride or the like is formed on a resistance layer C _{1 made} of chrome or the like.

When forming the bypass capacitor C, a resistance layer is formed by a CVD method, plating or the like, and then an unnecessary portion is removed by etching or the like to form a resistance layer C ₁ of a thin film resistor.

Then, after forming a dielectric of silicon nitride by a CVD method or the like on all surfaces except a part of the resistance layer C ₁ , unnecessary portions are removed by etching or the like to form a dielectric layer C ₂ . To do.

Therefore, a part of the resistance layer C ₁ is exposed without being covered with the dielectric layer C ₂ . Then, one of the wiring pattern 3b formed on the dielectric layer C _2, the other wiring patterns 3b, formed on the exposed resistive layer C _1.

[0074] Thus, in this second embodiment, the resistance to the intermediate board 3 _1, and by forming a bypass capacitor C, without reducing the throughput per one burn-in board, the destruction of the semiconductor device 7 It can be prevented and the test efficiency can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments and various modifications are possible without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the first and second embodiments, the intermediate board is formed of the flexible board, but a printed wiring board such as a glass epoxy board may be used.

[0077]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) By performing screening using a socket provided with a wiring conversion board, even if a semiconductor device having a different pin arrangement is used, a test throughput can be obtained simply by replacing the semiconductor device with a wiring conversion board corresponding to the semiconductor device. It is possible to use the inspection wiring board in common without reducing it.

(2) Further, the wiring conversion board has a protective resistor,
By forming at least one of the bypass capacitor, the pull-down resistor, and the pull-up resistor, it is possible to prevent the semiconductor device from being broken without lowering the test throughput.

(3) Further, according to the above (1) and (2), it is not necessary to design or manufacture an inspection wiring board corresponding to each semiconductor device of small-quantity, high-mix-volume production in which the arrangement of external terminals is different. The test cost of can be greatly reduced.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of an IC socket according to a first embodiment of the present invention.

FIG. 2 is a top view of an intermediate board provided in the IC socket of FIG.

FIG. 3 is a cross-sectional view of an intermediate board provided in the IC socket of FIG.

FIG. 4 is an explanatory diagram showing an outline of a test signal transmission path when a socket lower substrate provided in the IC socket of FIG. 1 and a semiconductor device are connected via an intermediate board.

5 is a cross-sectional view of a semiconductor device mounted on the IC socket of FIG.

6 is a flowchart showing manufacturing steps in the semiconductor device of FIG.

FIG. 7 is a top view of an intermediate board provided in an IC socket according to Embodiment 2 of the present invention.

8 is a sectional view of a resistor formed on the intermediate board of FIG.

9 is a cross-sectional view of a bypass capacitor formed on the intermediate board of FIG.

[Explanation of symbols]

1 IC socket (socket) 2 Socket lower base 2a Lower base 2b External pin 2c Pad 3 Intermediate board (wiring conversion board) 3 ₁ Intermediate board (wiring conversion board) 3a Insulation tape film 3b Wiring pattern 3c Through hole 3d Pad 3e For conversion Pin 4 Alignment adapter 5 Socket upper base 5a Upper base 5b Movable lid 5b ₁ Fixing tab 6 Screw hole 7 Semiconductor device 8 Wiring board 9 Semiconductor chip 10 Resin material 11 Solder bump 12 Solder bump (external terminal) C Bypass capacitor C ₁ Resistance Layer C ₂ Dielectric layer R Resistance (protection resistance)

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shinji Nishimura             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Kenichiro Morinaga             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F-term (reference) 2G003 AA07 AC01 AD02 AG01 AG08                       AH04                 5E024 CA18

Claims (5)

[Claims] 1. A step of preparing a semiconductor device to be screened, a step of preparing an inspection wiring board on which a socket having a wiring conversion board for converting a connection destination of an external terminal of the semiconductor device is mounted, A method for manufacturing a semiconductor device, comprising: a step of mounting the semiconductor device in a socket of an inspection wiring board; and a step of screening the semiconductor device mounted on the inspection wiring board. 2. A step of preparing a semiconductor device for screening, a step of converting a connection destination of an external terminal of the semiconductor device, and a socket provided with a wiring conversion board having a protective resistance of the semiconductor device mounted thereon. A step of preparing the inspection wiring board, a step of mounting the semiconductor device in a socket of the inspection wiring board, and a step of screening the semiconductor device mounted on the inspection wiring board. And a method for manufacturing a semiconductor device. 3. A step of preparing a semiconductor device to be screened, and a wiring for inspection in which a socket having a wiring conversion board formed with a bypass capacitor is formed while converting a connection destination of an external terminal of the semiconductor device. A semiconductor device comprising: a step of preparing a board; a step of mounting the semiconductor device in a socket of the inspection wiring board; and a step of screening the semiconductor device mounted on the inspection wiring board. Manufacturing method. 4. A step of preparing a semiconductor device to be screened, and a wiring conversion board for converting a connection destination of an external terminal of the semiconductor device and having at least one of a pull-down resistor and a pull-up resistor formed therein. A step of preparing an inspection wiring board on which the socket is mounted, a step of mounting the semiconductor device on the socket of the inspection wiring board, and a step of screening the semiconductor device mounted on the inspection wiring board. A method of manufacturing a semiconductor device, comprising: 5. A step of preparing a semiconductor device for screening, a step of converting a connection destination of an external terminal of the semiconductor device, a protection resistor, a bypass capacitor of the semiconductor device,
A step of preparing an inspection wiring board having a socket provided with a wiring conversion board in which at least one of a pull-down resistor and a pull-up resistor is formed by a thin film technique; and a step of preparing the semiconductor in the socket of the inspection wiring board. A method of manufacturing a semiconductor device, comprising: mounting a device; and screening the semiconductor device mounted on the inspection wiring board.