JPS5848920A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5848920A
JPS5848920A JP14614881A JP14614881A JPS5848920A JP S5848920 A JPS5848920 A JP S5848920A JP 14614881 A JP14614881 A JP 14614881A JP 14614881 A JP14614881 A JP 14614881A JP S5848920 A JPS5848920 A JP S5848920A
Authority
JP
Japan
Prior art keywords
groove
etching
laser beam
mask
mask material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14614881A
Other languages
Japanese (ja)
Inventor
Yutaka Misawa
三沢 豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14614881A priority Critical patent/JPS5848920A/en
Publication of JPS5848920A publication Critical patent/JPS5848920A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To simplify the groove forming process by selectively providing the etching mask material on the surface of semiconductor base material, forming the mask by removing the mask material after irradiating the laser beam to the groove forming area and etching said mask. CONSTITUTION:The both sides of semiconductor base material 41 having completed the diffusion is covered with the oxide film 42 and it is removed and simultaneously the groove 16 is formed by irradiating the laser beam to the groove forming area. Thereafter, the groove 45 is formed by etching process using the mixed acidic solution of the fluoric acid + nitric acid + acetic acid, thereby uneven surface of affected layer generated by irradiation of laser beam and pattern edges can be removed. Succeedingly, when the groove surface is covered with the insulating layer, the specified rejection characteristic can be obtained. According to this method, the groove can be selectively formed only with two processes, attaining reduction in cost.

Description

【発明の詳細な説明】 本発明は半導体基体に溝を形成する工程を具備する半導
体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, which includes a step of forming a groove in a semiconductor substrate.

半導体装置特に高耐圧半導体装置ではpn接合を形成し
た半導体基体の主表面に溝を形成して。
In semiconductor devices, particularly high voltage semiconductor devices, grooves are formed in the main surface of a semiconductor substrate on which a pn junction is formed.

溝内にpn接合を露出した後、溝の表面に絶縁膜を被着
する方法が広く行われている。この構造はプレーナ構造
よシも高耐圧が容易′に得られるという゛特徴を有する
が、溝を形成する余分な工程が必要になる。通常、溝を
形成するには第1図に示す方法が広く行われている。(
a)半導体基体1の両生表面に酸化膜2を形成する。こ
の工程は通常拡散と同時に行われる。(b)酸化膜2の
表面にホトレジスト3を塗布し、プリベークする。(C
−)露光、現像を行ない、溝を形成すべき1固所4のホ
トレジストを除去する。次いで、ポストベーキングを行
う。
A widely used method is to expose a pn junction within the trench and then deposit an insulating film on the surface of the trench. Although this structure has the advantage that a higher withstand voltage can be easily obtained than the planar structure, it requires an extra step of forming the grooves. Generally, the method shown in FIG. 1 is widely used to form grooves. (
a) An oxide film 2 is formed on the amphibodi surface of the semiconductor substrate 1. This step is usually performed simultaneously with diffusion. (b) A photoresist 3 is applied to the surface of the oxide film 2 and prebaked. (C
-) Perform exposure and development to remove the photoresist at one location 4 where a groove is to be formed. Next, post-baking is performed.

(d)弗化水素酸を主成分とする液に浸漬し、ホトレジ
スト3をマスクとして選択的に酸化膜2を除去′する。
(d) The oxide film 2 is selectively removed by immersing it in a solution containing hydrofluoric acid as a main component and using the photoresist 3 as a mask.

(e)弗化水素酸、硝酸、鉛酸からなる混酸に浸漬し、
ホトレジスト3及び酸化膜2をマスクとして半導体基体
1をエツチングしてpn接合よシ深い溝5を形成する。
(e) immersed in a mixed acid consisting of hydrofluoric acid, nitric acid, and lead acid;
Using the photoresist 3 and the oxide film 2 as a mask, the semiconductor substrate 1 is etched to form a deep trench 5 beyond the pn junction.

以上の如く、従来の溝形成法は工程が多く、半導体素子
のコストが高いという問題がある。
As described above, the conventional trench forming method requires many steps and has the problem that the cost of the semiconductor device is high.

本発明の目的は溝形成工程を簡略化した半導体装置の製
法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device that simplifies the trench forming process.

本発明は半導体基体表面にエツチング・マスクとなる材
料を形成した後、溝を形成すべきll1il所にレーザ
ー光を照射し、その個所のエツチング・マスク材料を除
去する。深い溝を形成する場合にはエツチング・マスク
材料の下の半導体基体の一部も除去した方が好ましい。
In the present invention, after a material serving as an etching mask is formed on the surface of a semiconductor substrate, a laser beam is irradiated to a location where a groove is to be formed, and the etching mask material at that location is removed. When forming deep trenches, it is preferable to also remove a portion of the semiconductor body under the etch mask material.

次いで、Aつだエツチング・マスク材料をマスクとして
エツチングし、溝を形成する。この場合、レーザー光照
射によシ生、じた変質層が残っていると半導体装置のも
れ電流が多く、かつ、耐圧も低くなる。第2図はレーザ
ー光照射後の二ソ′チング時間と半導体装置の電流−電
圧・特性を示す。曲JAはエツチング時間O秒、Bは5
秒、Cは30秒、Dは60秒のデータである。エツチン
グ時間が短いともれ電流が多くいわゆるソフトな波形で
あるが、エツチング時間の増加と共にもれ電流が減少し
、60秒以上で良好特性となる。このものではレーザー
光照射による変質層は完全に除去されている。また、レ
ーザーはパルスであるため、レーザー照射パターンの端
が第3図(a)の如く凹凸となるが、溝にこのような凹
凸、特に図中に丸で囲んだような鋭角の凸部があるとそ
の部分に電界が集中し耐圧が低下する。
Next, etching is performed using the A-shaped etching mask material as a mask to form grooves. In this case, if a deteriorated layer caused by the laser beam irradiation remains, the leakage current of the semiconductor device will be large and the withstand voltage will be low. FIG. 2 shows the two-sorting time after laser beam irradiation and the current-voltage characteristics of the semiconductor device. Song JA has an etching time of 0 seconds, B has an etching time of 5 seconds.
seconds, C is data for 30 seconds, and D is data for 60 seconds. When the etching time is short, there is a lot of leakage current and the waveform is so-called soft, but as the etching time increases, the leakage current decreases, and good characteristics are obtained when the etching time is longer than 60 seconds. In this case, the altered layer caused by laser beam irradiation has been completely removed. In addition, since the laser is a pulse, the edges of the laser irradiation pattern are uneven as shown in Figure 3 (a), and the grooves have such unevenness, especially acute-angled protrusions as circled in the figure. If there is, the electric field will concentrate in that area and the withstand voltage will drop.

また1通常凸部の曲率半径が300μm以下であると耐
圧の低下することを経験的に確認している。
Furthermore, it has been empirically confirmed that when the radius of curvature of the convex portion is 300 μm or less, the breakdown voltage decreases.

このものを適切な時間エツチングするとサイドエツチン
グにより凹凸がなくなり、所望の耐圧が得られる。従っ
てレーザー照射後のエツチングはレーザー照射変質層を
なくすと共に耐圧に影響を及ぼすような曲率半径の小さ
い凹凸部をなくするまで行う必要がおる。
If this material is etched for an appropriate time, the unevenness will be eliminated by side etching, and the desired withstand pressure will be obtained. Therefore, it is necessary to perform etching after laser irradiation until the laser irradiation-altered layer is eliminated and the irregularities with a small radius of curvature that would affect the breakdown voltage are eliminated.

次に本発明をダイオードの溝形成に実施した例について
第4図に従って述べる。(a)は拡散の終了した半導体
基体41を示す。半導体基体41の両生表面は拡散工程
で形成された酸化膜42で覆われている。(ト)溝を形
成すべき部分にレーザー光を照射し、酸化膜42を除去
すると共に深さ30μmの溝4σを形成する。(C)弗
化水素酸、硝酸。
Next, an example in which the present invention is applied to forming grooves in a diode will be described with reference to FIG. (a) shows a semiconductor substrate 41 that has been completely diffused. The amphibian surface of the semiconductor substrate 41 is covered with an oxide film 42 formed in a diffusion process. (G) Laser light is irradiated onto the portion where the groove is to be formed to remove the oxide film 42 and form a groove 4σ with a depth of 30 μm. (C) Hydrofluoric acid, nitric acid.

鉛酸の容量化が5:8:5の混酸で120秒エツチング
し、深さ80μmの溝45を形成する。このエツチング
によりレーザー照射により生じた変質層及びパターン端
の凹凸を除去する。しかる後、溝表面を絶縁膜で被覆す
ると所定の阻止特性が得られる。
Etching is performed for 120 seconds using a mixed acid with a lead acid capacity ratio of 5:8:5 to form a groove 45 with a depth of 80 μm. This etching removes the altered layer and unevenness at the edge of the pattern caused by laser irradiation. Thereafter, the groove surface is coated with an insulating film to obtain a predetermined blocking characteristic.

以上のように本発明によればわずか2工程で選択的に溝
を形成できるので溝形成の低コスト化がはかれる。
As described above, according to the present invention, grooves can be selectively formed in just two steps, thereby reducing the cost of groove formation.

上記実施例ではエツチング・マスク材料として酸化膜を
(資)用した場合について述べたが、窒化/リコン、燐
ガラス、アルミナ、酸素ドープ多結晶シリコン、酸化タ
ンタルなどいずれのものでもよい。
In the above embodiment, an oxide film is used as the etching mask material, but any material such as nitride/recon, phosphor glass, alumina, oxygen-doped polycrystalline silicon, tantalum oxide, etc. may be used.

本発明によれば工程が少なく、簡単であるので安価な溝
形成ができる。
According to the present invention, the number of steps is small and simple, so that grooves can be formed at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の14形成法を説明する工程図、第2図は
本発明を説明する半導体装置の電流−電圧特性図、第3
図は溝部の平面図、第4図は本発明による溝形成法を説
明する工程図である。 41・・・半導体基体、42・・・酸化膜、45・・・
溝。 葛1m 82m /l /L(r)
FIG. 1 is a process diagram explaining the conventional 14 forming method, FIG. 2 is a current-voltage characteristic diagram of a semiconductor device explaining the present invention, and FIG.
The figure is a plan view of the groove, and FIG. 4 is a process diagram illustrating the groove forming method according to the present invention. 41... Semiconductor base, 42... Oxide film, 45...
groove. Kudzu 1m 82m /l /L(r)

Claims (1)

【特許請求の範囲】 1、半導体基体の主表面に溝を形成する方法に於いて、
半導体基体の選択された表面に予めエツチング・マスク
材を形成する工程、溝を形成すべき個所にレーザー光を
照射し、少なくともエツチング・マスク材を除去する工
程、エツチング・マスク材をマスクとして半導体基板を
選択的にエツチングして半導体基体の選択された主表面
に溝を形成する工程を具備することを特徴とする半導体
装置の製造方法。 2、特許請求の範囲第1項に於いて、エツチングは少な
くともレーザー光照射によシ生じた変質層を除去すると
同時に溝パターンの凹凸をなくするのに充分な時間行う
ことを特徴とする半導体装置の製造方法。
[Claims] 1. In a method for forming grooves on the main surface of a semiconductor substrate,
A process of forming an etching mask material in advance on a selected surface of a semiconductor substrate, a process of irradiating a laser beam to the location where a groove is to be formed and removing at least the etching mask material, and a process of removing at least the etching mask material using the etching mask material as a mask. 1. A method of manufacturing a semiconductor device, comprising the step of selectively etching to form a groove in a selected main surface of a semiconductor substrate. 2. A semiconductor device according to claim 1, wherein the etching is carried out for a sufficient time to remove at least the altered layer caused by laser beam irradiation and at the same time eliminate the unevenness of the groove pattern. manufacturing method.
JP14614881A 1981-09-18 1981-09-18 Preparation of semiconductor device Pending JPS5848920A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14614881A JPS5848920A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14614881A JPS5848920A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5848920A true JPS5848920A (en) 1983-03-23

Family

ID=15401214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14614881A Pending JPS5848920A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5848920A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60118899A (en) * 1983-11-30 1985-06-26 松下電器産業株式会社 Voice analysis synthesization
JP2008053526A (en) * 2006-08-25 2008-03-06 Semiconductor Energy Lab Co Ltd Fabricating method of semiconductor device
JP2008078634A (en) * 2006-08-25 2008-04-03 Semiconductor Energy Lab Co Ltd Method of producing semiconductor device
KR101439103B1 (en) * 2006-08-25 2014-09-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60118899A (en) * 1983-11-30 1985-06-26 松下電器産業株式会社 Voice analysis synthesization
JP2008053526A (en) * 2006-08-25 2008-03-06 Semiconductor Energy Lab Co Ltd Fabricating method of semiconductor device
JP2008078634A (en) * 2006-08-25 2008-04-03 Semiconductor Energy Lab Co Ltd Method of producing semiconductor device
KR101439103B1 (en) * 2006-08-25 2014-09-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor device

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