JPS5848555A - Pcm reproducing relay circuit - Google Patents

Abstract

PURPOSE:To surely interrupt an output transistor circuit of a reproducing relay circuit at non-signal, by turning off an output signal of a non-signal detection circuit for two semiconductor elements generating a pulse signal of positive and negative polarity respectively. CONSTITUTION:A non-signal detection circuit NSD transmits a control signal to a discrimination circuit when no PCM signal is received. A discrimination circuit DC discriminates the polarity of each pulse of the received PCM signal, generates two high level RZ pulse signal corresponding to the polarity of each pulse, receives an output of a low level through the reception of the control signal from the non-signal detection circuit NSD and generates the output of a low level. A reproducing circuit RC' is provided with two semiconductor elements generating the pulse signal of positive and negative polarities, which are turned on with the output pulse signal of the discrimination circuit DC. The semiconductor elements are turned off with the low level output of the discriminating circuit DC.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PCM regenerative repeater circuit, and particularly to prevent overload or load on electrical elements of the regenerative circuit of the repeater circuit, such as amplifier elements. Also regarding the PCM regeneration relay circuit that is not given o”t”
be.

When transmitting a PCM signal7, a PCM regeneration repeater circuit is installed in the middle of the transmission path in order to correct and restore the signal, which has deteriorated due to transmission distortion, noise, etc. during transmission, back to its original correct waveform. Right now.

1 to 3 show a conventional OPCM regenerative repeater circuit PRC. In FIG. 1, the PCM signal 8 is transmitted from the transmitting end M to the line Lx as shown in FIG. 2 (I4). For rounding that does not include a DC component, a signal K, which is a combination of positive and negative pulses, is used as shown in Figure 2 (, I).Then, at the output end B of the transmission line L1, the signal shown in Figure 2 (, I) is used. The waveform deteriorates as shown in Figure 2 (0) K. The equalizer IQa of the PCM regenerative repeater circuit PRC corrects the distortion of the PCM signal received with this deteriorated condition, amplifies it, and sends it to the output terminal C as shown in Figure 2 (0) K. generates a waveform of
It is supplied to the timing circuit TO and the identification circuit DC. Timing circuit Tea receives this equalized waveform ((1) and generates a timing signal with the same period as the original PCM signal shown in FIG. 2(a) K at its output end. In response to the reception signal 4 (a), the presence or absence and polarity of the received PCM signal are identified and shaped, and the output terminal IK is as shown in Fig. 3 (
・）K outputs the positive polarity pulse in the PCM signal as shown in FIG.
A negative pulse in a CM signal is generated at a positive level. Transmission waveform (b), positive polarity pulse (@), negative polarity pulse' (f
) is mainly caused by the transmission peak Lλ. The original PCM signal is formed from the reproducing circuit RcFi (positive polarity pulse) and negative polarity pulse () to its output terminal G, and is transmitted to the next transmission line LmK.

In the conventional OFCM reproducing path shown in FIG. 1, the positive and negative pulses of the reproducing circuit RCa are each amplified by high-output transistor amplifiers.
If a high-output transistor is on when this positive or negative current is not supplied, its collector loss is at its maximum, so if this state continues for a long time, the transistor will Reliability is extremely reduced. The presence or absence of positive polarity pulses and negative polarity pulses of the PCM signal is determined by ζ, and when these signals are not supplied, K causes the high output transistor to be in a fast-acting state.

Figure 3 shows a regeneration circuit R that turns off the output transistor when there is no positive polarity pulse or negative polarity pulse of the PCM signal.
This figure shows one conventional example of C. In Fig. 3, when a positive pulse is supplied to the input terminal E, the flip-flop FFI consisting of two NAND circuits changes to -'p.
is turned on, NAND circuit NANDI is turned on, and transformer T
A high level positive pulse signal I is sent to the O primary coil L1.
z flows.

Similarly, when the λ power terminal PK negative polarity pulse is supplied, the flip-flop FF2 consisting of two NAND circuits is set, the similar NAND circuit NAND2 is turned on, and the transformer To primary cobe coil A111C has a high level negative polarity. The pulse signal 1 flows in the opposite direction to the positive pulse signal Il. By applying pressure in this way, the output end G1+G of the secondary coil tm
mk is the original PCM signal consisting of positive polarity pulse signal and negative polarity pulse signal is regenerated and output to transmission line Lm = If this is 0, either one or both of positive polarity pulse and negative polarity pulse is input. When not supplied to terminals E and F, inhibit circuit I consisting of two NAND circuits
NH generates an output and simultaneously leads slip-flops FFI and FF2 to output transistor circuit N.
AND1 and NAND2 are put into a fast-acting state.

The conductor TEA installed between the connection point of the two NAND circuits of the inhibition circuit INH and the ground is a time constant circuit that generates a reset output after no signal for a certain period of time.

Conventionally, in this way, when the positive polarity pulse (e) and the negative polarity pulse (f) were not supplied, it was impossible to avoid complicating the circuit configuration when the output run risk circuit was to be brought into a fast-acting state. .

Therefore, it is an object of the present invention to provide a PCM regeneration relay circuit which can improve the above-mentioned problems and reliably bring the output transistor circuit of the TKK regeneration circuit into the desired state. For this purpose, the PCM regeneration repeater circuit of the present invention includes a no-signal detection circuit that generates a control signal when a PC-M signal is not received, and a no-signal detection circuit that identifies the polarity of each pulse that makes up the received PCM signal. The first RZ pulse signal and the second RZ pulse signal are at a high level corresponding to the polarity of the pulse, and at a low level when receiving a control signal from the no-signal detection circuit. It has an identification M1 circuit which generates an output of the identification circuit, and a reproduction circuit which receives the output of the identification circuit and reproduces the PCM signal.

and the reproducing circuit is a first semiconductor element that is turned on by the first pulse signal to generate a positive pulse signal and is turned off when the second pulse signal PIi and a low level output are supplied. , the second semiconductor element is configured to be configured by a 20th semiconductor element which becomes ionized by the second pulse signal, generates a negative polarity pulse signal, and turns off when the first pulse signal and a low level output are supplied. Features.

An embodiment of the present invention will be described in detail below with reference to FIGS. 4 to 7.

Fig. 4 is a configuration diagram of an embodiment of the PCM regeneration relay circuit of the present invention, Fig. 5 is a regeneration circuit diagram thereof, Fig. 6 is an operation explanatory diagram, and Fig.
The figure shows an embodiment of the no-signal detection circuit N8D.

In FIG. 4, IQ is an equalizer, TC is a timing circuit, DC is an identification circuit, NSD is a no-signal detection circuit, and Rσ is a regeneration circuit. Among these, the configurations of the equalization-EQ, timing circuit TC, and discrimination circuit DC, and their output terminals C, D,
Waveforms at E and F (C), ■, (e), (f)
is the same as the conventional one shown in FIGS. 1 and 2.

The no-signal detection circuit NSD detects the output (
+1) and (f) t are both reset to low level.

Next, the configuration of the reproducing circuit Rσ will be explained with reference to FIG.

In FIG. 6, the emitters of transistors TRX and TRS are connected to one terminal (-Vo) of a power supply via a common emitter resistor Re. Collector is transformer T
o Connected to both ends of the primary coil L
1 is connected to the other terminal (+VB) of the power supply. The pace of the transistor TRI is supplied with an RZ type positive polarity signal (.) of the PC and M signals from the discrimination circuit DC.
An RZ type negative polarity signal (f) of the PCM signal is supplied to the pace of the transistor TRs from the job-specific circuit DC. The secondary coil No. 2 of transformer T forms the output terminal assembly for generating the regenerated original PCM signal. The transistor TR resistor R1 and the voltage dividing resistors Ra and Rs are the reference voltage generation circuit SVG, and the voltage of the power supply (+Vm, -Vo') is divided by the resistors Rs and Rs K to be applied to the transistor TRa.
A reference voltage vm, is generated at the input terminal of. This reference voltage vma g s ) is a positive polarity signal (.) of the PCM signal supplied to the pace of the run lister TRI, and a negative polarity signal (high level H and low level) of the PCM signal supplied to the pace of the transistor TRs. L (positive polarity signal (
e) and the high level H and low level L of the negative polarity signal (f) are the same).

Note that the transistors TRI to TRs are NPN in the embodiment.
It is of course possible to use a PNP type resistor Rs.
A Zener diode may be used as the

Next, the operations shown in FIGS. 4 and 5 will be explained with reference to FIG. 6.

In FIG. 4, the equalizer IQ, timing circuit TO, and job-specific circuit DC4D configuration lines are the same as those in FIG. 1, so
The waveforms of those output terminals C9D, E, and F (
C), (6), (・), (f) and transmitted nine PCs
M signal (e4 is the same as that in Figure 2 ・Waveform (・)
, (f) is the reference voltage generation circuit 8.
This is the reference voltage supplied from VG to the transistors TRz and TR, and to the common power supply terminals of the corridor. This reference voltage v1- is also at a high level (the zero level of the positive and negative pulses supplied to the transistors TRI and TRm).

As mentioned above, when the signal is 0, there is no signal, both transistors TRI and TRm are in the Kll off state. Therefore, the collector losses PCI and PCs of the transistors TRI and TRm become zero, as shown in FIG. Although current flows through transistors TR, gK,
Since s is for generating the reference voltage v1-, the values of its current flow and collector loss PCs are extremely small.

Now, when a positive pulse (.) shown in FIG. 6 is supplied from the output terminal E of the job-specific circuit DC to the pace of the transistor TRλ, the positive level of the positive pulse (.) becomes the reference voltage, voltage v1.
-, the transistor TR1 is turned on], and a positive pulse current Lx flows from the power supply +Vts to the primary coil t1 of the transformer TD in the direction shown. At this time, as shown in the 61st figure, the transistor TRz1m; rector loss PC1 occurs, but the transistor TRs
There is even a trench in the state of line breakage, so the collector loss PCm
is zero. In addition, the positive pulse current circuit, the common circuit of the transistor TRx and the TR nose (the voltage Vm is the base voltage of the transistor TRa, that is, the reference voltage Vma
When O reaches a very high level, the transistor TRi enters a fast-acting state, and its current Ia and collector loss become zero as shown in FIG.
Next, when a negative pulse (A) shown in FIG. 6 is supplied from the output terminal F of the discrimination circuit DC to the pace of the transistor TRs, the positive level of the negative pulse (A) is higher than the reference voltage Vms. Therefore, the transistor TRs is turned on, and a negative pulse current Is flows from the source +VB to the primary coil As of the transformer Tf) in the direction shown. At this time, transistor TR exposure (K - collector loss PC) occurs, but transistor TRx and Tag Fi are turned off, and their currents Ix, Is and collector loss PCz
, PCI both become zero.

- The positive polarity pulse signal 11 flowing in the primary coil t1 and the polarity pulse signal l flowing in the primary coil t1 are in opposite directions), and the secondary coil As O output terminal Gl of the transformer T is shown in Figure 6. The original PCM signal will be reproduced as shown in ”B;15 In this way, the reproduction circuit 8σ
In this case, the transistor TRI or TR is turned on only when a positive polarity pulse ←) or a negative polarity pulse is supplied from the identification circuit DC to the regeneration path RC', and when there is no signal, the transistors TRz and TRs are turned on. Since the condition is
The collector loss of transistors TR1 and TRm can be reduced to zero when there is no signal.The current and collector loss of transistor TRa are extremely small, so there is no risk of deterioration in reliability even if the on state continues for a long time. . Therefore, the loss when there is no signal in the entire reproducing circuit Rσ becomes extremely small. Next, when the PCM signal is not received, the output of the identification circuit DC is set to zero, that is, the output terminals E and FK.
The configuration and operation for bringing the generated positive and negative polarity pulses (e) and (a) to zero level will be described. In FIG. 1, the identification circuit bc normally generates positive polarity pulses (→ and negative polarity pulses) by two D-type flip allots FFλ and FF*, respectively, and converts these pulsed clock pulses CK into a NOR circuit N0RI, After inputting to N0R2 and performing RZ conversion on both pulses, output layer 1. The configuration is such that free kicks occur. So no signal detection circuit N8D
By detecting whether or not a PCM signal is received from K and generating a 7-bit signal at its output terminal H, the two 079 and 70 tubes (not shown) in the discrimination circuit DC' are reset. , its output terminals E and F can both be set to zero level. Whether or not a PCM signal is received can be determined by detecting the output of the equalizer IQ as shown by the dotted line.
A five-way connection using the output of C is a PC.
Since the timing signal is generated at a high level and at a uniform level only when the M signal is received, it is possible to effectively detect whether or not the PCM signal 0 is received. Figure 8 shows one embodiment of the no-signal detection circuit NOD. The diodes DI, DI and the antennas Cλ, Cm form a peak detector, whose output is applied to one λ terminal of the comparator COM.

The output (6) or (0) of the diverging IIITC or equalization amount BQ is supplied to the input terminal of the ♂ detector, that is, the input terminal of the no-signal detection circuit NSD. The cross-reference voltage Vso is supplied to the input terminal. When the reference voltage Vso is input with a large tkυL signal, the output level of the peak detector is smaller than the output level of the peak detector when there is no signal. The comparator COM generates the HK reset signal at its output when the output level of the peak detector is smaller than the reference voltage Vsc, i.e. when no PCM signal is being received. hand,
As explained above, according to the present invention, with an extremely small number of parts and circuit configuration, the output 2 of the reproduction circuit can be reset when no PCM signal is received. ? 1K i!
! I? L? :1 v/I @caro i□d
81, it is possible to maintain all axis properties for regeneration over a long period of time. Then, it is possible to reduce the loss of the entire seven pcM regenerative relay circuit, simplify the configuration, and improve reliability.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional PCM regenerative repeater circuit - Figure 2
Figure 1 is an explanatory diagram of the operating state; Figure 3 is an example of a regeneration circuit diagram for a regeneration circuit; Figure 1 is a block diagram of the PCM regeneration relay circuit of the present invention; Figure 5 is a diagram of the regeneration circuit of the present invention. 1 example, Figure 6 is an example of the company's No. 4 detection circuit N8D. L>, Ls is a transmission line, EQ is an equalizer,
TC is a tie construction circuit, DC is an identification circuit, RC, RC'
N8D is a regeneration circuit, N8D is a no-signal detection circuit, an 8VGa reference voltage generation circuit, a COMa comparator, and PRC is a PCM regeneration relay circuit. Patent applicant Fujitsu Ltd. Representative patent attorney Akira Yamatani Hata t2sen 287- 3W1 1hi2

Claims (1)

[Claims] (1) A no-signal detection circuit that generates a control signal when a PCM signal is not received; The polarity of each pulse constituting the received *PCM signal is divided into high-level 1f) RZO/'' pulse signals and a second RZ signal corresponding to the polarity of each pulse.
A discrimination circuit that generates a pulse signal and generates a low level output upon receiving a control signal from the no-signal detection circuit, and a regeneration circuit that receives the output of the discrimination circuit and reproduces the PC-M signal. and a tenth semiconductor element in which the regeneration circuit is turned into a positive polarity pulse signal by the first pulse signal, and is turned off when the second pulse signal and a low level output are supplied. and a second semiconductor element which is turned on by the second pulse signal to generate a negative polarity/cell signal and is turned off when the first pulse, signal and low level output are supplied. A PCM regeneration relay circuit characterized by nine functions.