JPS5848441A - Electron circuit device - Google Patents

Electron circuit device

Info

Publication number
JPS5848441A
JPS5848441A JP14544781A JP14544781A JPS5848441A JP S5848441 A JPS5848441 A JP S5848441A JP 14544781 A JP14544781 A JP 14544781A JP 14544781 A JP14544781 A JP 14544781A JP S5848441 A JPS5848441 A JP S5848441A
Authority
JP
Japan
Prior art keywords
conductor pattern
electron circuit
chip
electrode
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14544781A
Other languages
Japanese (ja)
Inventor
Norio Isshiki
Masatoshi Tanaka
Seiji Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP14544781A priority Critical patent/JPS5848441A/en
Publication of JPS5848441A publication Critical patent/JPS5848441A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE:To simplify the manufacturing process of the title device and to obtain a solid structure, excellent waterproof and humidity resistance properties for the device by a method wherein an IC chip is directly adhered on a conductor pattern using die-bonding and the like, and an IC electrode and the finger of the conductor pattern are coupled using a wire-bonding. CONSTITUTION:An IC chip 6 is die-bonded on the gold-plated layer 5 of the trapezoidal part 3 of the conductor pattern using an Au-Si eutectic material or a conductive bonding agent 8. Then, each electrode of the IC chip 6 and the finger part 2 of the conductor pattern corresponding to said electrode are wire- bonded using a gold or aluminum wire 7, and then a necessary electron circuit is formed on an insulating film 1 by attaching or forming a required electron circuit constituting element. Then, the processed insulating film 1 is folded back in the center part, and sealed by the same bonding agent 12 which was used on the peripheral region of the insulating film 1 or by performing thermal-press welding in such a manner that the electron circuit part will be enveloped.
JP14544781A 1981-09-17 1981-09-17 Electron circuit device Pending JPS5848441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14544781A JPS5848441A (en) 1981-09-17 1981-09-17 Electron circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14544781A JPS5848441A (en) 1981-09-17 1981-09-17 Electron circuit device

Publications (1)

Publication Number Publication Date
JPS5848441A true JPS5848441A (en) 1983-03-22

Family

ID=15385430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14544781A Pending JPS5848441A (en) 1981-09-17 1981-09-17 Electron circuit device

Country Status (1)

Country Link
JP (1) JPS5848441A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160145A (en) * 1984-01-30 1985-08-21 Mitsubishi Electric Corp Packaging method of hybrid integrated circuit
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JPS60160145A (en) * 1984-01-30 1985-08-21 Mitsubishi Electric Corp Packaging method of hybrid integrated circuit

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