JPS5848441A - Electron circuit device - Google Patents

Electron circuit device

Info

Publication number
JPS5848441A
JPS5848441A JP14544781A JP14544781A JPS5848441A JP S5848441 A JPS5848441 A JP S5848441A JP 14544781 A JP14544781 A JP 14544781A JP 14544781 A JP14544781 A JP 14544781A JP S5848441 A JPS5848441 A JP S5848441A
Authority
JP
Japan
Prior art keywords
insulating film
conductor pattern
chip
electronic circuit
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14544781A
Other languages
Japanese (ja)
Inventor
Norio Isshiki
功雄 一色
Masatoshi Tanaka
正敏 田仲
Seiji Takeuchi
武内 省二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP14544781A priority Critical patent/JPS5848441A/en
Publication of JPS5848441A publication Critical patent/JPS5848441A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE:To simplify the manufacturing process of the title device and to obtain a solid structure, excellent waterproof and humidity resistance properties for the device by a method wherein an IC chip is directly adhered on a conductor pattern using die-bonding and the like, and an IC electrode and the finger of the conductor pattern are coupled using a wire-bonding. CONSTITUTION:An IC chip 6 is die-bonded on the gold-plated layer 5 of the trapezoidal part 3 of the conductor pattern using an Au-Si eutectic material or a conductive bonding agent 8. Then, each electrode of the IC chip 6 and the finger part 2 of the conductor pattern corresponding to said electrode are wire- bonded using a gold or aluminum wire 7, and then a necessary electron circuit is formed on an insulating film 1 by attaching or forming a required electron circuit constituting element. Then, the processed insulating film 1 is folded back in the center part, and sealed by the same bonding agent 12 which was used on the peripheral region of the insulating film 1 or by performing thermal-press welding in such a manner that the electron circuit part will be enveloped.

Description

【発明の詳細な説明】 本発明はハイブリッドICによる!子回路装置に係わる
[Detailed Description of the Invention] The present invention is based on a hybrid IC! Related to child circuit devices.

従来9ハイブリツドIC製造、技術は自動車8やオート
バイ等の機械的、化学、的、気象、轡件的等あらゆる過
酷な環境でも高度の信頼性をもって5使用される電子回
路装置の、製造酋術としては未だ充分に開発されていな
かった。    、 、本発l!j1はかかる過酷な環
境にも充分耐えるハイブリッドICEよる電子回路−置
を提供す兎こと、金目的とすそ・     、 最近のハイブリッドエC製造技術に?ける能!I:IL
子の組立実装≦おいては、フィルムキャリヤ方式が知ら
むている。この方式は: (1)素子組立後に電気的試
験ができること、(2)基板に実装する際に基!上で占
有する面積を少くすることができること、等の利点tも
?ものである。こ9方式では通常I C,テップの電極
、部にバング   。
Conventional 9 hybrid IC manufacturing technology is a manufacturing technique for electronic circuit devices that are used with a high degree of reliability in all kinds of harsh environments such as automobiles and motorcycles, including mechanical, chemical, physical, weather, and accidental environments. has not yet been fully developed. , , this is the first one! J1 is a rabbit that provides electronic circuits using hybrid ICE that can withstand such harsh environments, and the latest hybrid ICE manufacturing technology? Keru Noh! I:IL
For child assembly and mounting, the film carrier method is well known. This method is based on: (1) ability to conduct electrical tests after device assembly; There are also advantages such as being able to reduce the area occupied by the top. It is something. In this 9 method, there is usually a bang in the IC, tip electrode, and part.

(突起電′I!り加工をしなければならすこの加工が容
扁でない理由惠あpて、あtb普及されていない。本発
明はフィルムチャリヤ方式を改良したものであって1.
従来の電子回−組1文技術のダイlンデイダ 9、ワイ
ヤlンデング等の組立技術はそのま\用い、加工が困難
なICチップの電極部のバンプ加工を使用しないで、自
動車等の厳しい環境で使用される機緘的に堅牢でかつ耐
候性、耐水性、耐湿性のある電子回路装置t−製造する
ことに成功したものである。
(It is necessary to perform a process to remove the protrusions. Unfortunately, this process is not very compact, and therefore, ATTB has not been widely used.The present invention is an improvement on the film carrier method.1.
Conventional electronic circuit assembly techniques such as assembly techniques such as die assembly 9 and wire assembly are used as they are, and the difficult-to-process bump processing of the electrodes of IC chips is not used, making it suitable for use in harsh environments such as automobiles. We have succeeded in producing electronic circuit devices that are mechanically robust, weather resistant, water resistant, and moisture resistant for use in.

本発明による電子回路装置をその製造方法とともに図面
に従って説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An electronic circuit device according to the present invention and a manufacturing method thereof will be explained with reference to the drawings.

at図、!2図、第3図は本発明の一実′に例に係る電
子回路装置の製造方法t−説明する説明図である。第1
図は本発明による電子回路装置の本体を形成するキャリ
ヤ用絶縁フィルム1の平面図であシ、絶縁フィルム1は
25〜ZQOμ程度の厚さを有するポリイミド勢の可撓
性フィル!であって、該絶縁フィルム10片面あるいは
両面に従来のフレキシブルプリント基板上に導体パター
ンを形成する技術によって所望の導体パターン、ICの
電極(接続されるフィンガ一部2.ICチップを乗せる
台部分3.電磁シールドの役割をもつ部分4等を形成す
る。次いでこれら導体)4ターンの台部分3.フィンガ
一部2の先端部には金あるい拡銀めっき5を施す。
AT diagram! 2 and 3 are explanatory diagrams illustrating a method of manufacturing an electronic circuit device according to an example of the present invention. 1st
The figure is a plan view of an insulating film 1 for a carrier forming the main body of an electronic circuit device according to the present invention, and the insulating film 1 is a flexible polyimide film having a thickness of about 25 to ZQOμ! By forming a conductor pattern on one or both sides of the insulating film 10 using a conventional technique of forming a conductor pattern on a flexible printed circuit board, a desired conductor pattern, an IC electrode (finger part 2 to be connected, a base part 3 on which an IC chip is placed) are formed. .Form the part 4 etc. that plays the role of electromagnetic shielding.Next, form the base part 3 with 4 turns of these conductors). The tip of the finger part 2 is plated with gold or expanded silver 5.

次に第2図は第1図に示す絶縁フィルムの断面図であっ
て、#r2図によって本発明を更に説明する。導体パタ
ーンの台部分3の金めっき層5の上K Au−8i共晶
体あるいは導電性接着剤8を用いてICチップ6t−グ
イデンデングする。
Next, FIG. 2 is a sectional view of the insulating film shown in FIG. 1, and the present invention will be further explained with reference to FIG. #r2. An IC chip 6t is glued onto the gold plating layer 5 of the base portion 3 of the conductor pattern using KAu-8i eutectic or conductive adhesive 8.

次いでICチップ6の各電極とこれに対応する導体パタ
ーンのフィンガ一部2との間を金やアルミニウムのワイ
ヤ7を用いてワイヤがンデングで接合し、更に電極間は
必要な電子回路構成要素を取付けあるいは形成して8R
フイルム1の上に必要な電子回路を形成する。なお、9
は導体・・′ターンの接着剤である。
Next, each electrode of the IC chip 6 and the corresponding finger portion 2 of the conductor pattern are bonded using gold or aluminum wire 7, and necessary electronic circuit components are connected between the electrodes. Install or form 8R
A necessary electronic circuit is formed on the film 1. In addition, 9
is the adhesive for the conductor...'turn.

次いで加工された絶縁フィルム1をその中央で折9返え
し、電子回路部分を包み込むように、熱圧着−2えは絶
縁フィルムlの周辺に塗布された接着剤12によって、
第3図に示す如く封止する。絶縁フィル□ム1の右半分
は電磁シールド4が形成されているため電子回路部分を
電磁的に遮蔽することができる。尚、絶縁フィルムを折
返す場合、電磁シールド4がIC電極等に触れない様に
、別の絶縁フィルム10、あるいは絶縁性発泡シートあ
るいはシリコン樹脂などを介在させる。特に電磁シール
ドを必要としない場合は絶縁フィルムだけで封止する。
Next, the processed insulating film 1 is folded 9 times in the center, and thermocompression bonding 2 is carried out using adhesive 12 applied around the periphery of the insulating film 1 so as to wrap around the electronic circuit part.
It is sealed as shown in FIG. An electromagnetic shield 4 is formed on the right half of the insulating film 1, so that the electronic circuit portion can be electromagnetically shielded. Note that when folding the insulating film, another insulating film 10, an insulating foam sheet, a silicone resin, or the like is interposed so that the electromagnetic shield 4 does not touch the IC electrodes or the like. In particular, if electromagnetic shielding is not required, seal with just an insulating film.

このようにして作った絶縁フィルム1で封止した電子回
路装置は、第3図に示す如く絶縁性基板15上に実装さ
れる。つまり、電子回路装置の電極部と、これに対応し
て絶縁性基板15上にあらかじめ設けられた導体配線部
14とを絶縁フィルム1に設けられ友穴11を介して・
・ンダ付け13で接合する。第3図は本発明による電子
回路装置の一実施例の断面金示す。なお、16′は抵抗
等の素子である。
The electronic circuit device sealed with the insulating film 1 thus produced is mounted on an insulating substrate 15 as shown in FIG. That is, the electrode portion of the electronic circuit device and the corresponding conductor wiring portion 14 provided in advance on the insulating substrate 15 are connected through the hole 11 provided in the insulating film 1.
・Join with soldering 13. FIG. 3 shows a cross-sectional view of an embodiment of an electronic circuit device according to the present invention. Note that 16' is an element such as a resistor.

以上の説明において、絶縁フィルム1と基板15との接
合は第3図に示す如く絶縁フィルム1に設けられた穴1
1を介したハンダ付けであったがこの外に、第4図に示
す如く、導体・クターンを電極部フィンガー2に対応し
て裏面にもフィンガー2′ヲ形成し両フィンガ一部を穴
11を介してスルーホールメッキを行って導体結合し、
下側の導体ノ臂ターンと基板15上に形成された導体配
a軒14との間tノ・ンダ付けすることもできる。
In the above explanation, the bonding between the insulating film 1 and the substrate 15 is carried out through holes 1 provided in the insulating film 1 as shown in FIG.
1, but in addition to this, as shown in Fig. 4, fingers 2' were formed on the back side of the conductor in correspondence with the electrode finger 2, and a hole 11 was formed in a part of both fingers. Through-hole plating is performed to connect conductors,
It is also possible to connect the lower conductor arm turn and the conductor arrangement eaves 14 formed on the substrate 15.

本発明によれば、フィルムキャリY方式におけるICチ
ップの電極部でのパシプ加工管必要とせず、導体パター
ンの上に直接ICチツft″ダイ〆ンド等で接着し、I
C電極と導体パターンのフィンガーとtワイヤがンドで
結合するため、製造工程が簡略化されると共に従来のフ
ィルムキャリヤ方式でIC部分を樹脂でモールドしてい
た加工が不必要となり、フィルムキャリヤ方式で形成さ
れ光ICt更に別の電子回路に組込む作業も不用となっ
た。また、本発明によればキャリヤ用の絶縁フィルムの
上に電子回路が形成され、この絶縁フィルムが密封にも
利用されるため、作業工程が短縮され且つ構造”的に堅
牢であって、防水・紡湿上勝れた構造の電子回路を安価
に提供すふことができるようになった。
According to the present invention, there is no need for a pipe-processed tube at the electrode part of the IC chip in the film carry Y method, and the IC chip is directly bonded onto the conductor pattern using a die-end or the like.
Since the C electrode, the conductor pattern finger, and the T wire are bonded together, the manufacturing process is simplified and the process of molding the IC part with resin in the conventional film carrier method is no longer necessary. The work of incorporating the formed optical IC into another electronic circuit is also no longer necessary. Furthermore, according to the present invention, an electronic circuit is formed on the insulating film for the carrier, and this insulating film is also used for sealing, so the work process is shortened and the structure is robust, waterproof and waterproof. It has become possible to provide electronic circuits with superior structures at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明に係り、第1図は導体パターンを形成した絶
縁フィルムの一例を示す平面図、第2図はその断面図、
第3図は電子回路装置の一例の断面図、t7g4図はス
ルーホールを用いた実施例の断面図である。 図面中、 1は絶縁フィルム、 2はICチップの電極に対するフィンガ一部、2′ハス
ルーホールでのフィンガーξP、3はICチップに対す
る台部分、 4は電磁シールド用の導体/臂ターン、5はメッキ層、 6はICチップ、 6′は電子回路構成要素、 7はワイヤ、 8はグイボンディング用接着剤、 9は導体パターンの接着剤、 10は他の絶縁フィルム、 11は絶縁フィルム19穴、 12は封止用の接着剤、 14は基板15の導体配線部、 15は絶縁性基板である。 特許出願人 住友電気工業株式会社 代理人弁理士  光 石 士 部 (他1名)第1図 第2図 第3図 第4図
The figures relate to the present invention; FIG. 1 is a plan view showing an example of an insulating film on which a conductive pattern is formed; FIG. 2 is a cross-sectional view thereof;
FIG. 3 is a sectional view of an example of an electronic circuit device, and FIG. t7g4 is a sectional view of an embodiment using through holes. In the drawing, 1 is an insulating film, 2 is a part of the finger for the electrode of the IC chip, 2' is the finger ξP in the through hole, 3 is the base part for the IC chip, 4 is the conductor/arm turn for electromagnetic shielding, and 5 is the part of the finger for the electrode of the IC chip. plating layer, 6 is an IC chip, 6' is an electronic circuit component, 7 is a wire, 8 is an adhesive for bonding, 9 is an adhesive for a conductive pattern, 10 is another insulating film, 11 is an insulating film 19 holes, 12 is a sealing adhesive, 14 is a conductor wiring portion of a substrate 15, and 15 is an insulating substrate. Patent Applicant: Sumitomo Electric Industries, Ltd. Representative Patent Attorney: Shibu Mitsuishi (and 1 other person) Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁フィルムや片面あるいは両面江導体パターン
を形成し、この導体ノ譬ターン上にICチップ會接着し
てこのICチップの電極点前記導体ピターンの該当する
部分と全ワイヤがイfインダによシ結線すると共に必賛
な電子回路構成要素を取付けて電子回蹄を形成9、前記
絶縁フィル台の−2部を折返して絶縁フィルムの周縁ど
うし1m着するととKよシ前配電子回路部分を封止して
なる電子回路装置。
(1) Form an insulating film or conductor pattern on one or both sides of the conductor pattern, adhere the IC chip on the conductor pattern, and connect the electrode points of the IC chip to the corresponding part of the conductor pattern and all the wires. Connect the wires and attach the necessary electronic circuit components to form the electronic circuit 9. Fold back the -2 part of the insulation film base and attach the periphery of the insulation film 1 m apart, and the front electronic circuit part will be formed. An electronic circuit device that is sealed.
(2)上記絶縁フィルムの折り44れる部すに、シール
ド用や導体I譬ターンを形−成しであることt特徴とす
る特許請求の範囲第1項記載の電子回路装、置。  、
        、
(2) An electronic circuit device according to claim 1, characterized in that a shielding or conductor I-turn is formed on the folded portion of the insulating film. ,
,
JP14544781A 1981-09-17 1981-09-17 Electron circuit device Pending JPS5848441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14544781A JPS5848441A (en) 1981-09-17 1981-09-17 Electron circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14544781A JPS5848441A (en) 1981-09-17 1981-09-17 Electron circuit device

Publications (1)

Publication Number Publication Date
JPS5848441A true JPS5848441A (en) 1983-03-22

Family

ID=15385430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14544781A Pending JPS5848441A (en) 1981-09-17 1981-09-17 Electron circuit device

Country Status (1)

Country Link
JP (1) JPS5848441A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160145A (en) * 1984-01-30 1985-08-21 Mitsubishi Electric Corp Packaging method of hybrid integrated circuit
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JPS60160145A (en) * 1984-01-30 1985-08-21 Mitsubishi Electric Corp Packaging method of hybrid integrated circuit

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