JPS5848439A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5848439A
JPS5848439A JP14676481A JP14676481A JPS5848439A JP S5848439 A JPS5848439 A JP S5848439A JP 14676481 A JP14676481 A JP 14676481A JP 14676481 A JP14676481 A JP 14676481A JP S5848439 A JPS5848439 A JP S5848439A
Authority
JP
Japan
Prior art keywords
film
oxide film
vapor
silicon oxide
silica
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14676481A
Other languages
Japanese (ja)
Inventor
Hiroshi Ishioka
石岡 浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14676481A priority Critical patent/JPS5848439A/en
Publication of JPS5848439A publication Critical patent/JPS5848439A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain the interlayer insulating film having excellent dampproof property, reliability and patterning property of aluminum wiring layer by a method wherein on a film such as a silica film, for example, a structure on which a silicon oxide film or a phosphosilicate glass film thicker than the above film is grown by performing a vapor-phase growing method or a plasma growing method. CONSTITUTION:The silicon oxide film 8 or a low density PSG film which is thicker than the silicon film is grown in approximately 1mum thickness by performing a vapor-phase growing method. The silicon oxide film formed by a vapor-phase growing method lacks uniformity in its film thickness due to the shape of the underlying layer and the more the stepping becomes larger, the more the nonuniformity of the film thickness is generated, but as a lessening (flattening of a step) of the stepping has been performed by a silica film, the silica oxide film 8 of uniform surface can be grown. As the silica oxide film formed by a vapor-phase growing method lacks density, a control hole is bored by performing a photoresist processing after a heat treatment, an aluminum vapor-deposition is then performed, and an element is formed by patterning the aluminum wiring 9 performing a photoresist processing.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置に係り、特にその層間絶縁
膜の構造に圓するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of an interlayer insulating film thereof.

眉間絶縁膜としては、熱酸化法による酸化珪素膜や気相
成長法による酸化珪素膜、あるいは気相成長法によるリ
ン珪酸ガラス膜等が用いられるが、素子寸法の微細化に
伴い、リン珪酸ガラスが熱処理時に軟化し、流動性を持
つ事i利用して、段差を緩和するために、リン濃度の高
い(pzOsの重量モル濃度がlQmol−以上)リン
珪酸ガラス(以下高濃度PEGと称す)が使用される事
が多い・しかし、高濃度PSGの上にアルミニウム配線
を形成した構造は耐湿性i劣る。これは、外部から水分
の浸透があると、高濃度PSGと水とによって、リン酸
(H3PO3)が発生し、アルミニウムを腐蝕させこの
アルミニウムの断線をおこすためでおる。従って、この
構造を用いた場合、素子のパッケージには水分の浸透が
極めて少ない材質(例えばセラミック系のもの)を用い
なゆれば、高信頼性を保証出来ない。また、゛製造コス
トを下げるためには高価なセラミックパッケージよりも
廉価なプラスチックパッケージを使うことが望ましいが
プラスチックパッケージ轄水分の浸透があるため、素子
自体の耐湿性が高くないと使用することは出来ない。し
たがって、素子自体の耐湿性を高めるためには前記の高
濃度psg4の上にアルミニウム配線を形成する構造を
使用するべきではない、=。
As the glabellar insulating film, a silicon oxide film formed by thermal oxidation, a silicon oxide film formed by vapor phase growth, or a phosphosilicate glass film formed by vapor phase growth are used, but as device dimensions become smaller, phosphosilicate glass Phosphorusilicate glass (hereinafter referred to as high-concentration PEG) with a high phosphorus concentration (the molar concentration of pzOs is 1Q mol- or more) is used to alleviate the level difference by taking advantage of the fact that it softens during heat treatment and has fluidity. It is often used. However, the structure in which aluminum wiring is formed on high concentration PSG has poor moisture resistance. This is because when moisture penetrates from the outside, phosphoric acid (H3PO3) is generated by the highly concentrated PSG and water, corroding the aluminum and causing wire breakage in the aluminum. Therefore, when this structure is used, high reliability cannot be guaranteed unless the element package is made of a material (for example, ceramic) that allows very little moisture to penetrate. Furthermore, in order to reduce manufacturing costs, it is desirable to use inexpensive plastic packages rather than expensive ceramic packages, but since moisture can penetrate into plastic packages, they cannot be used unless the device itself has high moisture resistance. do not have. Therefore, in order to improve the moisture resistance of the element itself, the structure in which aluminum wiring is formed on the high concentration psg4 should not be used.

、このような各点t−竺ぐためには、高I11度P、委
GO上に一濃度PEG(前記P2O5の重量モル濃度が
4′〜5ThOJ%)または気相成長法による酸化膜 
′素膜を重ねた構造にしても目的は達せられる。しかし
リン濃度が高いほど、バッフアートフッ歌でのエッチレ
ートが大きいため、コンタクトホール開孔から7.ルミ
ニ、ラム−蒸着−を行う前までの工程で、バッ7アード
フシ酸を用いると、上層の酸化珪素膜よシ下層の高濃度
PEGのサイドエッチが大きく、オーバーハングを生じ
、アルミニレムの段切れを起すため適当な方法ではない
。また、低濃度PSGのみで絶縁膜を艙成すると、低濃
度PSGは、高濃度PSGに比べ熱処理時の軟化ケ起こ
しにくいが、高圧酸化法を用いて低濃度PSGに軟化を
起こさせ段差の緩和を計る事は出来る・しかし、低濃度
PEGの軟化は高濃度PSG全使用した賜金はど十分に
は起らす十分な段差緩和の効果は得られない。そのうえ
、この場合にはポリシリコン等で形成し九他の配線層も
同時に酸化される丸め、層抵抗の上昇が引き起こされる
など、高圧酸イ、ヒ法の他の特性への影響が大きい。
, in order to measure the temperature at each point, it is necessary to apply a monoconcentration of PEG (the molar concentration of P2O5 is 4' to 5ThOJ%) or an oxide film by vapor phase growth on the high I11 degree P.
'The purpose can be achieved even if the structure is made up of layers of elementary films. However, the higher the phosphorus concentration, the higher the etch rate during buffering, so the 7. If buffered fusic acid is used in the steps before Lumini and Lamb evaporation, the side etch of the upper layer silicon oxide film and the lower layer of high concentration PEG will be large, resulting in overhang and breakage of the aluminum layer. This is not an appropriate way to wake up. In addition, if an insulating film is formed using only low concentration PSG, the low concentration PSG is less prone to softening during heat treatment than high concentration PSG, but high pressure oxidation is used to soften the low concentration PSG and alleviate the step difference. However, the softening of low-concentration PEG does not occur as much when all high-concentration PSG is used, but a sufficient effect of alleviating the level difference cannot be obtained. Moreover, in this case, other wiring layers formed of polysilicon or the like are also oxidized at the same time, resulting in rounding and an increase in layer resistance, which greatly affects other characteristics of the high-pressure acid method.

1中 珪素化合物を有機溶剤に溶かしたもので、これをスピン
塗布又祉ディップ塗布した後、熱処理を加えて酸化珪素
膜を焼成するものである。液体であ、るために、適当な
粘度のものを選ぶことに゛よ一ヤ効  −果的に段差を
緩和する事が出来る。このシリカフィルムを厚く塗布す
る事によって層間絶縁膜を形成することも可能であるが
、′厚く撒布すると焼成中にクララ−り−tz(発生し
易くなる。)ラックが発生したシリカフィルムは層間絶
縁膜としての役目を果たさなくなる。従りて、シリカフ
ィルムだけで層間絶縁膜を形成するのは安定した製造を
行うためには好ましくない。
A silicon oxide film is prepared by dissolving a silicon compound in an organic solvent, which is applied by spin coating or dip coating, and then subjected to heat treatment to bake a silicon oxide film. Since it is a liquid, choosing a material with an appropriate viscosity can more effectively alleviate differences in level. It is also possible to form an interlayer insulating film by applying this silica film thickly, but if it is spread too thickly, cracks will easily occur during firing. It no longer functions as a membrane. Therefore, forming an interlayer insulating film using only a silica film is not preferable for stable manufacturing.

本発明は、以上の欠点を解決し充分な段差緩和効果を得
たうえ耐湿性が−良く信頼性も高くする事が出来る構造
の層間絶縁膜を有する半導体集積回路装置を提供するも
のである。  2 本発明の特徴は、二層以よQ配線層を持?士導体集、積
回路装置において層間絶縁膜として、!布、−焼成法で
2形成した酸化ヰ素2を主成盆ト、する被膜例えばシリ
カフィル÷の上に5、気相成長睦するいは、4プラズマ
成長法、によシ、こOシ膜よシ厚く酸化珪素膜束たはリ
ン珪酸ガ、う、不換4t−成長させた構造の絶縁膜を持
?半、導体集積回路装黒に、ある。
The present invention solves the above-mentioned drawbacks and provides a semiconductor integrated circuit device having an interlayer insulating film having a structure capable of achieving a sufficient level difference mitigation effect and also having good moisture resistance and high reliability. 2. The feature of the present invention is that it has two or more Q wiring layers. As an interlayer insulating film in conductor collections and integrated circuit devices! Cloth - A coating mainly composed of 2 carbon oxide formed by a baking method, for example, on a silica film by vapor phase growth or by a plasma growth method. Does it have an insulating film with a structure grown by thicker silicon oxide film or phosphorus silicate film? Semi-conductor integrated circuit black.

以下、本発明を実施例により51図面を用いて説明。す
る。Nチャネルシリ、コンゲートの絶斡ゲート型電界効
果トランジスタを例に挙げる。
Hereinafter, the present invention will be explained with reference to Examples and 51 drawings. do. An example is an N-channel silicon or congate insulated gate field effect transistor.

第1図:第1図情薄1nH,il!、化膜5を介してイ
オン注入法によ)ソース・ドレイン領域にN型不純物(
例えば砒*)t−注入しに拡散層子を、形成した時、4
.、q断丙図である。イオン注入は基q、上に薄い酸化
膜(成長したよから打ち込ま−れるのが普通であシ1.
この酸化膜厚は、注入原子の投影飛程(lip)よ)も
充分、に薄くなければなら3ない、。1、 7第く図ニ
ジリカフィルムをこの薄り酸些膜上に塗布し焼成した場
合シリカフィルム中に含まれる不純物が、半導1体基板
まで拡散され素子を劣化させる恐れがある。不純物の拡
散の影響をおさえるために、イオン注入の後で酸化を行
い、基板上に1000X程度の酸化膜6を成長させる・
 ゛第3図:次にシリカフィルム7を2000〜300
0久になるようにスピン塗布を行なう。シ4す、力フィ
ルろはその粘性と表面張力によって段差の下で厚く、上
で薄く塗布され段差を、緩和する。次にシリカフィルム
の熱処理を行、うが、クラック・音発生させないた吟に
は熱処理を二段階に行う必要がある。
Figure 1: 1st pictureless 1nH,il! N-type impurities (
For example, when forming a diffusion layer for arsenic*) t-implantation, 4
.. , q section C diagram. Ion implantation is usually done by implanting a thin oxide film (after it has grown) on the substrate.1.
The thickness of this oxide film must be sufficiently thin for the projected range (lip) of implanted atoms. If a rainbow silica film is coated on this thin oxidized film and fired, the impurities contained in the silica film may diffuse into the semiconductor single-piece substrate and deteriorate the device. In order to suppress the influence of impurity diffusion, oxidation is performed after ion implantation to grow an oxide film 6 of approximately 1000X on the substrate.
゛Figure 3: Next, apply the silica film 7 to 2,000 to 300
Spin coating is performed so that it lasts for 0 hours. 4. Due to its viscosity and surface tension, the filter is applied thickly at the bottom of the step and thinly at the top to soften the step. Next, the silica film is heat treated. However, in order to prevent cracks and sounds from occurring, it is necessary to perform the heat treatment in two stages.

第1段階は溶剤を揮発させ今とと瀘主目的であり、17
0℃〜200℃、の窒素又は臭気雰囲気で3q分以上の
熱処理を行う・第2段階社酸、化、珪素膜の焼成が目的
であり、1000°C以上の窒素雰囲気で30分以上の
熱処理を行う。以上、O勢処、理によ東、熱酸化法によ
る酸化珪、木馬に近い性2質を持つ酸化砒素膜を得る事
、が出来る。  、−1、、よ 1、第4図:次に、気
相成長、法によシ酸化珪素膜8あ今一は弊濃度P8GI
Ilを、rリカフィルムよシも厚く約1μm OJIさ
て成長、する。気相成長法にょる酸化珪素膜は、下地の
形状によシ、成長膜厚の均一性が変化し、段差が大きい
ほど膜厚ムラが生じやすいが、既にシリカフィルムによ
る段差の緩和(段ダラシ)が行われているため表面には
均一な酸化珪素膜8を成長させる事が出来る。
The first stage is to volatilize the solvent and remove it.
Heat treatment is carried out for 3 q minutes or more in a nitrogen or odor atmosphere at 0°C to 200°C. The purpose of the second stage is acid, chloride, and baking of the silicon film, and heat treatment is carried out in a nitrogen atmosphere of 1000°C or more for 30 minutes or more. I do. As described above, it is possible to obtain an arsenic oxide film having two properties similar to those of silicon oxide and a wooden horse by O-energization treatment and a thermal oxidation method. , -1,, 1. Figure 4: Next, a silicon oxide film 8A is grown using a vapor phase growth method at a concentration of P8GI.
Grow the Il to a thickness of about 1 μm using the Rica film. Silicon oxide films grown using the vapor phase growth method vary in uniformity in the thickness of the grown film depending on the shape of the underlying layer, and the larger the step, the more likely it is that uneven film thickness will occur. ), it is possible to grow a uniform silicon oxide film 8 on the surface.

第5図:気相成長法で被着した酸化珪素膜は、そのiま
では 密性に欠けるため、熱処理を加えたのちフォトレ
ジスト工程によってコンタクトホールを開孔し、アルミ
ニウム蒸着を行い、フォトレジスト工程によってアルミ
ニウム配!!9t−パターニングし素子を形成する。
Figure 5: The silicon oxide film deposited by vapor phase growth lacks density up to i, so after applying heat treatment, contact holes are opened using a photoresist process, aluminum evaporation is performed, and the photoresist is Aluminum layout depending on the process! ! 9t-Patterning to form elements.

なお、コンタクト開孔時にバッ7アードフッ酸によるエ
ツチングレートの違いでオーバーハングが発生するのを
防止するために、シリカフィルムにはリンなどの添加物
を含まないものを用い、その上に気相成長法で低濃度P
8Gを成長させるのが較果的である。
In addition, in order to prevent overhang from occurring due to the difference in etching rate due to buffered hydrofluoric acid when forming contact holes, a silica film that does not contain additives such as phosphorus is used, and vapor phase growth is performed on it. Low concentration of P
It is comparatively fruitful to grow 8G.

以上の方法によシ、耐湿性、信頼性およびアルミニウム
配線層のバターニング性に秀れた層間絶縁膜を得る事が
できる。
By the method described above, it is possible to obtain an interlayer insulating film that is excellent in moisture resistance, reliability, and patterning properties of aluminum wiring layers.

【図面の簡単な説明】[Brief explanation of the drawing]

+ 第1図は、ソースドレイン領域のべ拡散層3を形成した
あとの素子の断面図、第2図は、熱酸化法によシソ−ス
トレイン領域に酸化膜6を成長させた後の素子の断面図
、第3図は、シリカフィルム7を塗布し、熱処理を加え
たあとの断面図、第4図は、シリカフィルム上に気相成
長法によシ酸化珪素膜8を成長させたあとの断面図、第
5図は、アルミニウム配線のパターニングが終了した素
子の断面図、である。 々お図において、1・・・・・・シリコン基板、2・・
・・・・+ 選択酸化による熱酸化膜、3・・・・・・N拡散層、4
・・・・・・ポリシリコンのゲート電極、5・・・・・
イオン注入時の薄い酸化珪素膜、6・・・・・・熱酸化
法で追加形成した酸化珪素膜、7・・・・・・シリカフ
ィルム、8・・・・・・気相成長法で形成し九酸化珪素
膜、9・・・・・アルミニウム配線、である。 $svJ
+ Figure 1 is a cross-sectional view of the device after forming the base diffusion layer 3 in the source/drain region, and Figure 2 is a cross-sectional view of the device after the oxide film 6 has been grown in the source/drain region by thermal oxidation. 3 is a cross-sectional view after a silica film 7 has been applied and heat treated, and FIG. 4 is a cross-sectional view after a silicon oxide film 8 has been grown on the silica film by vapor phase growth. The cross-sectional view, FIG. 5, is a cross-sectional view of the element after patterning of the aluminum wiring has been completed. In the figures, 1... silicon substrate, 2...
...+ Thermal oxide film by selective oxidation, 3...N diffusion layer, 4
...Polysilicon gate electrode, 5...
Thin silicon oxide film during ion implantation, 6... Silicon oxide film additionally formed by thermal oxidation method, 7... Silica film, 8... Formed by vapor phase growth method 9...aluminum wiring. $svJ

Claims (1)

【特許請求の範囲】[Claims] 二層以上の配線層を持つ半導体集積回路装置において、
層間絶縁膜として、塗布−焼成法で形成した酸化珪素を
主成分とする被膜の上に、気相成長法、あるいはプラズ
マ成長法により、この被膜よシ厚く酸化珪素膜または(
す゛ン珪酸ガラス膜を成長させた構造の絶縁膜を有する
事を特徴とする半導体集積回路装・置。
In semiconductor integrated circuit devices with two or more wiring layers,
As an interlayer insulating film, a silicon oxide film or (
A semiconductor integrated circuit device/equipment characterized by having an insulating film having a structure in which a silicon silicate glass film is grown.
JP14676481A 1981-09-17 1981-09-17 Semiconductor integrated circuit device Pending JPS5848439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14676481A JPS5848439A (en) 1981-09-17 1981-09-17 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14676481A JPS5848439A (en) 1981-09-17 1981-09-17 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5848439A true JPS5848439A (en) 1983-03-22

Family

ID=15415030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14676481A Pending JPS5848439A (en) 1981-09-17 1981-09-17 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5848439A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208175A (en) * 1990-12-21 1993-05-04 Samsung Electronics Co., Ltd. Method of making a nonvolatile semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208175A (en) * 1990-12-21 1993-05-04 Samsung Electronics Co., Ltd. Method of making a nonvolatile semiconductor memory device

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