JPS5846643A - Treating method for wafer - Google Patents

Treating method for wafer

Info

Publication number
JPS5846643A
JPS5846643A JP14429481A JP14429481A JPS5846643A JP S5846643 A JPS5846643 A JP S5846643A JP 14429481 A JP14429481 A JP 14429481A JP 14429481 A JP14429481 A JP 14429481A JP S5846643 A JPS5846643 A JP S5846643A
Authority
JP
Japan
Prior art keywords
wafer
processing
uniformity
section
conditions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14429481A
Other languages
Japanese (ja)
Inventor
Kyusaku Nishioka
西岡 久作
Shinji Orisaka
伸治 折坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14429481A priority Critical patent/JPS5846643A/en
Publication of JPS5846643A publication Critical patent/JPS5846643A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve the uniformity of accuracy on processing in the wafer by mounting a plurality of nozzles spraying a developing liquid or an etching liquid and making the conditions of the treatment of these nozzles independent. CONSTITUTION:In the development of a resist film or the etching treatment of the semiconductor wafer, not only the nozzle 3 to the central section of the wafer 1 but also the nozzles 4 to a peripheral section are set up, and the conditions of the treatment of each nozzle are controlled independently while turning the wafer by means of a wafer chuck 7, thus remarkably improving the uniformity of accuracy on processing in the wafer. An automatic end point detector 5, which consists of a light emitting section 51 and a light receiving section 52 and measures the change of the reflectivity of the section to be treated, is mounted to the central section while a similar automatic end point detector 6 is set up to the peripheral section, the conditions of the treatment of the nozzles corresponding to each are automatically controlled, and uniformity can further be improved.

Description

【発明の詳細な説明】 この発明は、半導体装置などの製造工程におけるウェハ
処理法の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in wafer processing methods in the manufacturing process of semiconductor devices and the like.

集積回路は、ますます高集積化の請求が厳しく、パター
7の微細化が進んでいる。従来、広く量産技術として使
われて色た4真製版技術では、フォトレジストまたは電
子線レジストなどに霧光を行つた後に現像して、第1図
の断面図に示すように、例えば半導体のウェハ(1)上
に所定のパターンを有するレジスト膜(2)を形成し、
このレジスト膜(2)をマスクにして化学薬品またはガ
スプラズマを使ってウェハ(11の表面部をエツチング
して、第2図の断面図に示すように、ウェハ(1)に機
軸パターンを形成していた。現像工程およびエツチング
工程では、ウェハ25枚程度を1バツチとして一括に理
していたが、この方法でLウェハ間の加工精度が愁いた
め、最近ではウェハ1枚ずつ処理し、その処理終点検出
も、赤外光線、可視光線、紫外光線などの発光スペクト
ル、透過率、反射率などの変化により自動的に行う方法
に変わりつつある。このような方法をとればウェハ間の
均一性は確かに向上するが、ウェハ内の均一性は従来の
方法に比べてそれ程改善されない。
Integrated circuits are increasingly required to be highly integrated, and the pattern 7 is becoming increasingly finer. Conventionally, in the 4-press plate making technology, which has been widely used as a mass production technology, a photoresist or an electron beam resist is exposed to fog light and then developed to form a wafer, such as a semiconductor wafer, as shown in the cross-sectional view of Figure 1. (1) forming a resist film (2) having a predetermined pattern thereon;
Using this resist film (2) as a mask, the surface of the wafer (11) is etched using chemicals or gas plasma to form a vertical pattern on the wafer (1) as shown in the cross-sectional view of Figure 2. In the developing and etching processes, about 25 wafers were processed in one batch, but since this method had poor processing precision between L wafers, recently the wafers were processed one by one. End point detection is also changing to a method that is automatically performed based on changes in the emission spectrum, transmittance, reflectance, etc. of infrared light, visible light, ultraviolet light, etc. If such a method is used, uniformity between wafers can be improved. While this is certainly an improvement, the within-wafer uniformity is not significantly improved compared to conventional methods.

この発明L1ウェハを複数領域に分けそれらのそれぞれ
に対する処理条件を独立に制御することによって、ウェ
ハ内の加工精度の均一性を向上させることができるウェ
ハ処理法を提供することを目的としたもである。
The object of this invention is to provide a wafer processing method that can improve the uniformity of processing accuracy within the wafer by dividing an L1 wafer into a plurality of regions and independently controlling the processing conditions for each region. be.

以下、実施例に基づいてこの発明を説明する。The present invention will be explained below based on examples.

通常、ウェハ全面を同一条件で処理すると、ウェハの周
辺部と中心部とでは加工の進み具合が異なるため加工精
度のウェハ内の均一性が低下する。
Normally, when the entire surface of a wafer is processed under the same conditions, the progress of processing differs between the periphery and the center of the wafer, which reduces the uniformity of processing accuracy within the wafer.

そこで、実施例の方法では、第3図の断面図に示すよう
に、現像液またはエツチング液をスプレーするノズルと
してウェハ11+の中央部に対するノズル(3)のみな
らずウェハ0)の周辺部に対するノズル(411に設け
、ウェハ11)を回転するウェハチャック())で回転
させながらそれぞれの処理条件を独立に制御することに
より、ウェハ内の加工精度の均一性を格段に向上させる
ことができた。さらに、発光部(51)と受光部(52
)とからなり被処理部の反射率の変化を測定する自動終
点検出器+a+をウェハil+の中央部に対して設ける
と共に、発光部(61)と受光部(62)とからなる同
様の自動終点検出器(6)をウェハ[11の周辺部に対
して設け、それぞれに対応するノズルの処理条件を自動
的に制御するようにしたところ、ウェハ内の加工精度の
均一性をさらに一増向上させることが可能になった。
Therefore, in the method of the embodiment, as shown in the cross-sectional view of FIG. By independently controlling each processing condition while rotating the wafer 11 with a rotating wafer chuck ( ), it was possible to significantly improve the uniformity of processing accuracy within the wafer. Furthermore, a light emitting part (51) and a light receiving part (52
) is provided at the center of the wafer il+, and an automatic end point detector +a+ for measuring changes in the reflectance of the processed area is provided at the center of the wafer il+. By installing a detector (6) around the wafer [11] and automatically controlling the processing conditions of the corresponding nozzle, the uniformity of processing accuracy within the wafer is further improved. It became possible.

上記の実施例においては、ウェハの処理としてレジスト
膜の現像または半導体ウェハのエツチングを取りあげ、
現像液またはエツチング液をスプレーするノズルを1枚
のウェハに対して複数個設けそれらのノズルによる処理
条件を独立に制御して、ウェハ内の加工精度の均一性を
向上させる場合について述べたが、処理手段としては、
ノズルによるスプレーに限られるわけではなく、ウェハ
内の複数領域に対してそれぞれ別個の処理条件によって
処理で色るものであればよい。例えば成膜工程において
、ウェハ全面にわたり同一条件にて成膜する代りにウェ
ハを複数の領域に分け、各領域の膜厚を成膜処理中に膜
厚測定器によって検出しなから成膜条件を制御すること
によって、ウェハ内の膜厚の均一性を向上させることが
できるらまた、プラズマ′エツチングの場合、例えは、
ウェハの複数の領域に対してそれぞれ対向する複数のガ
ス導入口を設けれることによってこれらの複数の領域に
対するガス流量を独立に制御するとか、複数の領域に対
してそれぞれ対応する複数の電極を設けることによって
これらの複数の領域に対するRF’印加を力または放電
時間を独立に制御するとかすることによってウェハ内の
加工精度の均一性を向上させることができる。
In the above embodiments, development of a resist film or etching of a semiconductor wafer is taken up as the wafer processing.
We have described the case where a plurality of nozzles for spraying a developing solution or an etching solution are provided for one wafer, and the processing conditions by those nozzles are independently controlled to improve the uniformity of processing accuracy within the wafer. As a processing means,
The method is not limited to spraying using a nozzle, but may be any method that colors a plurality of areas within the wafer according to separate processing conditions. For example, in a film forming process, instead of forming a film under the same conditions over the entire wafer, the wafer is divided into multiple regions, and the film thickness of each region is detected by a film thickness measuring device during the film forming process, and then the film forming conditions are changed. In the case of plasma etching, for example, if the uniformity of film thickness within a wafer can be improved by controlling
By providing multiple gas inlet ports facing each other in multiple regions of the wafer, the gas flow rate to these multiple regions can be controlled independently, or by providing multiple electrodes corresponding to each of the multiple regions. By independently controlling the force or discharge time of RF' application to these multiple regions, it is possible to improve the uniformity of processing accuracy within the wafer.

また、終点検出器も、反射率の変化を検出する検出器に
限られるわけでなく、処理により変化する状aを−a数
の処理箇所において別個に検出できるものであれはよく
、例えばレーザビーム干渉法による検出器であってもよ
い。
Furthermore, the end point detector is not limited to a detector that detects changes in reflectance, but may be one that can separately detect the state a that changes due to processing at -a number of processing locations, such as a laser beam detector. It may also be an interferometric detector.

以上?述したように、この発明によるウェハ処理法にお
いては、ウェハを複数領域に分けそれらのそれぞれに対
する処理条件を独立圧制御するのテ、ウェハ内の処理の
均一性を向上させることがで龜る。      、
that's all? As described above, in the wafer processing method according to the present invention, the uniformity of processing within the wafer can be improved by dividing the wafer into a plurality of regions and independently controlling the processing conditions for each region. ,

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来の写真制版技術による微細パ
ターン形成法を説明するための断面図、第3図はこの発
明にょるウェハ処理法の一実施例を説明するための断面
図である。 図において、+11はウニノ1、(2)はレジ1ト膜、
(3)。 (4)はノズル、(5)、(6)は自動終点検出((7
)はウェハチャックである。 なお、図中同一符号はそれぞれ同一または相当部分を示
す。 代理人  葛 野 侶 −(外1名) 第1図 第2図 第3図
1 and 2 are cross-sectional views for explaining a fine pattern forming method using conventional photolithography technology, and FIG. 3 is a cross-sectional view for explaining an embodiment of a wafer processing method according to the present invention. . In the figure, +11 is Unino 1, (2) is Resist 1 film,
(3). (4) is a nozzle, (5) and (6) are automatic end point detection ((7)
) is a wafer chuck. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Tsutomu Kuzuno - (1 other person) Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 ill  ウェハを複数領域に分けそれらのそれぞれに
対する処理条件を独立に制御することによってウェハ内
の処理の均一性を向上させること′fr%徴とするウェ
ハ処理法。 (2)  ウェハの複数領域のそれぞれの処理状態全処
理中に独立に検出することによって上記複数領域のそれ
ぞれに対する処理条件を独立に制御することを特徴とす
る特許請求の範囲i11記載のウェハ処理法。
[Claims] ill A wafer processing method characterized by improving the uniformity of processing within a wafer by dividing a wafer into a plurality of regions and independently controlling processing conditions for each region. (2) The wafer processing method according to claim i11, characterized in that the processing conditions for each of the plurality of regions of the wafer are independently controlled by independently detecting the processing condition of each of the plurality of regions during all processing. .
JP14429481A 1981-09-12 1981-09-12 Treating method for wafer Pending JPS5846643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14429481A JPS5846643A (en) 1981-09-12 1981-09-12 Treating method for wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14429481A JPS5846643A (en) 1981-09-12 1981-09-12 Treating method for wafer

Publications (1)

Publication Number Publication Date
JPS5846643A true JPS5846643A (en) 1983-03-18

Family

ID=15358718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14429481A Pending JPS5846643A (en) 1981-09-12 1981-09-12 Treating method for wafer

Country Status (1)

Country Link
JP (1) JPS5846643A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60103830U (en) * 1983-12-20 1985-07-15 株式会社東芝 rotary developing device
US4559722A (en) * 1983-10-14 1985-12-24 New Balance Athletic Shoe, Inc. Construction of upper for athletic shoe
JP2002520850A (en) * 1998-07-09 2002-07-09 エーシーエム リサーチ,インコーポレイティド Method and apparatus for electropolishing metal interconnects on semiconductor devices
WO2007088755A1 (en) * 2006-01-31 2007-08-09 Sumco Corporation Single wafer etching method
JP2010056405A (en) * 2008-08-29 2010-03-11 Shibaura Mechatronics Corp Device and method for treating substrate
JP2016515300A (en) * 2013-02-28 2016-05-26 ビーコ プリジション サーフェイス プロセシング エルエルシー System and method for performing a wet etching process
CN109560012A (en) * 2017-09-25 2019-04-02 株式会社斯库林集团 Substrate processing device and Method of processing a substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5448170A (en) * 1977-09-26 1979-04-16 Hitachi Ltd End-point deciding device for etching

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5448170A (en) * 1977-09-26 1979-04-16 Hitachi Ltd End-point deciding device for etching

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4559722A (en) * 1983-10-14 1985-12-24 New Balance Athletic Shoe, Inc. Construction of upper for athletic shoe
JPS60103830U (en) * 1983-12-20 1985-07-15 株式会社東芝 rotary developing device
JP2002520850A (en) * 1998-07-09 2002-07-09 エーシーエム リサーチ,インコーポレイティド Method and apparatus for electropolishing metal interconnects on semiconductor devices
WO2007088755A1 (en) * 2006-01-31 2007-08-09 Sumco Corporation Single wafer etching method
JP4974904B2 (en) * 2006-01-31 2012-07-11 株式会社Sumco Single wafer etching method of wafer
US8466071B2 (en) 2006-01-31 2013-06-18 Sumco Corporation Method for etching single wafer
JP2010056405A (en) * 2008-08-29 2010-03-11 Shibaura Mechatronics Corp Device and method for treating substrate
JP2016515300A (en) * 2013-02-28 2016-05-26 ビーコ プリジション サーフェイス プロセシング エルエルシー System and method for performing a wet etching process
JP2019153803A (en) * 2013-02-28 2019-09-12 ビーコ プリジション サーフェイス プロセシング エルエルシー System and method for performing wet etching process
CN109560012A (en) * 2017-09-25 2019-04-02 株式会社斯库林集团 Substrate processing device and Method of processing a substrate
JP2019062007A (en) * 2017-09-25 2019-04-18 株式会社Screenホールディングス Substrate processing apparatus and substrate processing method
CN109560012B (en) * 2017-09-25 2023-06-09 株式会社斯库林集团 Substrate processing apparatus and substrate processing method

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