JPS5846621A - Epitaxial growth method of amorphous silicon or polycrystalline silicon on wafer - Google Patents
Epitaxial growth method of amorphous silicon or polycrystalline silicon on waferInfo
- Publication number
- JPS5846621A JPS5846621A JP56144693A JP14469381A JPS5846621A JP S5846621 A JPS5846621 A JP S5846621A JP 56144693 A JP56144693 A JP 56144693A JP 14469381 A JP14469381 A JP 14469381A JP S5846621 A JPS5846621 A JP S5846621A
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- Japan
- Prior art keywords
- wafer
- silicon
- temperature
- lamps
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はウェハー上のアモルファスシリコンもしくは多
結晶シリコンをエピタキシアル成長させる方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for epitaxially growing amorphous or polycrystalline silicon on a wafer.
上記方法については、既にいくつかの文献に紹介されて
いるとζろであるが、従来量も一般的な方法は、厚さ４
０００にのアモルフスシリコン（以下α−８４）の層を
、例えば６００℃の電気炉で約８０分間加熱する電気炉
法であるが、比較的長い時間の加熱なので、生産性の点
で実用的でない。ま企、温度を上げることによシ結晶成
畏速ｆは上昇するが、シリコンのウェハーＫ「反り」が
発生したシ、汚染されたり、したがって生産の歩留が悪
い等の欠点があり、最近ではレーザビームで短時間照射
する方法が研究されている。しかしながらこのレーザビ
ームによる方法の場合は、小さなビムスポットでα−３
（の層を走査する関係で、走査線と走査線との間に生ず
る境界区域に成長ムラが生じた沙、走査線の間隔を小さ
くすれば時間がか＼るう先に過剰加熱部分が生じたりす
る欠点が指摘されているうそのため、最も新しいＩＣ回
路方式と言われる「三次元積層型ＩＣ回路」の生産には
使用できないとされている。The above method has already been introduced in some literature, but the conventional method is that the thickness is 4
The electric furnace method heats a layer of amorphous silicon (hereinafter referred to as α-84) in an electric furnace at 600°C for about 80 minutes, but since the heating time is relatively long, it is not practical in terms of productivity. Not. Although increasing the temperature increases the crystal growth rate f, there are drawbacks such as warpage of silicon wafers, contamination, and poor production yields. Research is currently underway on methods of short-term irradiation with laser beams. However, in the case of this method using a laser beam, α-3
(Due to the scanning of layers, uneven growth occurs in the boundary area between the scanning lines.If the spacing between the scanning lines is made smaller, overheating will occur over time.) It is said that the method cannot be used in the production of ``three-dimensional stacked IC circuits,'' which are said to be the newest IC circuit method, because of the lies that have been pointed out to have such shortcomings.
本発明の目的はウェハー上のアモルファスシリコンもし
くは多結晶シリコンをエピタキシアル成長させる方法に
おいて、比較的短時間で、しかもウェハーを損傷させる
ことなくα−８４の全域を成長ムラなく実行する新規外
方法を提供するととＫあり、その特徴とするところは、
（イ）複数の管状ランプを管軸を平行もしくはほぼ平行
にして、エピタキシアル成長させるべきシリコンの通路
に対して平行もしくはほぼ平行な、かつ骸通路を挾む位
置の２つの平面内に配置し、
（ロ）シリコンの表面が１１００℃〜１４００℃の温度
に加熱されるよう、両方の平面内の管状ランプを少なく
とも４秒間以上点灯し、
（うシリコンの表面に面する方の平面内の管状ランプの
少なくとも１本を過入力点灯して、シリコンの表面の一
部を局部的に１４１０℃〜１４８０℃に昇温せしめ、
に）その後、過入力点灯されるべき管状ランプを隣接す
る順に切り替えてエピタキシアル成長されるべき全域を
１４１０℃〜１４８０℃に昇温させる、
工程を含むことにある。The purpose of the present invention is to provide a novel method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer, which can uniformly grow the entire α-84 area in a relatively short time and without damaging the wafer. (a) The tube axes of multiple tubular lamps are parallel or nearly parallel to the path of the silicon to be epitaxially grown, and the features are as follows. (b) The tubular lamps in both planes are lit for at least 4 seconds so that the silicon surface is heated to a temperature of 1100°C to 1400°C, and ( At least one of the tubular lamps in the plane facing the silicon surface is turned on with excessive power to locally heat a part of the silicon surface to 1410°C to 1480°C; The method includes the steps of switching the input tubular lamps to be turned on in the order of adjacent ones to raise the temperature of the entire area to be epitaxially grown to 1410° C. to 1480° C.
以下、実施例を参照しながら本発明を説明する。The present invention will be described below with reference to Examples.
第１図は、本発明に使用する管状ランプの一例の説明図
であって、具体的には定格消費電力１訓のハロゲン白熱
電球である。図において、１はバルブ、２はシール部、
３は、シール部に埋設された金属箔、４及び５は、前記
箔から導出される外導線及び内導線であり、内導線５．
５間には、管−軸に沿って長さ約１６５１のフィラメン
ト６が張架されている。７け、フィラメントロを管軸に
支えるためのアンカーであり、パ〜し内には稀ガスと共
に徽量のハロゲンを含み、上記電球は小型長寿命の特性
を有するものとして知られている。FIG. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, specifically a halogen incandescent light bulb with a rated power consumption of one unit. In the figure, 1 is a valve, 2 is a seal part,
3 is a metal foil embedded in the sealing portion; 4 and 5 are outer and inner conductor wires led out from the foil; and inner conductor wire 5.
A filament 6 having a length of approximately 1651 mm is stretched between the tubes 5 and 5 along the tube axis. 7 is an anchor for supporting the filament tube on the tube shaft, and the bulb contains a large amount of halogen along with rare gas, and the above-mentioned light bulb is known to have the characteristics of small size and long life.
第２図は、上記管状ランプ１００の複数を、管軸を平行
にして、エピタキシアル成長させるべきα−８（の層を
具えたウェハー８の蓮路上に対して平行な、かつ該通路
を挾む位置の２つの平面Ｓ１．８、内に配置し、上方及
び下方をミラー９で覆りた１、本発明方法を実施するた
めの加熱炉の一例の要部の説明図である。図において千
両Ｓ、とＳ、の間隔は６ａａである。FIG. 2 shows a plurality of the above-mentioned tubular lamps 100, with their tube axes parallel to each other, parallel to the lotus path of a wafer 8 having a layer of α-8 to be epitaxially grown, and sandwiching the path. FIG. 1 is an explanatory view of the essential parts of an example of a heating furnace for carrying out the method of the present invention, which is placed within two planes S1. The interval between Senryo S and S is 6aa.
第３図は、エピタキシアル成長させるべきα−８（の層
を具えたウェハー８の一例の説明図であって、具体的に
は、ウェハーは単結晶シリコン（以下５−ｓｔ）、ｌＯ
は、例えば８（０，や８（、Ｎ、の如き絶縁層、１１は
α−８４の層であり、厚みは夫々約０５曽約０．２ｊ＋
ｍ、約１畔で、ウェハー８の直径は約１０−である。と
＼で、絶縁層１０には、第４図に拡大図飛した如く、重
数μ一種度の溝１２が、約５０〜５００ｇ＋＋ｓの間隔
で設けられてシリ、α−８（層１１とウェハー８とは溝
１２を介して接触している。したがって、α−８（の層
をエピタキシアル成長させた場合、５−８（の層が、絶
縁層１０を介して「積層」された亀のとなる。三次元積
層ＩＩＸＣ回路の製造に際しては適宜絶′縁層内にスル
ーホールを設は上下の５−Ｓｔ層を電気的に接続して、
三次元積層１１１１Ｃ回路の製作が可能となる。FIG. 3 is an explanatory diagram of an example of a wafer 8 having a layer of α-8 (hereinafter referred to as 5-st) to be epitaxially grown.
is an insulating layer such as 8(0, or 8(, N), and 11 is an α-84 layer, each having a thickness of approximately 0.05×0.2j+
The diameter of the wafer 8 is approximately 10 m. In the insulating layer 10, as shown in the enlarged view in FIG. 8 through the groove 12. Therefore, when the layer α-8() is epitaxially grown, the layer 5-8() is in contact with the turtle layer "stacked" through the insulating layer 10. When manufacturing a three-dimensional laminated IIXC circuit, through holes are appropriately provided in the insulation layer to electrically connect the upper and lower 5-St layers.
It becomes possible to manufacture a three-dimensional laminated 1111C circuit.
さて、ウェハー８を加熱炉に挿入し、両方の平面内のラ
ンプ１００を点灯せしめると、ウェハー及びα−Ｓンの
層は３〜５秒程度で１１００℃〜１４００℃に略均−に
昇温するので、しばらくその温度で保持せしめ、後、他
方の千＠Ｓ、内の、ウェハーの一番端部のラシプ１００
６のみ過入力点灯し、順次隣接する右側のランプ（第２
図参照）を切替選択して過入力点灯すると、α−８１の
層は、所定時間の間だけ、右側から部分的に少しず＼１
４１０℃〜１４８０℃の温度になる。頂度、ゾーンメル
ティングやゾーンリファイニング操作のように部分部分
処理して行くものであって、１４１元〜１４８０℃に保
たれる所定時間は、ランプの消費電力、ランプ間の相互
距離、ランプとウェハーとの離間距離、切替選択速度に
よって種々の値が選べるが、上記ゾーンが少なくも０．
１ａｗ／秒以上で移動するよう順次切替選択する。この
選択速度は、実際には加熱炉が設計されれば実験的に決
めることができる。この場合、炉内雰囲気はアルゴンが
良く、成長の始点となる結晶核は、溝を介して接触して
いる５−８ｔがその役割を果している。Now, when the wafer 8 is inserted into the heating furnace and the lamps 100 in both planes are turned on, the temperature of the wafer and the α-S layer increases approximately evenly from 1100°C to 1400°C in about 3 to 5 seconds. Therefore, hold the temperature at that temperature for a while, and then remove the rasp 100 at the end of the wafer in the other
Only 6 lights up due to excessive input, and the adjacent right lamp (2nd
When the over-input light is turned on by switching the switch (see figure), the α-81 layer will be partially removed from the right side for a predetermined period of time.
The temperature will be between 410°C and 1480°C. The predetermined time for maintaining the temperature between 141 yuan and 1480°C depends on the power consumption of the lamps, the mutual distance between the lamps, and the lamp temperature. Various values can be selected depending on the separation distance between the wafer and the wafer, and the switching selection speed, but the above zone is at least 0.
Sequentially switch and select to move at 1 aw/sec or more. This selection speed can actually be determined experimentally once the heating furnace is designed. In this case, the atmosphere in the furnace is preferably argon, and the 5-8t crystals that are in contact with each other through the grooves play the role of the crystal nuclei that serve as the starting point for growth.
上記エピタキシアル成長は、シリコンの融点近傍で行う
のが良く、全域同時に、長時間、１４１０℃〜１４８０
℃に昇温すると、ウェハーが熔融したり、「反り」など
が生ずる欠点があるが、ゾーンリファイニングのような
方法で進行さ６．せると、ウェハーを損傷させず、「反
り」なども生ずると七なくα−８（の層の全域のエピタ
キシアル成長が完成し、しかも成長ムラもない。温度制
御の方は、ランプの消費電力、ランプ間の相互距離、ラ
ンプとウェハーの離間距峻郷で１１００℃〜１４８０℃
の範囲で比較的自由に選択でき、上記、１１００℃〜１
４００℃に一時的に保持したのは、全域を同時に、室温
から直接成長ａｍに昇温させるよりも昇温ムラによる成
長ムラ、ウニノ・−の変形が少ないものが得られるから
であシ、一種の「サーマルアシスト法」である。The above epitaxial growth is preferably carried out near the melting point of silicon, simultaneously over the entire area and for a long period of time at 1410°C to 1480°C.
6. If the temperature is raised to ℃, the wafer may melt or "warp" may occur, but this process can be carried out using methods such as zone refining. By doing so, the epitaxial growth of the entire α-8 layer is completed without damaging the wafer or causing any "warping", and there is no uneven growth. , mutual distance between lamps, separation distance between lamps and wafers: 1100℃~1480℃
It can be selected relatively freely within the range of 1100℃ to 1
The reason why the temperature was temporarily held at 400°C was that it was possible to obtain a product with less uneven growth due to uneven temperature rise and less deformation of Unino- than when the entire area was raised from room temperature directly to the growth temperature at the same time. This is the "thermal assist method".
前記の一時的保持時間は、少なくとも４秒以上あれは喪
い。そして、ゾーンの移動速度は、成長温度として、融
点近傍の１４１０℃〜１４８０℃を選ぶ関係で、０．１
ａｌ／秒以上の速度になるように過入力ランプ１００Ｓ
を隣接する順に切り替え選択するのが喪く、それよシ違
いと過剰加熱部分が生じたり、ウェハーを損傷するので
好ましくない。また、熔融表面が表面張力によシ盛りあ
がり、それがその壕＼冷却し、表面に凹凸が生ずる欠点
も現われてくる。たソし、あｔ９早いと、成長が不十分
な区埴が生ずることがあり、移動速度の上限は８信／秒
にした方が良い。The temporary holding time is at least 4 seconds. The moving speed of the zone is 0.1 by selecting the growth temperature from 1410°C to 1480°C near the melting point.
Over-input lamp 100S so that the speed is higher than al/second
It is undesirable to switch and select the wafers in the order of adjacency, but this is not preferable because it may cause overheating or damage the wafer. Another problem is that the molten surface rises due to surface tension, which cools the molten surface, creating unevenness on the surface. However, if it is too fast, it may result in insufficiently grown kubo, so it is better to set the upper limit of the movement speed to 8 speeds/second.
ところで、本発明の方法においては、加熱源として、点
灯・消灯、定格点灯・過入力点灯いづれの切り替え作業
に応じて殆んど瞬時に全放射光が追随して変化する管状
ランプを利用するものであるから、温間の制御が容易に
実行できること、ランプであるので加熱源が劣化しても
交換や保守も容易、ウェハーの汚染もなく、「反り」郷
の変形防止にも極めて有利である。前記実施例では、）
・ロゲン白熱電球を示したが、キセノンロングアークラ
ンプの如き放電灯を利用しても、同じ利点を有する。By the way, in the method of the present invention, a tubular lamp is used as a heating source, and the total emitted light changes almost instantaneously in accordance with the switching operation of turning on/off, rated lighting, and over-input lighting. Therefore, warm temperature control can be easily performed, and since it is a lamp, it is easy to replace and maintain even if the heating source deteriorates, there is no contamination of the wafer, and it is extremely advantageous in preventing deformation of "warp". . In the above embodiment,)
-Although rogen incandescent lamps are shown, discharge lamps such as xenon long arc lamps can also be used with the same advantages.
本発明は以上の説明からも理解できるように、ウェハー
上のアモルファスシリコン４Ｌ＜は多Ｍ晶シリコンをエ
ピタキシアル成長させる方法ニオいて、
（−（）複数の管状ランプを管軸を平行もしくはほぼ平
行にして、エピタキシアル成長させるべきシリ゛コンの
通路に対して平行もしくはほぼ平行な、かつ該通路を挾
む位置の２つの平面内に配着し、
（ロ）シリコンの表面が１１００℃〜１４００℃の温度
に加熱きれるよう、両方の平面内の管状ランプを少なく
とも４秒間以上点灯し、
ｔ＋シリコンの表面に面する方の平面内の管状ランプの
少々〈と４１本を過入力点灯して、シリコンの表面の一
部を局部的に１４１０℃〜１４８０℃に昇温せしめ、
に）その後、過入力点灯されるべき管状ランプを隣接す
る順に切り替えてエピタキシアル成長されるべき全域を
１４１０℃〜１４８０℃に昇温させる、
ことによって、比較的短時間で、しかもウニノ・−上の
α−８４の全域を、成長ムラなく、シかもウェハーを損
傷させることなくエピタキシアル成長させる亀のであり
、反９、汚染もない成長方法が提供できる。As can be understood from the above description, the present invention is based on a method for epitaxially growing poly-M crystalline silicon on a wafer. (b) The surface of the silicon is heated to a temperature of 1100°C to 1400°C. The tubular lamps in both planes were turned on for at least 4 seconds to heat up to the temperature of °C, and a few of the tube lamps in the plane facing the t+ silicon surface were turned on with excessive power. A part of the silicon surface is locally heated to 1410°C to 1480°C, and then the entire area to be epitaxially grown is heated to 1410°C to 1480°C by switching the tubular lamps to be turned on with excessive input in the order of adjacent ones. By heating the wafer to a temperature of 9°C, it is possible to epitaxially grow the entire area of α-84 on the surface of the wafer in a relatively short time, evenly, and without damaging the wafer. , a pollution-free growth method can be provided.
第１図は、本発明に使用する管状ランプの一例の説明図
、第２図は、本発明を実行するための加熱炉の一例の！
部の説明図、第３図はウニノ・−の説明図、第４図は、
ウニノ・−の拡大説明図である。
図において、１００は管状ランプ、８はウニノ１−１９
はさラー、１０は絶縁層、１１はα−８（の層、１２は
溝を夫々示す。
特許出願人FIG. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, and FIG. 2 is an explanatory diagram of an example of a heating furnace for carrying out the present invention.
Figure 3 is an explanatory diagram of the unit, Figure 4 is an explanatory diagram of the unit.
It is an enlarged explanatory view of Unino. In the figure, 100 is a tubular lamp, 8 is Unino 1-19
10 is an insulating layer, 11 is an α-8 layer, and 12 is a groove. Patent applicant
Claims (1)
）コンをエピタキシアル成長させる方法において、 （（）複数の管状ランプを管軸を平行もしくはほぼ平行
にして、エピタキシアル成長させるべきシリコンの通路
に対して平行もしくはほぼ平行な、かつ該通路を挾む位
置の２つの平面内に配置し、 （ロ）シリコンの表面が１１００℃〜１４００℃の温度
に加熱されるよう、両方の平面内の管状ランプを少なく
とも４秒間以上点灯し、 （うシリコンの表面に面する方の平面内の管状ランプの
少なくとも１本を過入力点灯して、シリコンの表面の一
部を局部的に１４１０℃〜１４８０℃に昇温せしめ、 に）その後、過入力点灯されるべき管状ランプを隣接す
る順に切９替えてエピタキシアル成長されるべき全壊を
１４１０℃〜１４８０℃に昇温させる、 １糧を含むことをｓ像とする、ウェハー上のアモルファ
スシリコンもしくは多結晶シリコンをエピタキシアル成
長させる方法。[Claims] Amorphous silicon 4L<H polycrystalline V' on a wafer
) In a method for epitaxially growing silicon, (() a plurality of tubular lamps are arranged so that their tube axes are parallel or nearly parallel to a passage in silicon to be epitaxially grown, and the passage is sandwiched between the lamps. (b) Turn on the tubular lamps in both planes for at least 4 seconds so that the surface of the silicon is heated to a temperature of 1100°C to 1400°C; At least one of the tubular lamps in the plane facing the surface is turned on with excessive power to locally heat a part of the silicon surface to 1410°C to 1480°C; Amorphous silicon or polycrystalline silicon on a wafer is heated to 1410°C to 1480°C by switching the tubular lamps to be epitaxially grown in the order of adjacent ones. How to grow epitaxially.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144693A JPS5943810B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144693A JPS5943810B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846621A true JPS5846621A (en) | 1983-03-18 |
| JPS5943810B2 JPS5943810B2 (en) | 1984-10-24 |
Family
ID=15368068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56144693A Expired JPS5943810B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5943810B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020234959A1 (en) * | 2019-05-20 | 2020-11-26 | 三菱重工機械システム株式会社 | Tire electrical resistance measurement device and electrical resistance probe |
-
1981
- 1981-09-16 JP JP56144693A patent/JPS5943810B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5943810B2 (en) | 1984-10-24 |
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