JPS5846620A - Epitaxial growth method of amorphous silicon or polycrystalline silicon on wafer - Google Patents
Epitaxial growth method of amorphous silicon or polycrystalline silicon on waferInfo
- Publication number
- JPS5846620A JPS5846620A JP56144692A JP14469281A JPS5846620A JP S5846620 A JPS5846620 A JP S5846620A JP 56144692 A JP56144692 A JP 56144692A JP 14469281 A JP14469281 A JP 14469281A JP S5846620 A JPS5846620 A JP S5846620A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- silicon
- temperature
- lamp
- epitaxial growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はウーハ−上のアモルファスシリコンもしくは多
結晶シリコンをエピタキシアル成長ｄ、せる方法に関す
る。 ・、：上記方法については
、既にいくつかの文献に紹介されているところであるが
、従来最も一般的な方法は、厚さ４０００人のアモルフ
ァスシリコン（以下α−８ｔ）の層を、例えば６００’
Ｃの電気炉で約８０分間加熱する電気炉法であるが、比
較的長い時間の加熱なので、生産性の点で実用的でない
。また、温度を上げることにより結晶成長速度は上昇す
るが、
シリコンのつ℃バーに「反り」が発生したシ、汚染され
たり、したカドっで生産の歩留が悪い等の欠点があり、
最近ではレーザビームで短時間照射する方法が研究され
ている。しかしながら、とのレーザビームによる方法の
場合は、小さなビームスポットでα−８ｉの層を走査す
る関係で、走査線と走査線との間に生ずる境界区域に成
長ムラが生じたり、走査線の間隔を小さくすれば時間が
かかるうえに過剰加熱部分が生じたりする欠点が指摘さ
れている。そのため、最も新しいＩＣ回路方式と言われ
る「三次元積層型ＩＣ回路」の生産には使用できないと
されている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for epitaxially growing amorphous silicon or polycrystalline silicon on a woofer.・,: The above method has already been introduced in several documents, but the most common method to date is to form a layer of amorphous silicon (hereinafter referred to as α-8T) with a thickness of 4000 mm, for example, with a thickness of 600 mm.
The electric furnace method involves heating in an electric furnace for about 80 minutes, but since the heating time is relatively long, it is not practical in terms of productivity. In addition, although increasing the temperature increases the crystal growth rate, there are disadvantages such as "warping" of the silicon temperature bar and poor production yields due to contamination or corners.
Recently, methods of short-time irradiation with laser beams have been studied. However, in the case of the method using a laser beam, since the α-8i layer is scanned with a small beam spot, uneven growth occurs in the boundary area between the scanning lines, and the spacing between the scanning lines. It has been pointed out that reducing the temperature takes time and causes excessive heating. Therefore, it is said that it cannot be used in the production of "three-dimensional stacked IC circuits," which are said to be the newest IC circuit method.
本発明の目的は、ウェハー上のアモルファスシリコンも
シくハ多結晶シリコンを１ビタキシアル成長させる方法
において、比較的短時間で、しかもウェハーを損傷させ
ることなくα−８ｉの全域を成長ムラなく実行する新規
な方法を提供することにあり、その特徴とするところは
、
（イ）複数の管状ランプを管軸を平行もしくは＃１ぼ平
行にして、エピタキシアル成長させるべきシリコンの通
路に対して平行もしくはほぼ平行な、かつ該通路を挾む
位置の２つの平面内に配置し、
（ロ）シリコンの表面が１１００’Ｃ〜１４００’ｃの
温度に加熱されるよう、両方の平面内の管状ランプを少
なくとも４秒間以上点灯し、
（ハ）シリコンの表面に面する方の平面内の管状ランプ
の少なくとも１本を過入力点灯して、シリコンの表面の
一部を局部的に１４１０℃〜１４８０°Ｃに昇温せしめ
、
に）シリコンを、管状ランプの管軸に対して直角方向に
、管状ランプに対して相対的に少なくとも０．１ ｃｍ
７秒以上の速度で移動させる、工程を含むことにある
。An object of the present invention is to perform one-bitaxial growth of polycrystalline silicon on a wafer from amorphous silicon to uniform growth over the entire α-8i region in a relatively short time and without damaging the wafer. The purpose is to provide a new method, and its characteristics are as follows: (a) A plurality of tubular lamps are arranged with their tube axes parallel or approximately parallel to #1, and parallel or parallel to the path of silicon to be epitaxially grown. (b) Tubular lamps in both planes are arranged in two planes that are substantially parallel and sandwich the passage, and (b) tubular lamps in both planes are heated so that the surface of the silicon is heated to a temperature of 1100'C to 1400'C. (c) At least one of the tubular lamps in the plane facing the silicon surface is turned on with excessive power to locally heat a part of the silicon surface to 1410°C to 1480°C. a) heating the silicon to a temperature of at least 0.1 cm perpendicular to the tube axis of the tubular lamp and relative to the tubular lamp;
It includes a step of moving at a speed of 7 seconds or more.
以下、実施例を参照しながら本発明を説明する。The present invention will be described below with reference to Examples.
第１図は、本発明に使用する管状ランプの一例の説明図
であって、具体的には定格消費電力１瞑のハロゲン白熱
電球である。図において、１はバルブ、２はシール部、
３は、シール部に埋設された金属箔、４及び５は、前記
箔から導出される外導線及び内導線であり、内溝１１！
５．５間には、管軸に沿って長さ約１６５！のフィラメ
ント６が張架されている。７は、フィラメント６を管軸
に支えるためのアンカーであり、パルプ内には稀ガスと
共に微量のハロゲンを含み、上記電球は小型長寿命の特
性を有するものとして知られている。FIG. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, specifically a halogen incandescent lamp with a rated power consumption of 1. In the figure, 1 is a valve, 2 is a seal part,
3 is a metal foil embedded in the sealing portion, 4 and 5 are outer and inner conductive wires led out from the foil, and the inner groove 11!
Between 5.5 and 5.5, there is a length of about 165 along the tube axis! filament 6 is stretched. Reference numeral 7 denotes an anchor for supporting the filament 6 on the tube shaft, and the pulp contains rare gas and a small amount of halogen, and the above-mentioned light bulb is known to have the characteristics of small size and long life.
第２図は、上記管状ランプ１００の複数を、管軸を平行
にして、エピタキシアル成長させるべきα−８ｉの層を
具えたウニノ・−８の通路Ｐに対して平行な、かつ該通
路を挾む位置の２つの平面Ｓ１、Ｓ。FIG. 2 shows a plurality of the above tubular lamps 100 with their tube axes parallel to and parallel to the path P of the Unino-8 with the layer of α-8i to be epitaxially grown. Two planes S1 and S at sandwiching positions.
内に配置し、上方及び下方をミラー９で覆った、本発明
方法を実施するだめの加熱炉の一例の要部の説明図であ
る。図示の如く、ウェハー８は、管状ランプ１００の管
軸に対して直角方向（矢印方向）に走行するものであり
、平面ＳＩ、８２間の距離は６υである。FIG. 2 is an explanatory view of the main parts of an example of a heating furnace for carrying out the method of the present invention, which is placed inside the furnace and covered with mirrors 9 on the upper and lower sides. As shown, the wafer 8 runs in a direction perpendicular to the tube axis of the tubular lamp 100 (in the direction of the arrow), and the distance between the planes SI and 82 is 6υ.
第３図は、エピタキシアル成長させるべきα−８ｉの層
を具えたウェハー８の一例の説明図であって、具体的に
は、ウェハーは単結晶シリコン（以下ｚ−８ｉン、１０
は、例えばＳｉｎ、やＳｉ、Ｎ４の如き絶縁層、１１は
α−８ｉの層であり、厚みは夫々約０，５龍、約０．２
１１ｍ 、 約１ ｐｍで、ウニ／’−８の直径は約
１０ｃｍである。ここで、絶縁層ＩＵｖｗは、第４図に
拡大図示した如く、中敷μｍ程度の溝１２が、約５０〜
５００μｍの間隔で設けられており、α−８ｉ層１１と
ウニ・・−８とは溝１２を介して接触している。したが
って、α−３ｉの層をエピタキシアル成長させた場合、
ｌ−Ｓｉｎ層が、絶縁層１０を介して「積層」されたも
のとなる。三次元積層型ＩＣ回路の製造に際しては適宜
絶縁層内にスルーホールを設は上下の５−８ｉ層を電気
的に接続して、三次元積層型ＩＣ回路の製作が可能と々
る。FIG. 3 is an explanatory diagram of an example of a wafer 8 having a layer of α-8i to be epitaxially grown.
11 is an insulating layer such as Sin, Si, or N4, and 11 is an α-8i layer, the thickness of which is approximately 0.5× and approximately 0.2×, respectively.
11 m, about 1 pm, and the diameter of Urchin/'-8 is about 10 cm. Here, as shown in an enlarged view in FIG. 4, the insulating layer IUvw has grooves 12 of about 50 to
They are provided at intervals of 500 μm, and the α-8i layer 11 and the sea urchin...-8 are in contact via the grooves 12. Therefore, when a layer of α-3i is grown epitaxially,
The l-Sin layers are "stacked" with the insulating layer 10 in between. When manufacturing a three-dimensionally stacked IC circuit, a through hole is appropriately provided in the insulating layer to electrically connect the upper and lower 5-8i layers, thereby making it possible to manufacture a three-dimensionally stacked IC circuit.
さて、ウニノ・−８を加熱炉に挿入し、両方の平面内の
ランプ１００を点灯せしめると、ウニノ・−及びα−８
Ｌの層は３〜５秒程度で１１００℃〜１４００℃に略均
−に昇温するので、しばらくその温度で保持せしめ、後
、他方の平面ＳＩ内の、ウニノー−の一番端部のランプ
１００ａのみ過・入力点灯し、その直下を、ウニノ・−
の全域が通過するようにウニ・・−を移動する。α−８
ｉの層は、直下に来た部分のみ１４１０°Ｃ−１４８０
″Ｃになり、その部分がエピタキシアル成長させられる
。つまり、ゾーンメルテイングやゾーンリファイニング
操作のように、エピタキシアル成長は、ウェハーの走行
に応じて、過入力点灯しているランプ１００ａの直下に
到達する順に、部分的に少しずつ進行し、最後に全域に
またがって完成する。この場合、炉内雰囲気はアルゴン
が良く、成長の始・点となる結晶核は、惰を介して接触
しているｓ −８ｉがその役割を果している。Now, when Unino-8 is inserted into the heating furnace and the lamps 100 in both planes are turned on, Unino-8 and α-8 are turned on.
The temperature of the layer L rises approximately uniformly to 1100°C to 1400°C in about 3 to 5 seconds, so it is held at that temperature for a while, and then the lamp at the end of the Uni-No-1 in the other plane SI is heated. Only 100a lights up, and just below it, Unino--
Move the sea urchin so that the whole area passes through. α-8
For layer i, only the part directly below is heated to 1410°C - 1480°C.
"C" and that part is epitaxially grown. In other words, as in zone melting and zone refining operations, epitaxial growth is performed as the wafer moves, directly under the lamp 100a that is turned on with excessive input power. In order to reach this point, the growth progresses little by little, and finally the whole area is completed.In this case, the atmosphere inside the furnace is good with argon, and the crystal nuclei, which are the starting point of growth, are in contact with each other through inertia. The s-8i, which is currently in use, plays this role.
上記エピタキシアル成長は、シリコンの融点近傍で行う
のが良く、全域同時に、長時間、１４１０”Ｃ〜１４８
０°Ｃに昇温すると、ウニノ・−が熔融したり、「反り
」などが生ずる欠点があるが、ゾーンリファイニングの
ような方法で進行させると、ウニノ・−を損傷させず、
「反シ」なども生ずることなくα−８ｉの層の全域のエ
ピタキシアル成長が完成し、しかも成長ムラもない。温
度制御の方は、ランプの消費電力、ランプ間の相互距離
、ランプとウェハーの離間距離等で１１００℃〜１４８
０℃の範囲で比較的自由に選択でき、上記、１１００°
Ｃ゛〜１４００’Ｃに一時的に保持したのは、全域を同
時に、室温から直接成長温度に昇温させるよりも昇温ム
ラによる成長ムラ、ウェハーの変形が少ないものが得ら
れるからであシ、一種の「サーマルアシスト法」である
。The above epitaxial growth is preferably carried out near the melting point of silicon, simultaneously over the entire area and for a long period of time at temperatures ranging from 1410"C to 148"C.
Raising the temperature to 0°C has the drawback of melting the Unino-- and causing "warping," but if the process is carried out using a method such as zone refining, the Unino-- will not be damaged.
The epitaxial growth of the entire area of the α-8i layer was completed without any "reverse cracks" occurring, and there was no uneven growth. Temperature control varies from 1100℃ to 148℃ depending on the power consumption of the lamps, the mutual distance between the lamps, the distance between the lamps and the wafer, etc.
It can be selected relatively freely within the range of 0°C, and above, 1100°
The reason why the temperature was temporarily held at C'~1400'C is that it is possible to obtain a product with less uneven growth and less deformation of the wafer due to uneven heating than if the entire area was heated directly from room temperature to the growth temperature at the same time. , which is a kind of "thermal assist method."
前記の一時的保持時間は、少なくとも４秒以上あれば良
い。そして、ウェハーの移動速度は、成長温度として、
融点近傍の１４１０°Ｃ〜１４８０°Ｃを選ぶ関係で、
０．１ ｔｒｎ ７秒以上の速度で過入力ランプ１００
αの直下を通過させるのが良く、それより遅いと過剰加
熱部分が生じたり、ウニノ・−を損傷するので好ましく
ない。また、熔融表面が表面張力により盛りあがり、そ
れがそのまま冷却し、表面に凹凸が生ずる欠点も現われ
てくる。ただし、あまり早いと、成長が不十分な区域が
生ずることがあり、移動速度の上限は８ ｃｍ ７秒に
した方が良い。The temporary holding time may be at least 4 seconds or more. Then, the moving speed of the wafer is expressed as the growth temperature.
By choosing 1410°C to 1480°C near the melting point,
0.1 trn Over-input lamp 100 at speed of 7 seconds or more
It is better to pass the heat just below α; if it is slower than that, overheating may occur or damage may occur, so it is not preferable. Another problem is that the molten surface bulges due to surface tension, which then cools down, resulting in unevenness on the surface. However, if the movement speed is too fast, areas with insufficient growth may occur, so it is better to set the upper limit of the movement speed to 8 cm and 7 seconds.
ところで、本発明の方法においては、加熱源として、点
灯・消灯、定格点灯・過入力点灯いずれの切り替え作業
に応じて殆んど瞬時に全放射光が追随して変化する管状
ランプを利用するものであるから、温度の制御が容易に
実行できること、ランプであるので加熱源が劣化しても
交換や保守も容易、ウェハーの汚染もなく、「反り」等
の変形防止にも極めて有利である。前記実施例では、ハ
ロゲン白熱電球を示したが、キセノンロングアークラン
プの如き放電灯を利用しても、同じ利点を有する。By the way, in the method of the present invention, a tubular lamp is used as a heating source, and the total emitted light changes almost instantaneously depending on whether the lamp is switched on/off, rated lighting, or over-input lighting. Therefore, the temperature can be easily controlled, and since it is a lamp, it is easy to replace and maintain even if the heating source deteriorates, there is no contamination of the wafer, and it is extremely advantageous in preventing deformation such as "warping". Although a halogen incandescent lamp is shown in the above embodiment, a discharge lamp such as a xenon long arc lamp may also be used with the same advantages.
本発明は以上の説明からも理解できるように、ウェハー
上のアモルファスシリコンもしくは多結晶シリコンをエ
ピタキシアル成長させる方法において、
（イ）複数の管状ランプを管軸を平行もしくはほぼ平行
にして、エピタキシアル成長させるべきシリコンの通路
に対して平行もしくはほぼ平行な、かつ該通路を挾む位
置の２つの平面内に配置し、
（ロ）シリコンの表面が１１００″Ｃ〜１４００℃の温
度に加熱されるよう、両方の平面内の管状ランプを少な
くとも４秒間以上点灯し、
（ハ）シリコンの表面に面する方の平面内の管状ランプ
ｄ少なくとも１本を過入力点灯して、シリコンの表面の
一部を局部的に１４１０°Ｃ〜１４８０°Ｃに昇温せし
め、
に）シリコンを、管状ランプの管軸に対して直角方向に
、管状ランプに対して相対的に少なくとも０．１ ｃｍ
７秒以上の速度で移動させる、ことによって、比較的
短時間で、しかもウニノー−上のα−８ｉの全域を、成
長ムラなく、しかもつ工・・−を損傷させることなくエ
ピタキシアル成長させるものであり、反り、汚染もない
成長方法が提供できる。。As can be understood from the above description, the present invention provides a method for epitaxially growing amorphous silicon or polycrystalline silicon on a wafer. Arranged in two planes that are parallel or nearly parallel to the path of the silicon to be grown and sandwiching the path, and (b) the surface of the silicon is heated to a temperature of 1100"C to 1400C. (c) At least one of the tubular lamps in the plane facing the silicon surface is turned on with excessive power, and a part of the silicon surface is lit. (a) heating the silicon locally to 1410°C to 1480°C; a) heating the silicon at a distance of at least 0.1 cm perpendicular to the tube axis of the tubular lamp and relative to the tubular lamp;
By moving at a speed of 7 seconds or more, it is possible to epitaxially grow the entire area of α-8i on the surface in a relatively short time, with even growth and without damaging the structure. Therefore, a growth method that is free from warping and contamination can be provided. .
第１図は、本発明に使用する管状ランプの一例の説明図
、第２図は、本発明を実行するための加熱炉の一例の要
部の説明図、第３図はウニノ・−の説明図、第４図は、
ウニノ・−の拡大説明図である。
図において、１００は管状ランプ、８はウニノ１−１９
はミラー、１０は絶縁層、１１はα−８ｉの層、１２は
溝を夫々示す。
特許出願人Fig. 1 is an explanatory diagram of an example of a tubular lamp used in the present invention, Fig. 2 is an explanatory diagram of main parts of an example of a heating furnace for carrying out the present invention, and Fig. 3 is an explanatory diagram of an example of a heating furnace for carrying out the present invention. Figure 4 is
It is an enlarged explanatory view of Unino. In the figure, 100 is a tubular lamp, 8 is Unino 1-19
10 is an insulating layer, 11 is an α-8i layer, and 12 is a groove. patent applicant
Claims (1)
コンをエピタキシナル成長させる方法において、 （イ）複数の管状ランプを管軸を平行もしくはほぼ平行
にして、エピタキシアル成長させるべきシリコンの通路
に対して平行もしくはほぼ平行な、かつ該通路を挾む位
置の２つの平面内に配置し、 （ロ）シリコンの表面が１１００’Ｃ〜１４００’Ｃの
温度に加熱されるよう、両方の平面内の管状ランプを少
なくとも４秋間以上点灯し、 （ハ）シリコンの表面に面する方の平面内の管状ランプ
の少なくとも１本を過入力点灯して、シリコンの表面の
一部を局部的に１４１０’Ｃ〜１４８゜°Ｃに昇温せし
め、 に）シリコンを、管状ランプの管軸に対して直角方向に
、管状ランプに対して相対的に少なくとも０．１ ｃｍ
７秒以上の速度で移動させる、工程を含むことを特徴
とする、ウェハー上のアモ７＋、７アスシＩＪ ：ｙン
もしくは多結晶シリコンを１ピタキシアル成長させる方
法。[Claims] In a method for epitaxially growing amorphous silicon or polycrystalline silicon on a woofer, (a) a plurality of tubular lamps are used with their tube axes parallel or nearly parallel to grow silicon to be epitaxially grown; (b) placed in two planes that are parallel or nearly parallel to the passageway and sandwiching the passageway; (c) At least one of the tubular lamps in the plane facing the silicon surface is turned on with excessive power to locally lighten a part of the silicon surface. (b) heating the silicon to 1410'C to 148°C, and (b) dispersing the silicon at a distance of at least 0.1 cm perpendicular to the tube axis of the tubular lamp and relative to the tubular lamp.
A method for 1-pitaxial growth of ammo 7+, 7-assi IJ:yn or polycrystalline silicon on a wafer, the method comprising the step of moving at a speed of 7 seconds or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144692A JPS5948533B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56144692A JPS5948533B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846620A true JPS5846620A (en) | 1983-03-18 |
| JPS5948533B2 JPS5948533B2 (en) | 1984-11-27 |
Family
ID=15368043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56144692A Expired JPS5948533B2 (en) | 1981-09-16 | 1981-09-16 | Method for epitaxial growth of amorphous silicon or polycrystalline silicon on a wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5948533B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0827950A (en) * | 1994-07-12 | 1996-01-30 | Katsuji Hagiwara | Building precast concrete slab, manufacture thereof, and building precast concrete slab fitting method |
-
1981
- 1981-09-16 JP JP56144692A patent/JPS5948533B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0827950A (en) * | 1994-07-12 | 1996-01-30 | Katsuji Hagiwara | Building precast concrete slab, manufacture thereof, and building precast concrete slab fitting method |
| JP2939787B2 (en) * | 1994-07-12 | 1999-08-25 | 克爾 萩原 | Method of manufacturing PCa plate for building, PCa plate for building, and mounting method of PCa plate for building |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5948533B2 (en) | 1984-11-27 |
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