JPS5846436U - Semiconductor wafer display card - Google Patents
Semiconductor wafer display cardInfo
- Publication number
- JPS5846436U JPS5846436U JP14052981U JP14052981U JPS5846436U JP S5846436 U JPS5846436 U JP S5846436U JP 14052981 U JP14052981 U JP 14052981U JP 14052981 U JP14052981 U JP 14052981U JP S5846436 U JPS5846436 U JP S5846436U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- display card
- wafer display
- lofts
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Packaging Of Annular Or Rod-Shaped Articles, Wearing Apparel, Cassettes, Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は半導体ウェハの正面図、第2図はキャリヤの斜
視図、第3図は半導体ウェハに対する処理工程を示すブ
ロック図、第4図はキャリヤケースの斜視図、第5図以
降はこの考案に係り、第5図は半導体ウェハ、−カード
を内装したキャリヤの斜視図、第6図ないし第8図はい
ずれも夫々が1実施例のカードの正面図、第9図は半導
体ウェハに対する処理工程を示すブロック図、第10図
はカード読取りのための発光部の正面図、第11図はカ
ードの正面図である。
1.1′・・・半導体ウェハ、2・・・キャリヤ、4a
。
4a′・・・4b・・・4C・・・半導体ウェハの処理
工程、7・・・カード、7a、 7a’・・・7b、
7c・・・カードの穿孔、9・・・発光部。Fig. 1 is a front view of the semiconductor wafer, Fig. 2 is a perspective view of the carrier, Fig. 3 is a block diagram showing the processing steps for the semiconductor wafer, Fig. 4 is a perspective view of the carrier case, and Fig. 5 and subsequent figures show this invention. 5 is a perspective view of a carrier containing a semiconductor wafer and a card, FIGS. 6 to 8 are each a front view of a card of one embodiment, and FIG. 9 is a processing step for a semiconductor wafer. FIG. 10 is a front view of a light emitting unit for reading a card, and FIG. 11 is a front view of the card. 1.1'...Semiconductor wafer, 2...Carrier, 4a
. 4a'...4b...4C...Semiconductor wafer processing step, 7...Card, 7a, 7a'...7b,
7c...Card perforation, 9...Light emitting part.
Claims (1)
ャリヤに収納し各処理装置間を搬送するため半導体ウェ
ハのロフトにつける表示カードにおいて、表示カードが
半導体ウェハと同じ大きさおよび型に形成され半導体ウ
ェハの1枚分としてキャリヤに挿入されるとともに、こ
のカードにロフトを表示するパンチ孔と記録とが設けら
れたことを特徴とする半導体ウェハの表示カード。A large number of semiconductor wafers are stored in carriers in lofts divided into manufacturing units and are attached to semiconductor wafer lofts for transportation between processing equipment. 1. A semiconductor wafer display card, which is inserted into a carrier as one wafer and is provided with a punch hole and a record for displaying a loft.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14052981U JPS5846436U (en) | 1981-09-24 | 1981-09-24 | Semiconductor wafer display card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14052981U JPS5846436U (en) | 1981-09-24 | 1981-09-24 | Semiconductor wafer display card |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5846436U true JPS5846436U (en) | 1983-03-29 |
Family
ID=29933686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14052981U Pending JPS5846436U (en) | 1981-09-24 | 1981-09-24 | Semiconductor wafer display card |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5846436U (en) |
-
1981
- 1981-09-24 JP JP14052981U patent/JPS5846436U/en active Pending
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