JPS5845681A - Memory system - Google Patents

Abstract

PURPOSE:To improve the utilizing rate of a memory system, by using two arbitrary chip selection signal output terminals of a chip selecting means in common and extending the address area of one memory chip. CONSTITUTION:An address decoder 11 outputs chip selection signals CS1, CS2- CSN selecting one of a plurality of memory chips with address signals A1-A9 from chip selection signal output terminals 121, 122-12N. Two arbitrary adjacent chip selection signal output terminals are shortened with a jumper and a short-pin in common. Thus, the two memory chips corresponding to the chip selection signals at the shortened terminals have duplicated addresses of data storage area, allowing to extend the address area of each memory chip.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory system in which a data storage section is composed of a plurality of memory chips, and when data is accessed, all of one memory chip is selected.

Random access memory systems used in data processing devices such as microcomputers usually have several RAs.
It is composed of memory chips such as M. When accessing data in such a memory system, one memory chip is all selected by the chip selection signal output from the address decoder to which part of the address signal is applied, and the remaining address signals are By using this method to address all of the memory chips at the same time, it is possible to access data only at a predetermined location on one memory chip. In the above memory system, consecutive addresses are generally assigned to one memory chip. For this reason, conventionally, even if there is an unused data storage area in one memory chip, and even if there is an amount of data that can be stored in this area, the address of this data corresponds to the address of the data storage area. If you don't have it, you won't be able to store it in this memory chip. Therefore, in this case, it is necessary to prepare another memory chip to which addresses corresponding to the above-mentioned data addresses are allocated. Sugawachi, 1st
As shown in the figure, of one memory chip 1 which is divided from address a to address a 1, data storage area A from address a to address b is used, and data storage area A from address C to d is used.
If the data storage area B in the address switch is not used, even if there is an amount of data that can be stored in the data storage area B, if the address of this data is a ''=g other than address d. If there are any memory chips from address h to address h, it is necessary to prepare all other memory chips to which addresses e to h, including this address g to h, are allocated.By the way, from the two memory chips 1 and 2 shown in FIG. In the memory system 1), ゝ)me', the data storage areas that are actually used are area A at addresses a to b, and area B at addresses g to h, and area B at address c''□d. Area C at addresses a-f is not used and is wasted, resulting in extremely poor utilization efficiency.

Its purpose is to provide a memory system with high utilization efficiency.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit configuration diagram of an address decoder portion that generates a chip selection signal in a memory system according to the present invention. The A1'' pulse decoder 11, for example,
Among the 0-bit address signals, some second-digit bits of the signal A, H-A9 (0 (j(9)) are given, and these signals fully select any one of the multiple memory chips. Chip selection for A8 C8I.

C82...C8N to each chip selection signal output terminal 121
It is designed to output from ゜122, . . . 12N.

In the present invention, any two adjacent chip selection signal output terminals of the address decoder 1, for example, terminals 12. and 122 are short-circuited with a no-amper wire, a short pin, etc. to make them common.

Here, the chip selection signal C which is now output from the terminal 121
It is assumed that one memory chip f1 shown in FIG.

In this way, the two terminals 121r of address decoder 1
122, addresses a to 5 of one memory chip shown in FIG. 1, addresses e to f of the other memory chip 2, and addresses C to d of memory chip 1 are The respective addresses from address g to h of memory chip 2 overlap, and as a result, data storage areas A and C
, B and D have the same address, which means that the address area of memory chip 1 or 2 has been expanded.

Therefore, the two memory chips 1 and 2 shown in FIG.
When using only the range from address a to address b and the range from address g to h, two memory chips f1 are used.
．． It is sufficient to provide only one of the two. Temporarily memory chip 7″1
If the range from address a to address b is fully provided, accessing the range from address a to address b corresponds to accessing data storage area A of memory chip 1, and accessing the range from address g to h address is equivalent to accessing data storage area A of memory chip 701. Data storage area B
This corresponds to accessing . As a result, memory chips can be used efficiently without waste.

Also, if all data storage areas A-D'i of two memory chips 7°1 and 2 are to be used, just disconnect terminal 121*12zk of address decoder 1 and add another memory chip 2. .

Note that the present invention is not limited to the above-mentioned embodiment; for example, in the above-mentioned embodiment, a case has been described in which any two adjacent chip selection signal output terminals of the address decoder 11 are shared; Alternatively, two terminals that are not adjacent to each other and are apart may be shared.

As explained above, according to the present invention, since any two chip selection signal output terminals of the chip selection means are made common, the address area of one memory chip is expanded, and as a result, A complete memory system can be provided with a sieve of utilization efficiency.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the allocation of addresses to two memory chips, and FIG. 2 is a circuit configuration diagram of an embodiment of the present invention. 1.2...Memory chip, 1...Address decoder, 12...Chip selection signal output ψIM element. Applicant's agent Patent attorney Takehiko Suzue 7- Figure 1 Figure 2 493-

Claims (1)

[Claims] The chip selection means selects all one memory chip from a plurality of memory chips using a part of the address signal, and the chip selection means selects all of one memory chip, and the remaining address signals are used to select a plurality of memory chips. In a memory system in which data is accessed at a predetermined location in one memory chip by simultaneously specifying addresses, one A memory system characterized by expanding the address area of a memory chip.