JPS5843624A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5843624A
JPS5843624A JP56141900A JP14190081A JPS5843624A JP S5843624 A JPS5843624 A JP S5843624A JP 56141900 A JP56141900 A JP 56141900A JP 14190081 A JP14190081 A JP 14190081A JP S5843624 A JPS5843624 A JP S5843624A
Authority
JP
Japan
Prior art keywords
transistor
integrated circuit
power supply
electric power
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56141900A
Other languages
Japanese (ja)
Inventor
Kuniharu Ito
伊藤 邦晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56141900A priority Critical patent/JPS5843624A/en
Publication of JPS5843624A publication Critical patent/JPS5843624A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00315Modifications for increasing the reliability for protection in field-effect transistor circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Abstract

PURPOSE:To prevent breakdown of a transistor due to static electricity without exerting no influence at the time of operation, by connecting a depression type transistor between a terminal of an integrated circuit, and ground and an electric power supply. CONSTITUTION:Between an output terminal 1-6, and ground and an electric power supply VCC, depression type transistors 1-1, 1-2 are connected, respectively. A base potential generating circuit 1-5 is constituted so that base potential VS becomes the same potential as the ground potential, in a state that the electric power supply VCC is not turned on. In this state, even if high voltage caused by static electricity is generated in an output terminal 3-6, a current flows through a resistance 3-1 or 3-2, on high voltage is applied between the source and the gate of an internal transistor 3-3, or between the drain and the gate of a transistor 3-4, and they are protected against a high potential pulse, etc. from the outside. Subsequently, in case when the electric power supply VCC has been turned on and the device has entered into the operating state, said transistors 1-1, 1-2 can be neglected, and no influence is exerted on an output.

Description

【発明の詳細な説明】 本発明は絶縁ゲート蓋電界効果トランジスタ(以下、M
O8i1)ランジスタと称す)を使用した半導体集積回
路装置に係り、JIK改良された保護回路を内蔵した半
導体集積回路装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate lid field effect transistor (hereinafter referred to as M
The present invention relates to a semiconductor integrated circuit device using a transistor (referred to as a transistor), and a semiconductor integrated circuit device incorporating a JIK-improved protection circuit.

一般に、MO811)ランジスタを用いた半導体装置は
静電気によりてトランジスタが破壊されることがある。
Generally, in semiconductor devices using MO811) transistors, the transistors may be destroyed by static electricity.

このため、保護手段として抵抗などを入出力端子に接続
するなどの方法がとられている。しかし、抵抗を用いる
方法では、例えば入力端子に%この抵抗を挿入する場合
は抵抗値を数にΩ以上の値にしないと効果がなく、従っ
て高速スイッチング特性の要求される入力端子には使用
できない欠点があうた。また出力端子に挿入する場合に
は、挿入した抵抗分による電圧降下分が出力レベル0@
性を悪化させゐ欠点がありた。
For this reason, methods such as connecting a resistor or the like to the input/output terminals are used as a protection measure. However, with the method of using a resistor, for example, when inserting this resistor into an input terminal, the resistance value must be set to a value of Ω or more in order to have an effect, and therefore it cannot be used for input terminals that require high-speed switching characteristics. The shortcomings were obvious. In addition, when inserting it into the output terminal, the voltage drop due to the inserted resistance will cause the output level to be 0@
It had the disadvantage of deteriorating sexuality.

本発明は上記従来の欠点に僑み、入力端子のスイッチン
グ特性の劣化もなく、また、出力端子の出力レベルの劣
化もなく、さらに静電気によゐ破壊もない入出力端子を
有する半導体集積回路装置を提供する事を目的とするも
のである。
The present invention overcomes the above-mentioned conventional drawbacks and provides a semiconductor integrated circuit device having input/output terminals without deterioration of the switching characteristics of the input terminals, without deterioration of the output level of the output terminals, and without being destroyed by static electricity. The purpose is to provide the following.

即ち、M08[)ツンジスタで構成された集積回路の端
子と11j111(以下、GNDと称す)間あるいは電
源間にデプレッション蓋トランジスタが接続され、前記
デプレッシ璽ン型トランジスタのゲート電極はGNDに
接続され、前記デプレ、シ。
That is, a depletion lid transistor is connected between a terminal of an integrated circuit constituted by an M08[) tunister and 11j111 (hereinafter referred to as GND) or between a power supply, and a gate electrode of the depletion lid transistor is connected to GND, Said Despres, C.

ン重トランジストを非導通状態とせしめる基盤電位を発
生する基盤電位発生回路を内部した事を特徴とする牛導
体装置である。
This conductor device is characterized by incorporating a base potential generation circuit that generates a base potential that causes the double transistor to become non-conductive.

以下図面を用いて、本発明の一実施例を説明する。第1
図に本発明による一実施例を示す。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an embodiment according to the present invention.

第1図は出力端子とGND及び電源間にデプレッション
型トランジスタを接続したものである。
FIG. 1 shows a device in which a depletion type transistor is connected between the output terminal, GND, and the power supply.

第1図において、1−1.1−2はデプレッシ嘗yll
Nch)うyジxり、1−3.1−4はエンハンスメン
トIINch)ランジスタ、l−5は基盤電位発生回路
である。トランジスタt−x、1−2は基盤電位VsK
対しt’:11図2に示す曲線のようにしきい値電圧v
テが変化する。
In Figure 1, 1-1.1-2 is depression
1-3.1-4 is an enhancement IINch) transistor, and l-5 is a base potential generation circuit. Transistors t-x, 1-2 have a base potential VsK
t': 11 As shown in the curve shown in Figure 2, the threshold voltage v
Te changes.

電源VCCが投入されていない状態で杜、■、は接地電
位と同電位となるようvcx−so基盤電位斃生關路が
構成されてい石。この時トランジスター −1* 1−
!i() Vt as 211OVtt テhD s 
)、 ランジスタ1−1*1−2は抵抗として働く。第
38!1社ヒO#O状態を示したものである。第3図に
11Fいて出力端子1−6’に静電気に一因する高電圧
が発生しても3−1又拡3−2の抵抗を介して電流が流
れ、内部のトランジスタ3−3のソースとダート間又状
トランジスタ3−4のドレインとゲート間に高電圧が加
わることはなく、外部からO高電位パルス等に対して保
護される。
The VCX-SO base potential connection is configured so that when the power supply VCC is not turned on, the voltage is the same as the ground potential. At this time, the transistor -1* 1-
! i() Vt as 211OVtt tehD s
), transistor 1-1*1-2 acts as a resistor. This shows the 38th!1 company's O#O status. In Fig. 3, even if a high voltage that contributes to static electricity is generated at the output terminal 1-6' at 11F, current flows through the resistor 3-1 or 3-2, and the source of the internal transistor 3-3. A high voltage is not applied between the drain and gate of the cross-shaped transistor 3-4, and the transistor 3-4 is protected from external high potential pulses.

次Ktl[Vccが投入され動作状態に入うた場合、!
I盤電位発生回路1−5にようて基盤電位vI■vsw
mが発生されるとトランジスター−1,1−−40v!
は第2Et)Vtlとなる。この時、トランジスター−
1,1−1は高インビーダyス状膣となjjlllml
は第4:・図と等債となる。すなわち、動作竺1111 状態KTh″1 ・□・j縞1100)9ydx#1−
1・1−2はII/AII″e自出力Kl響をあたえる
ことはない・ 以上、述べてきたように1本発Ij1によれば動作時に
影響を及ぼすことなく、使用時以外、たとえばL8Iの
保管中移動運搬時の静電気によるトランジスタ□の破壊
を防ぐζ、とができる。
Next, when Ktl[Vcc is turned on and enters the operating state, !
The base potential vI■vsw is determined by the I-board potential generation circuit 1-5.
When m is generated, the transistor -1,1--40v!
becomes the second Et)Vtl. At this time, the transistor -
1, 1-1 is a high invidae vagina jjllllml
is equal to the fourth figure. That is, operation line 1111 state KTh''1 ・□・j stripe 1100) 9ydx#1-
1.1-2 does not give II/AII''e self-output Kl effect. As mentioned above, according to the single-source Ij1, it does not affect operation, and when not in use, for example, L8I It is possible to prevent the transistor □ from being destroyed by static electricity during storage and transportation.

なお、本実施例は出力端子に本発明を適用した場合であ
るが、入力端子に本発明を適用しても同勢の効果が得ら
れゐ事祉勿論である。
Although this embodiment is a case in which the present invention is applied to an output terminal, it is of course possible to obtain the same effect even if the present invention is applied to an input terminal.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を宗すwJ%j12WJは□
 ≠プレ、シWシ麗トッンジメタのVtと基盤電位の関
係を示す図、第3図は電源投入前の第1図の出力端子部
の等価回路を示す図、第4図は電源投入螢の第1図の出
力端子部の等価1路を示す図、である。 なお図において、1−1.1−2・・・・・−デプレ。 ’/ W 3/I!NCh )ツンジスタ、1−3.1
−4.1−3.3−4.4−3.4−4・・・・・・エ
ンハンスメント1llNch)ツーンジスタ、1−5・
旧・−基盤電位発生回路、1−6 、3−6 I 4−
6−−−−”−出力端子、3−113−2””−’デプ
レff VW yllNch )ランジスタの替個抵抗
、である。 第2図 第3閏 −4 第4図
Figure 1 shows an embodiment of the present invention where wJ%j12WJ is □
≠ A diagram showing the relationship between Vt and base potential of the pre- and current switch metals. Figure 3 is a diagram showing the equivalent circuit of the output terminal section of Figure 1 before power is turned on. Figure 4 is a diagram showing the equivalent circuit of the output terminal section of Figure 1 before power is turned on. 2 is a diagram showing one equivalent path of the output terminal section of FIG. 1. FIG. In addition, in the figure, 1-1.1-2...-Depres. '/W 3/I! NCh) Tunjista, 1-3.1
-4.1-3.3-4.4-3.4-4...Enhancement 1llNch) Tunister, 1-5.
Old・-Base potential generation circuit, 1-6, 3-6 I 4-
6----"-output terminal, 3-113-2""-'depreff VW yllNch ) transistor replacement resistor. Figure 2 Figure 3 Leap-4 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁ゲート製電界効果トランジスタで構成された
半導体集積回路装置において、前記集積回路の端子と接
地間にデプレッシ璽ン型トランジスタが接続され、前記
デプレッション型トランジスタのゲート電極は前記接地
に接続され、前記デプレッション歴トランジスタを非導
通状態とせしめる基盤電位を発生する基盤電位発生回路
を内蔵した事、を特徴とする半導体装置。
(1) In a semiconductor integrated circuit device configured with an insulated gate field effect transistor, a depressing type transistor is connected between a terminal of the integrated circuit and the ground, and a gate electrode of the depressing type transistor is connected to the grounding. . A semiconductor device comprising a built-in base potential generation circuit that generates a base potential that causes the depletion history transistor to become non-conductive.
(2)デプレ、シ、ン型トランジスタが集積回路の端子
と電源間に接続された事を特徴とする特許請求の範囲第
(1)項記載の半導体集積回路装置。
(2) A semiconductor integrated circuit device according to claim (1), characterized in that a double-sided, thin-type transistor is connected between a terminal of the integrated circuit and a power supply.
JP56141900A 1981-09-09 1981-09-09 Semiconductor integrated circuit device Pending JPS5843624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56141900A JPS5843624A (en) 1981-09-09 1981-09-09 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56141900A JPS5843624A (en) 1981-09-09 1981-09-09 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5843624A true JPS5843624A (en) 1983-03-14

Family

ID=15302768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56141900A Pending JPS5843624A (en) 1981-09-09 1981-09-09 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5843624A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6311421A (en) * 1986-06-30 1988-01-18 Kubota Ltd Transmission structure of working vehicle
US5854569A (en) * 1994-11-15 1998-12-29 Mitsubishi Denki Kabushiki Kaisha Current source for rapid switching and reduced oscillatory transients

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6311421A (en) * 1986-06-30 1988-01-18 Kubota Ltd Transmission structure of working vehicle
JPH0526686B2 (en) * 1986-06-30 1993-04-16 Kubota Kk
US5854569A (en) * 1994-11-15 1998-12-29 Mitsubishi Denki Kabushiki Kaisha Current source for rapid switching and reduced oscillatory transients

Similar Documents

Publication Publication Date Title
US4409501A (en) Power-on reset circuit
US5034845A (en) Integrated circuit apparatus including static electricity protection circuit
US6650520B2 (en) Power supply reverse bias protection circuit for protecting both analog and digital devices coupled thereto
KR920022678A (en) Data input buffer of semiconductor memory device
JPS6237819B2 (en)
JP2652061B2 (en) Intermediate potential generation circuit
KR970072377A (en) Protection circuit
JPS5843624A (en) Semiconductor integrated circuit device
JPS61277227A (en) High voltage insulation circuit
US6271692B1 (en) Semiconductor integrated circuit
JPH0379120A (en) Input protecting circuit
US6633468B1 (en) High voltage protection circuit for improved oxide reliability
JP2598147B2 (en) Semiconductor integrated circuit
KR910001775A (en) Semiconductor memory
JPH06237124A (en) Input protection circuit for differential amplifier
KR100307514B1 (en) Charge pump circuit
JPS58122695A (en) Input overvoltage protection circuit
JPH07101710B2 (en) MIS integrated circuit electrostatic protection device
JP2544157B2 (en) Semiconductor integrated circuit device
JPH04213869A (en) Circuit device for terminal protection use at integrated circuit
JP3250249B2 (en) Constant current charging circuit
JPS59169225A (en) Integrated circuit
JPH1127855A (en) Rush current preventive circuit
US6151199A (en) Semiconductor integrated circuit device
KR960025766A (en) Electrostatic discharge protection circuit