JPS5843576A - Compound semiconductor field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive the high performance of elements, by effectively shortening an electrode length and reducing series resistances between source.gate and gate.drain. CONSTITUTION:A trapezoidal part 14 is formed on a semi-indulating GaAs substrate 11, a source region conductive layer 15 and a drain region conductive layer 16 are respectively provided on both sides of the trapezoidal part 14, an N type GaAs active layer 17 is provided over the upper surface of the trapezoidal part 14, the surface of the source region conductive layer 15 and the surface of the drain region condutive layer 16, and a gate electrode 18 having an electrode length longer than the upper side of the trapezoidal part 14 is provided on the surface of this N type GaAs active layer 17. Therefore, a gate electrode region active layer participating in the control action of the gate electrode 18 is only the N type GaAs active layer 17 on the upper surface of the trapezoidal part 14. Since the gate electrode length effectively corresponds to the upper side length of the trapezoidal part 14, high performance element by reducing the gate length are easily attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a planar type high performance compound semiconductor field effect transistor and a method for manufacturing the same.

It is well known that field effect transistors with compound semiconductor substrates such as GaAa or InP exhibit much better performance in the area of ultra-high frequency and ultra-high speed signal processing than those with so-called silicon substrates. In order to improve the performance of the gate, shortening the gate length,
It is important to reduce the series resistance between the source and ff-) and between the gate and drain. However, in order to realize the above, there are manufacturing difficulties such as manufacturing a gate electrode with a fine structure, precise control of the thickness of the active layer in the dirt electrode region, and precise mask alignment of the gate electrode and source/drain electrodes. Is there a problem? 1. A breakthrough based on completely new ideas is required in the structure of the device and its manufacturing method.

Figure 1 shows a structural diagram of a typical conventional compound semiconductor field effect transistor. Figure 1 (,) shows an n-type G
An aAs active layer 2 is formed, and a Schottky junction gate electrode 3, an ohmic contact source electrode 4, and a drain electrode 5 are provided thereon. Figure 2(b) shows n-type GaA
This structure, in which a trench 6 is provided in a part of the active layer 2 and a Gunite electrode 3 is provided therein, has the following important drawbacks. First, Figure 1 (a) and (b) both show r21! Immediately below the electrode 3 is an n-type GaAs active layer 2 with a uniform thickness, and the gate length involved in controlling the electron flow in the n-type GaAs active layer 2 is r-1, which is the length of the electrode 3 itself. In order to shorten the gate length, r-1.
Since it is necessary to shorten the length of the electrode 3 itself, we are faced with limitations in microfabrication for forming the gate electrode. Mahe1::1-
Focusing on each series resistance between the source and f-1- and between the gate and drain, in the case of Figure 1 (,), it is the same as that of the gate electrode area active layer (lean-type GaAs active layer 2 directly below the gate electrode 3). Since a series resistance is formed in the thick n-type GaAs active layer 2, the distance between the source and drain is shortened and the matching accuracy for securing the relative position to the r-1 electrode 3 is at its limit. will be decided. In the case of Fig. 1(b), it is necessary to make the digging part 6 slightly larger than the length of the case-1 electrode.In addition, the relative alignment accuracy of the gate electrode 3 with respect to the digging part 6 becomes a problem. In order to control the thickness of the active layer in the gate electrode area, precise control of both the thickness of the n-type GaAs active layer 2 and the depth of the trench 6 is required. This becomes a major obstacle in the implementation of IC.

Figure 2 is a diagram showing an example of the manufacturing process of a compound ± conductor field effect transistor of the present invention.
An insulating film such as z2o'31 S'3N4 is provided, a resist material is applied, and exposure drawing is performed using the resistor 142° as a mask. .

1. Leaving the insulating film 13. ..., 1. In the step shown in FIG. 2(b), the trapezoidal portion 14 is formed by selectively etching the semi-insulating GaAa substrate 11 using an etching solution such as sulfuric acid or phosphoric acid using the insulating film 13 as a mask. The trapezoidal part 14 is
For example, if the length of the insulating film 13 is 1 .mu.m and the amount of etching of the semi-insulating GaAs substrate 11 is 0.25 .mu.m, the length of the upper side will be 0.5 .mu.m due to the lateral etching effect. Nahomoshijis 1 and 12 are semi-insulating GaAs substrates 1
Although it may be removed before etching step 1, if it is left until after etching, short-time dielectric etching step 13 is performed before removing resist 12, and semi-insulating GaAs substrate 11 is removed.
It is possible to remove the eave-like protrusions on the periphery of the edge film 13 that are caused by etching. Next, in the step shown in FIG. 2(C), an n-type GaAs source region conductive layer 15 and drain region conductive layer 16 are selectively epitaxially grown using the insulating film 13 as a mask. The growth thickness is set so that the surface is almost flush with the surface.As the epitaxial growth method for compound semiconductors, known methods such as vapor phase growth using a normal halogen method, organometallic pyrolysis CVD, 9-molecular beam epitaxial method, etc. In the case of selective epitaxial growth using the insulating film 13 as a mask, these epitaxial growth methods may be used.

Depending on the growth conditions such as temperature, the presence of eaves-like protrusions at the periphery of the insulating film 13 may be partially effective in planarizing the selective epitaxially grown layer, and removal of the eaves-like protrusions described above may be effective. In the process shown in FIG. 2(d), the insulating film 13 is first removed. In this case, depending on the type and growth conditions of the selective epitaxial growth in the previous step, an amorphous compound semiconductor layer may be formed on the insulating film 1-3. Such a layer is also removed at the same time.

Next, an n-type GaAs active layer 1 is placed over the trapezoidal part 14 on the surface of the source region conductive layer 15 and the surface of the Drayshi region conductive layer 16.
7 is epitaxially grown. n-type GaAs active layer 1
2, the source region conductive layer 15, and the drain region conductive layer 16 are of the same conductivity type and have substantially similar impurity concentrations. Then, in the process shown in FIG. 2(,), a Schottky junction case 1 electrode 18 having an electrode length longer than the upper side of the trapezoidal part 14 is provided on the surface of the n-type GaAs active layer 17, and a source electrode 18 with an ohmic contact is formed. 19 and 'by providing the drain electrode 2o) the present compound semiconductor field effect l.
2' The compound semiconductor field effect transistor of the present invention has a structural feature that a trapezoidal part 14 is formed on a semi-insulating GaAa substrate 11, and a source region conductive layer 1 is formed on each side of the trapezoidal part 14.
5 and a drain region conductive layer 16 are provided.
An n-type GaAs active layer 17 is provided across the surface of the n-type GaAs active layer 17, and a dart electrode 18 having an electrode length longer than the upper side of the trapezoidal portion 14 is provided on the surface of the n-type GaAs active layer 17. .

Therefore, □f- is involved in the control action of the gate electrode 18.
1-electrode area active layer is n-type Ga on the upper surface part of the trapezoidal part 14.
There is only an As active layer 17, and the gate electrode length effectively corresponds to the length of the upper side of the trapezoidal part 14. As mentioned above, the upper side of the 0.5 μm trapezoidal part of the 1 μm mask is the voice.

It is easy to form, and even if a gate electrode with a length of 1 μm is provided,
1 Since the effective gate electrode length is 0.5 μm,
High performance devices can be easily achieved by shortening the gate length.
...=2,
・Also, since the thin dart electrode active layer is directly connected to the thick source region conductive layer 15 and drain region conductive layer 16, additional series resistance can be minimized, greatly contributing to higher performance. do.

- According to the manufacturing method of Rikiki's invention, the same insulating film 13 is used in the steps of selective etching to form the trapezoidal part 14 and selective epitaxial growth to form the source region conductive layer 15 and drain region conductive layer 16. Since it can be used as a mask, it simplifies the process and eliminates the need for mask alignment between processes. r-1・electrode area active layer thickness is
In contrast to the conventional method shown in FIG. 1(b), which depends on the difference between the active layer growth thickness and the etching depth, controllability is good because it is determined only by the active layer growth thickness. Furthermore, since the gate electrode 18 can be made longer than the effective gate electrode length,
Control of the length of the date electrode 18 and) la-1-electrode 18
The mask alignment accuracy system for relative positioning of the joint part 14 and the joint part 14 is relaxed, and the manufacturing yield is reduced to 1o□,,%1゜ゎI.
Isa. '□6゜1 As explained and described above, according to the compound semiconductor field effect transistor and the manufacturing method thereof of the present invention, the gate electrode length can be effectively shortened and the distance between the source and gate and between the gate and gate can be effectively shortened.
Since it is possible to reduce the direct resistance between the drains, it is possible to improve the performance of the device, simplify the manufacturing process, improve the manufacturing yield, and achieve uniform characteristics.
Excellent effects such as easy conversion can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a conventional compound semiconductor field effect transistor, and FIG. 2 is a diagram showing -flj of the manufacturing process of the compound semiconductor field effect transistor of the present invention. DESCRIPTION OF SYMBOLS 11... Semi-insulating compound semiconductor substrate, 12... Insulating film, '14... Trapezoidal part, 15... N-type GaAs source region conductive layer, 16... N-type GaAs drain region conductive layer )'ji,"... n-type GaAs active layer, 18...
gate electrode. (b)

Claims (2)

[Claims] (1) a semi-insulating compound semiconductor substrate having a trapezoidal portion on its upper surface; a conductive layer of one conductivity type provided on both sides of the trapezoidal portion so that its surface is approximately the same as the upper surface of the trapezoidal portion; an active layer of the same conductivity type as the conductive layer of the lower conductivity type provided on the upper surface of the trapezoidal part and the surface of the conductive layer of the conductivity type; 1. A compound semiconductor field effect transistor comprising: a dart electrode having a long dart electrode length. (2) A step of performing selective etching on a semi-insulating compound semiconductor substrate using an insulating film as a mask to form a trapezoidal part, and masking the insulating film so that the selectively etched part is filled with a conductive layer of one conductivity type. a step of epitaxially growing an active layer of the same conductivity type as the conductive layer of the -conductivity type on the upper surface of the trapezoidal part and the surface of the conductive layer of the -conductivity type; 1. A method for manufacturing a compound semiconductor field effect transistor, comprising the step of providing an r-1 electrode having a dart electrode length.