JPS5843546A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5843546A JPS5843546A JP56141689A JP14168981A JPS5843546A JP S5843546 A JPS5843546 A JP S5843546A JP 56141689 A JP56141689 A JP 56141689A JP 14168981 A JP14168981 A JP 14168981A JP S5843546 A JPS5843546 A JP S5843546A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- shielding film
- ray shielding
- polyimide
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明線新規な方法でｇｉｇａ蔽膜を形成し九半導体装
置Ｋｌｌするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a novel method for forming a giga shielding film and manufacturing a semiconductor device.
一般１１、Ｆランジスタ等が形成された半導体素子はセ
ラミック封正体、樹脂封止体などの封止体で封止される
。これらの封止体にはウラニウムやトリウム等の不純物
が含まれている。General 11. A semiconductor element in which an F transistor or the like is formed is sealed with a sealing body such as a ceramic sealing body or a resin sealing body. These sealed bodies contain impurities such as uranium and thorium.
これらの不純物は、たとえば、１６ｔｈ Ａｓｓｔｗｓ
ｌハｖａａｇｄｉｖ４ａｏｆ １９７Ｂ １ｓｔａｒｔ
ｓａｔｉｔｎｗｈｌ Ｒ５１ｉａｈｉ１４ｔｙ Ｐｈｙ
ｓｉｃｓ〜ｔｑ）ｍｓｉｍ／゛
（１９７８）ｐ３３ に述べられているように、ａ□
線を放出１半導体素子内に形成されたグイナンツクメモ
リ卯路の誤−作（ソフトエラと呼ぶ）の賛因となること
が知られている。These impurities are, for example, 16th Asstws.
lhavaagdiv4aof 197B 1start
satitnwhl R51iahi14ty Phy
sics~tq)msim/゛(1978) p33, a□
It is known that emitting wires can lead to errors (referred to as soft errors) in the memory circuits formed in semiconductor devices.
このソフトエラ、を防止する方法の一つとして、半導体
素子の表面にａＩＩ迩蔽膜形成ける方法が知られている
。ｆ！ＩＮｌ蔽膜は、形成Ｐ以上の厚膜形成が可能であ
ること、半導体素子の封止工程に耐えるだけの耐熱性を
有すること、−線発生源のつλモウムやトリウムおよび
素子に悪影響を及ぼすナトリウムなどの不純物含有量が
極めて小さいこと、などの特性￥を有している必要があ
る。これらの特性を満足する材料として一ポリインド系
樹脂が好んで用いられて−る。As one method for preventing this soft error, a method is known in which an aII shielding film is formed on the surface of a semiconductor element. f! The INl shielding film must be able to be formed into a thicker film than the formation P, have heat resistance sufficient to withstand the sealing process of semiconductor elements, and must be free from radiation sources such as λmoum and thorium, which have an adverse effect on the elements. It must have characteristics such as extremely low content of impurities such as sodium. Monopolyindo resin is preferably used as a material that satisfies these characteristics.
ポリイミド系樹脂ｔ−ｔｔａｙａ形成に用いた半導体素
子としては、第１図に示すように、半導体基体１ｔ−パ
ッケージの所定の位置にグイボンディングし、さらに外
部接続のためにボンディングワイヤ２を接着し良後、ポ
リイミド系樹脂膜３ｔ−ポツティングで形成１ついで、
第２図のように、セラミック封正体で気密封止したもの
が広く製造されている。この場合、通常、ポリイミド系
樹脂膜３は第１図に示しであるように、半導体基体の全
面を覆って＞９１．；ディングワイヤの一部にもかかっ
て匹る。第２図で示した１−、う表気密封止の場合はこ
の構造で全く問題な一札第６図で示すような樹脂封止し
喪場合社、−ンデイングワイヤにかかつているポリイミ
ド系ディングワイヤ切れを生じて素子の信頼性が著しく
低下する。As shown in FIG. 1, the semiconductor element used for forming the polyimide resin t-ttaya was bonded to a predetermined position of the semiconductor substrate 1t-package, and bonding wires 2 were bonded for external connection. After that, a polyimide resin film is formed by 3T-potting, and then
As shown in FIG. 2, those hermetically sealed with a ceramic sealing body are widely manufactured. In this case, the polyimide resin film 3 usually covers the entire surface of the semiconductor substrate and has a diameter of >91 mm, as shown in FIG. ;It also hangs over a part of the ding wire. As shown in Figure 2, in the case of air-tight sealing, this structure is completely problematic.In the case of resin sealing as shown in Figure 6, the polyimide-based bonding wire is used. This causes the cutting wire to break, significantly reducing the reliability of the device.
セラミック封止Ｏような気密對止紘製造コストが高く、
樹脂封止への移行が必然となって−る。このためには、
前述のワイヤ切れを防止する手段が必要である。The production cost of airtight seals such as ceramic seals is high;
A shift to resin sealing has become inevitable. For this purpose,
There is a need for a means to prevent the aforementioned wire breakage.
この問題ｔ−同避するために鉱、第４図で示すように、
少なくと本ポンディングパッド部金除く領域のみにｆｉ
１ｍ蔽膜を形成する必要がある。しかし従来から用いら
れて込るポツティング法ではａ！！遮蔽膜の形状をコン
トロニルすることはできず、少なくともポンディングパ
ッド部を除く領域のみにα線遮蔽ｌ［を形成することは
できな１０、；！
本発明はかかる現状を鑑みてなされたものであ広その目
的は、簡易な方法で樹−封止可能なａｍｍ蔽ｍｉ形成し
た半導体装置を提供することにある。To avoid this problem, as shown in Figure 4,
At least the area excluding the bonding pad part should be fi
It is necessary to form a 1 m thick film. However, the conventional potting method uses a! ! It is not possible to control the shape of the shielding film, and at least it is not possible to form α-ray shielding only in the area excluding the bonding pad part10;! The present invention has been made in view of the current situation, and its broad purpose is to provide a semiconductor device having an amm-shield structure and which can be sealed by a simple method.
すなわち、本発明は、半導体素子表面に、ポンディング
パッド部を除くように、＃！Ｉｉ蔽膜形成膜形成領域に
堰會設け、ついで−線遮蔽用樹脂をポツティングして形
成したことを特徴とする半導体装蝋に関するものである
。That is, in the present invention, the #! The present invention relates to a semiconductor wax which is characterized in that it is formed by providing a weir in the Ii shielding film forming region and then potting -ray shielding resin.
壜は、少なくともｌンデイングバットにａｍｍｍｍ用膜
用ポツティング樹脂れ込まないように形成すればよい。The bottle may be formed in such a way that at least the potting resin for the ammmm film does not get into the binding vat.
ポンディングパッド各ｋｔ−丁ぺて堰で囲んでもよい。Each pounding pad may be surrounded by a weir.
また、第５“図に示すように、ポンディングパッドを含
む工→ジ部ゆき素子の中央部を囲むように形成してもよ
い。Alternatively, as shown in FIG. 5, it may be formed so as to surround the center of the element including the bonding pad.
堰の材料としては、ｅｔｌｊｉを放出するウラニウム、
トリウム表どの放射性元素や素子の％注に悪影響を及ぼ
すナトリウムイオンなどの金属イオン含有量が小さく、
かつ、α線遮蔽膜のボッティング工程および樹脂封止工
程に耐えるだけの耐熱性のあるものでなければならない
。The materials for the weir include uranium, which emits etlji;
The content of metal ions such as radioactive elements such as thorium and sodium ions, which have a negative effect on the percentage of elements, is small.
In addition, it must be heat resistant enough to withstand the botting process and resin sealing process of the α-ray shielding film.
堰の材料としては、シリコーン樹脂、芳香族ポジアンド
、芳香族ポリアミドイミド、芳香族ポリイミド系樹脂な
どが例として挙げられるが、これらに限定されない。ポ
リイミド系樹脂がとくに好ましく用いられる。Examples of the material for the weir include, but are not limited to, silicone resin, aromatic posiand, aromatic polyamideimide, and aromatic polyimide resin. Polyimide resins are particularly preferably used.
堰の形成紘素子管形成し終ったウエーノ・段階で行なう
のが望まし１０例えば素子を形成し終った？ニーＡＫ、
ポリイオド系樹脂の前駆体淋液を塗布して、ついで、フ
ォトリソグラフィ法などで堰を形成する。It is preferable to perform the weir formation at the stage after the element tube has been formed.For example, when the element tube has been formed. Knee AK,
Gonorrhea, a precursor of polyiodide resin, is applied, and then a weir is formed by photolithography or the like.
−ａｍ形成用樹脂のボッティングは堰を形成し終ったウ
ェーハプロセスの段階で行なってもよ−し、ウェー／Ｎ
からチップを切り出し、リードフレームに堆りつけた後
に行なってもよい。後者の場合、ボンディングワイヤ接
続前後のいずれでもよい。-Botting of the am forming resin may be done at the stage of the wafer process after the weir has been formed, or the wafer/N
This may be done after cutting out the chip from the material and attaching it to the lead frame. In the latter case, it may be done either before or after the bonding wire is connected.
ａｌｉ迩蔽膜形成脂は、堰の材料と同様に、ウラニウム
、ト” リウム、ナ）９ウムなどの不純物の含有量が小
さく、かつ、樹脂封止工程に耐えるだけの耐熱性が必要
である。Similar to the weir material, the ali-covering film-forming fat must have a low content of impurities such as uranium, thorium, and sodium, and must have sufficient heat resistance to withstand the resin sealing process. .
ａ＠遮蔽膜用樹脂としては、シリコーン樹脂、芳香族ボ
リア宅ド、芳香族ポリアミトイ建ド、芳香族ポリイミド
系樹脂などが例として挙げられるが辷れらに限定される
もので拡なへこれらの中では、ポリインド系樹脂が好ま
しく用いられる。Examples of resins for the shielding film include silicone resins, aromatic boria resins, aromatic polyamide resins, and aromatic polyimide resins, but these are limited to resins and cannot be expanded. Among these, polyindo resins are preferably used.
ポリイミド系樹脂とは、テトラカルボン酸二無水物とジ
アミンとを反応させるか、またはこの系にさらにトリア
さン、テトラミン、ジアミノモノアンド、トリカルボン
酸−無水物、ジイソシアネートまたはその他の共重合可
能な化合物から選ばれた化合物を共重合成分として共存
させて反応させて得たポリアミド酸系樹脂ｔ、熱または
化学的手段で閉環して得られるものである。通常、閉ｊ
ｊｌ前の前駆体の形で実用に供せられているｏ
：、：・１□ヮＴｂｊａ＊ｚ’ｌ−ｙ益お
、７あ、ヵ８、。イオド系樹脂の場合、フォトレジスト
およびヒドラジン系あるい・はアルカリ水溶液系エッチ
ャントの助妙を借シて行なうむとができる。Polyimide resin is produced by reacting tetracarboxylic dianhydride and diamine, or by adding triamino, tetramine, diamino monoand, tricarboxylic acid anhydride, diisocyanate, or other copolymerizable compounds to this system. A polyamic acid-based resin t obtained by coexisting and reacting a compound selected from the following as a copolymerization component, and a polyamic acid-based resin t obtained by ring-closing by heat or chemical means. Usually closed
o which is in practical use in the form of a precursor before jl
：、：・１□ヮTbja＊z'l-y benefit o, 7a, ka8,. In the case of iodo-based resins, this can be carried out with the aid of photoresists and hydrazine-based or alkaline aqueous etchants.
また、感光性ボリイぐド系樹脂を用いると、この壜の形
成工程が著しく合理化できる。感光性ポリイミド系樹脂
とは、前記のポリイミド系樹脂の前駆体に感光基金導入
したもので、フォトレジストおよびエッチャントの助は
管借夕ないでパターン加工することが可能となる。Furthermore, the use of photosensitive polyimide resin can significantly streamline the process of forming the bottle. A photosensitive polyimide resin is a precursor of the polyimide resin described above into which a photosensitive resin is introduced, and it becomes possible to process a pattern without using a photoresist or an etchant.
ポリイミド系樹脂の原料であるテトラカルボン酸二無水
物の例としては、ピロメリット酸二無水執ベンシフ！ノ
ンテトラカルボン絃二無水物、ビフェニルナト２カルボ
ン酸二無水物やす７タレンテトラカルポン酸二無水物な
どの芳香族テトラカルボン酸二無水物が挙けられるが、
これらに限定されるもので社な匹。゛
、−・リ
ジアミンの例ト′□しては、ジアミノジフェニルエーテ
ル、シアｉノジフェニにスルホン、シアζフジフェニル
メタン、ビス（３−７ミノプロビル）テトラメチルジシ
ロキサンなどが挙げられるが、これらに限定されるもの
ではない。An example of tetracarboxylic dianhydride, which is a raw material for polyimide resin, is pyromellitic dianhydride! Examples include aromatic tetracarboxylic dianhydrides such as nontetracarboxylic dianhydride, biphenylnato dicarboxylic dianhydride, and 7talentetracarboxylic dianhydride;
The company is limited to these. Examples of lydiamines include, but are not limited to, diaminodiphenyl ether, cyanodiphenyl sulfone, cyanodiphenylmethane, bis(3-7minoprobyl)tetramethyldisiloxane, etc. It's not a thing.
テトラカルボン酸二無水物、ジアミンと共重合可能な化
合物の例としては、３・４・４′−トリアミノジフェニ
ルエーテル、３−モノアミド−４・４′−ジアミノジフ
ェニルエーテル、３・４・３′・４′−テトラアミノジ
フェニルエーテル、トリメリット酸無水物塩化物、４・
４′−ジフェニルエーテルジイノシアネートなどが例と
して挙げられるが、これらＫｍ定されるもので鉱ない。Examples of compounds copolymerizable with tetracarboxylic dianhydride and diamine include 3,4,4'-triamino diphenyl ether, 3-monoamide-4,4'-diaminodiphenyl ether, and 3,4,3',4. '-Tetraaminodiphenyl ether, trimellitic anhydride chloride, 4.
Examples include 4'-diphenyl ether diinocyanate, but these Km are not determined.
′
感光基とは、光（通常、紫外光）を照射した時、ポリイ
ミド系１１４４＠またはその前駆体の架橋構造管形成し
、特定の溶剤への溶解性會低下させる効果のあるもので
ある。感光基の例として、メタクリル基、アクリル基、
アリル基、メタリル基、シンナメート基、アジド基など
が挙げられるが、これらには限定されない。'A photosensitive group is a group that forms a crosslinked structure of polyimide 1144@ or its precursor when irradiated with light (usually ultraviolet light) and has the effect of reducing the solubility in a specific solvent. Examples of photosensitive groups include methacrylic group, acrylic group,
Examples include, but are not limited to, allyl group, methallyl group, cinnamate group, and azide group.
ポリイミド系樹脂の前駆体に感光基を導入する方法とし
ては、ポリイミド系樹脂の前駆体の溶液に、ビスアジド
化合物、ジメチルアミノエチルメタクリレ−Ｆ１アリル
アンンなどを混合する方法がで例として挙げられる。An example of a method for introducing a photosensitive group into a polyimide resin precursor is a method of mixing a bisazide compound, dimethylaminoethyl methacrylate-F1 allyl amine, etc. into a solution of the polyimide resin precursor.
また、次のよ□うな感光基を有する化合物音シア２ンと
共重合す６方法もあり一’
ｏら愼
鳴
感光性ポリイミド前駆体線、通常、溶媒中で合成また紘
調合され、溶液の形で実用に供せられる。また、感光性
ポリイミド前駆体の溶液には、通常、感度【上げるため
に、ミヒラーズ・ケトンのような光開始剤が加えられる
。There are also 6 methods of copolymerizing with a compound having a photosensitive group, such as the following:
The photosensitive polyimide precursor wire is usually synthesized or mixed in a solvent, and then put to practical use in the form of a solution. Additionally, a photoinitiator such as Michler's ketone is usually added to the photosensitive polyimide precursor solution to increase sensitivity.
堰の幅、高さは、ａ線遮蔽膜形成用樹脂をポツティング
した時、樹脂が壜を越えないように選択する必要がある
。これらの値は、−線鐘形成の厚さ、増肉に滴下し友時
の樹脂の表面張力などにより異雀る。堰の幅については
堰と半導体基体の接着性が十分保圧れればよく、とくに
制限蝶ないが、通常５０μ以上あれば十分である。堰の
高さは、通常膚線鐘形成の厚さより低くてもよ１０通常
、値線遮蔽膜は３０〜１００μの膜厚で形成されている
が、堰の高さ絋この膜厚の半分位の厚さにはした方がよ
い。しかし、ａＳＳ蔽膜形成用ボッティくグ樹脂や表面
張力が大きく、かつ流動性の小さ一場合鉱、さらに堰の
膜厚１會薄くすることができる。The width and height of the weir must be selected so that when the resin for forming the A-ray shielding film is potted, the resin does not exceed the bottle. These values vary depending on the thickness of the -line bell formation, the surface tension of the resin when dripping into the thickening layer, etc. Regarding the width of the weir, it is sufficient that the adhesiveness between the weir and the semiconductor substrate is sufficiently maintained, and although there is no particular limit, a width of 50 μm or more is usually sufficient. The height of the weir is usually lower than the thickness of the skin line formation.Normally, the line shielding film is formed with a thickness of 30 to 100μ, but the height of the weir is about half of this film thickness. It is better to make it as thick as possible. However, in the case of a Bottig resin for forming an aSS coating film, which has a high surface tension and low fluidity, the film thickness of the weir can be made one inch thinner.
次に実施例に基づいて本発明を説明する。Next, the present invention will be explained based on examples.
実施例 １． 、
素子を形成したシリコン・ウェー／）全面に、ポリイミ
ド前駆体のワニスである東し電子絶縁コーティング剤′
″ＳＰ−’１１０”全膜厚（キ工ア後）が３０μになる
ノ：：廉に塗布した。１５０ｔｌ：で３０分間乾燥した
。Example 1. The entire surface of the silicon wafer on which the device was formed is coated with Toshi Denshi Insulating Coating Agent, a varnish made of polyimide precursor.
"SP-'110" was coated at a low price so that the total film thickness (after keying) was 30 μm. It was dried at 150 tl for 30 minutes.
この上に、ネガ型フォトレジストである東京応化（株）
０ターンが形成されるようなフォトマスクを用いて、仁
の７オトレジストに紫外１ＩＮ−照射りつ匹で、フォト
レジストの現像を行なった。ヒドラジンヒトラードを用
いてポリ信Ｖｆに
ラテン・グした後、フォトレジストを剥離して、第５図
に示すようなポリイミドのｊＩＩＩを形成し良。On top of this, Tokyo Ohka Co., Ltd., which is a negative photoresist,
Using a photomask in which 0 turns were formed, the photoresist was developed by irradiating 1 IN of ultraviolet light onto the 7-layer photoresist. After laminating the polyurethane Vf using hydrazine hydrogen, the photoresist is removed to form a polyimide jIII as shown in FIG.
ウェーハからチップを切夛出ム リードフレームに固定
しワイヤ・ボンデ・インクを行なった。ついで堰の中へ
ベンゾフェノンテトラカルボン酸二無水物とジアミノジ
フェニルエーテルから合成されたポリ信ド前駆体のＮ−
メチルピロリ）’ン溶液（１７％ 、 １３０−Ｗ’７
Ｘ／ ３０ Ｃ） ｋａｌｉ下ＬＡＩＳＯＣ１２５０℃
、３５０Ｃテ各に３０分Ｍ’−Ｌ７しテ＃ｉ！ａ蔽ａｔ
形成した。最も厚い部分の膜厚１ｊａｏ、ｐであった。Chips were cut out from the wafer, fixed to a lead frame, and wire bonded and inked. Next, the N-
Methylpyrrolidine solution (17%, 130-W'7)
X/30C) LAISOC 1250℃ under kali
, 350C for 30 minutes each M'-L7 and Te#i! a cover at
Formed. The film thickness at the thickest part was 1 jao, p.
この時、ａ！Ｉ！蔽膜は形成？みに形成場れた。ついで
、樹脂封止を行なった。At this time, a! I! Is the membrane formed? It was a formation place. Then, resin sealing was performed.
ポンゲイングヮイヤには”１１！蔽膜がかかっていない
ので、第３図で示すよう表ワイヤの切断は生じなかった
。Since the ponge wire was not covered with a ``11!'' shield, no breakage of the front wire occurred as shown in FIG.
実施例 ２゜
ベンゾフェノンテトラカルボン酸二無水物とジアミノジ
フェニルエーテルから合成されたポリイミド前駆体のＮ
−メチルピロリドン溶液に、ジメチルアｔノエチルメタ
クリレートおよびンヒラーズ・ケトンを添加して感光性
ポリイミド前駆体溶液を得良。Example 2 N of polyimide precursor synthesized from benzophenone tetracarboxylic dianhydride and diaminodiphenyl ether
- A photosensitive polyimide precursor solution was obtained by adding dimethyl at-noethyl methacrylate and NH3-ketone to the methylpyrrolidone solution.
素子を形成したシリコンウェーハに該感光性ポリインド
前躯体溶液’ｉｎ布ＬＡ ８０Ｃで１時間乾燥した。実
施例１と同じフォトマスクを使用して紫外ｓＹｔ照射し
、ついで、現像液で現像を行なった。１３０Ｃ、２５Ｇ
’Ｃ、４００Ｃで各３０分づつキュアすることにより、
膜厚２０７１１のポリイミドの壜ｔ−，を九。The silicon wafer on which the device was formed was dried with the photosensitive polyind precursor solution 'in cloth LA 80C for 1 hour. Ultraviolet sYt irradiation was performed using the same photomask as in Example 1, and then development was performed with a developer. 130C, 25G
By curing at 'C and 400C for 30 minutes each,
A polyimide bottle t-, with a film thickness of 20,711 mm.
実施例１と同様に、テップｔ−ａＳ出しり−ド７レーム
に取シつけ、さらにワイヤボンディングした後、ａ線遮
蔽膜用樹脂を滴下した。最も厚一部分の膜厚紘５．０μ
であったが、項内のみに形成されていた。ついで、樹脂
封止を行なった。７In the same manner as in Example 1, it was attached to the step t-aS extension frame and wire bonded, and then the resin for the a-ray shielding film was dropped. Film thickness at the thickest part: 5.0μ
However, it was formed only within the term. Then, resin sealing was performed. 7
第１図はａｆｇ連蔽偵を半導体基体上にボッティング法
によ、。
シ形成した半導体基体の断面図、第２図は七ラミック封
止した半導体装置の断面図、第３図は本発明の方法によ
）樹脂封止した半導体装置の断面図、＃Ｉ４図紘ポンデ
ィング・パッドｍｔ除く部分にａＩｍ遮蔽膜を形成（牟
半導体基体の断面図、第５図杖本発明により、堰とａ線
適藪膜會形成した半導体奉体の平面図、第６図にボッテ
ィング法によ５＃Ｉｉ遮蔽膜を形成し、樹脂封止した半
導体素子の断面図である。
１・・・・・・半導体基＆ ２−７．”・ボンデ、イ
ンクワイヤ、３，３３・・・・・・ａ線遮蔽膜、４ 、
５−・・・・・セラミック封止体、６・・・・・・シー
ルガラス、７・・・・・・リード、８・・・・・・樹脂
封止体、９・・・・・・ポンディングパッド、１０・・
・・・・壜、１１・・・・・・ａｌｉ趣蔽膜形成脂封地
体の界面。
１１回
１１３図
３
を畑
Ｏ
３３ｌ
冨４図
冨６ｕFigure 1 shows an afg serial probe placed on a semiconductor substrate by the botting method. Figure 2 is a cross-sectional view of a semiconductor device sealed with a resin by the method of the present invention, Figure #I4 is a cross-sectional view of a semiconductor device sealed with a resin according to the method of the present invention. An aIm shielding film is formed on the area excluding the ding pad mt. 1 is a cross-sectional view of a semiconductor element on which a 5#Ii shielding film is formed by the tinging method and sealed with resin. ...A-ray shielding film, 4,
5-... Ceramic sealing body, 6... Seal glass, 7... Lead, 8... Resin sealing body, 9...... Ponding pad, 10...
. . . Bottle, 11 . . . Interface of ali-screening film-forming fat sealing body. 11 times 113 Figure 3 Field O 33l Tomi 4 Figure Tomi 6u
Claims (3)
脂封止してなる半導体装置において、該＃ｉｉ碑蔽膜形
成ボンディング、＜ラド部を除（ように、肩線遮蔽膜形
成領域の周辺に壜を設け、ついてｇ＊ａ蔽膜形成脂ｔボ
ッティングして形成したこと全特徴とする半導体装置。(1) In a semiconductor device formed by forming a CiI shielding film on the surface of a semiconductor element and sealing with a resin, the #ii shielding film forming bonding is carried out in the vicinity of the shoulder line shielding film forming area (excluding the radius area). A semiconductor device characterized in that the semiconductor device is formed by providing a bottle and then botching a g*a shielding film.
ｌｉ遮蔽用樹脂がポリイミド系樹脂からなっていること
を特徴とする特許請求の範囲第１項記載の半導体装置。(2) The weir is made of polyimide resin and AI
2. The semiconductor device according to claim 1, wherein the Li shielding resin is made of polyimide resin.
されたこと全特徴とする特許請求の範囲第１項記載の半
導体装置。(3) The semiconductor device according to claim 1, characterized in that the bottle is formed using a photosensitive polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141689A JPS5843546A (en) | 1981-09-10 | 1981-09-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141689A JPS5843546A (en) | 1981-09-10 | 1981-09-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5843546A true JPS5843546A (en) | 1983-03-14 |
Family
ID=15297922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56141689A Pending JPS5843546A (en) | 1981-09-10 | 1981-09-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5843546A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4801998A (en) * | 1984-08-20 | 1989-01-31 | Oki Electric Industry Co., Ltd. | EPROM device |
-
1981
- 1981-09-10 JP JP56141689A patent/JPS5843546A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4801998A (en) * | 1984-08-20 | 1989-01-31 | Oki Electric Industry Co., Ltd. | EPROM device |
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