JPS5843031A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To ensure an optional correction of gain for an A/D converter as a whole, by selecting switching for an input signal and two reference voltages via a multiplexer and supplying it to an analog-digital converter. CONSTITUTION:An analog signal SI is led into a channel 1 of a multiplexer MPX, and the reference voltages EV1 and EV2 are supplied to the channels 2 and 3. The output signal SXO selected by the multiplexer MPX is led into an arithmetic processing part CPU via an A/D converter CAD. The output SCR is led out via a D/A converter CDA and driving parts DR1 and DR2 and also fed to the multiplexer MPX. Then the gain characterisitics of the converter CAD is controlled in accordance with the voltages EV1 and EV2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital conversion device that digitizes analog data and enables the data to be taken in, for example, by a digital combination converter.

OK for adjusting the gain of this kind of analog-to-digital (hereinafter referred to as "A") converter, such as the A/D included in it.
It was common to adjust the variable resistor in the converter. Also, if you do not adjust the variable resistor, etc., the A/D
It was necessary to configure the transducer to be highly accurate. Since the gain adjustment based on such a M/D conversion is calibrated at the input of this A/D converter, a 1/" C 7) 1111 etc. In this case, the level shift circuit etc. must also be calibrated.

In addition, the gain adjustment of the A/D conversion device is performed by
There is a drawback that the method must be adjusted depending on the gain of the /D converter, multiplexer, etc.

In view of the above-mentioned points, it is an object of the present invention to calibrate the gain of the entire A/D converter regardless of differences in gain in individual circuits constituting the A/D converter.
To provide a long-lasting A/D conversion device that does not require calibration of a level shift circuit even if a level shift circuit is provided in a preceding stage of a converter.

The present invention will be described in detail below based on the following.

FIG. 1 shows an electronic device that performs A/D conversion and digital-to-analog (hereinafter referred to as D/A) conversion to which the present invention is applied. Here, multiplexer MPX.

The number of human channels is 5, and the analog input signal SI is introduced into the channel l CHI, and the channel 2 C112
Reference voltage EVI is applied to each channel 3 and CH3.
and 1iN2 (=+ 1Ivl-), respectively. The switching operation in the multiplexer MPX is performed based on the control signal port 2 from the arithmetic processing unit CPU, and the output signal SxO selected for switching is sent to the mu/D converter CAD.
supply to. The converted digital signal 8AD obtained by the MU/D converter CAD is introduced into the arithmetic processing unit CPU,
Necessary calculations are performed based on this signal BAD. Digital signal 8CRw based on the calculation result D/mu converter C
Two analog signals SAI and SMU 2 are introduced into the DM.
and supplies each of them to the output drive unit DRI and the output drive unit DR2. Okayama force drive unit DR
The Okayama force signals 801 and 802 of I and DR2 are used as output signals of this electronic device, and the multiplexer MPX
(D channel 4 CH4 and channel) The operation with the above configuration will be explained.The offset and gain calibration of the device shown in FIG. Turn on the device and
Start the calibration operation.

Multiplexing is performed by the control signal CMX from the arithmetic processing unit CPU. MPX O switching operation to channel 2 CH2
(Step 211). Next, RAM is used to store data necessary to perform calculations within the calculation processing unit CPU.
The above gain adjustment term Y KAD and offset term are set to 0F.
Let it be FAD. KAD of these terms = 1, OF
'FAD-0 is set (step 213). By the way, by selecting the channel 201i2 of the multiplexer MPX, the reference voltage 11VI is selected to 0, which becomes the output signal SXO of the multiplexer MPX, and is sent to the arithmetic processing unit C as the signal SAD digitized by the mu/D converter CAD.
Supplied to PU. Let it be an internal representation t-XVI based on the measurement of the signal SAD in the arithmetic processing unit CPU at that time.

It is also common to use multiplexer MPX for channel I CH
Let X be the internal representation of the arithmetic processing unit CPU O when switching to I and measuring the voltage v of the analog input signal 8I, and let tvl be the internal representation of the voltage corresponding to the voltage EVI. In such a state, in step 215, an operation expressed by the following general formula is executed based on the subprogram IK shown in FIG.

X@ = KM) ((X10FFAD) -Vl
) +V1 (1) Also, this offset term 0PFQ
, is 0FFAD = Vl −XVI'
Since it is given by (2), by (1) II
! JIIl: Output data Xo is XQ=4=X+ (V
l −XVI ) (3). Therefore, there is no effect of offset in the A/D conversion path. That is, 1, step 215, the obtained voltage v, O internal data Xo (7XVt
), the offset term OFM) on the RAM corresponding to the offset of the entire A/D conversion operation should be added.
” (Vl-XVI), first Stella, j
Replace with @ o II set in 213 (Step 2
20). In this way, by performing simple calculations within the arithmetic processing unit CPU, there is no need for offset adjustment of the A/D converter including the MU/D converter q. In addition, it is possible to cope with changes in the offset due to changes in the circuit profile during manufacture over time. .

Next, gain adjustment will be explained. , multiplexer wpx,
Switch KV2 so that t' channel 30HI is selected
The digital signal SAD is subjected to V/D conversion and is supplied to the arithmetic processing unit CPU. This arithmetic processing 1 part CPU,
The reference voltage EE W24D is expressed as XV2. Also, generally analog input, signal S! Let t-x be the internal representation of the voltage 2, and the internal table 7C14 of the voltage corresponding to the reference voltage EV2 and the execution of the sub/program IY. Due to the initial setting in step 213, the gain KAD=1. Therefore, X=((XV20FF4D) −Vl)+Vl
(4) is calculated. In addition, off 4t term 9FFJJ
) is as set in step 220 (,0FFAD =V
1- XVI Te & Ru, (4 formula is,
). From this, XV2-XVI =X-Vl (6
) is obtained.

Also, in the general formula including interest @ KAD, V2=KAD
((XV2-FoFFAD)-Vl)+V1 (7
). From equations (4) and (7), the gain KADY
If you ask for it, you will get . By substituting the expression ←) into the expression (°), t is obtained.

It is possible to perform calculations according to this equation (9).

In this way, by performing simple calculations in the J6m111 CPU, the module including the A/D converter CAD t' can be
Gain adjustment of the entire D conversion section is unnecessary. Furthermore, it is possible to deal with changes in the state of the device over time.

Next, the D/A converter C and output driver DRI.

Calibration including DR2 will be explained. The flow of the operation is shown in tg s 5 (2), @ and yu. Here, first, the control signal cmo command from the calculation m1ascpu! Channel 4CH4 is switched and selected in the multiplier MPX (step 311). This selects the output power. Next, in the arithmetic processing unit CPU, the gain adjustment term KDAl of the D/MU conversion output 1 is initialized to 1, and the offset adjustment term 0FFDMU1 of the D/MU conversion output 1 is initialized to 0 (step 313). Thereafter, the data Xr to be digitized and output is set as the reference value DAVI in the arithmetic processing unit CPU (step!15). In this state, in step 317, the following (10
) is executed based on the subprogram 2 shown in the aS diagram (B).

Xo=KAD1(Xr-DAVI)+DAV1+0FF
DAl (10) Here, XO is the actual output data,
Xr is the data to be output. This data
A digital signal SCR representing - is supplied from the arithmetic processing section CPU to a D/m converter CAD. A signal SAI t-
The output signal 801 is supplied to a total of six driving units DRI, and its output signal 801 is supplied to an A/D converter CAD via a multiplexer MPX. The signal SAD digitized by the A/D converter CAD is read by the arithmetic processing unit CPU. The reading is carried out in step 321 by executing the subprogram 1'4 shown in FIG. uses the values already set up to step 235 for calculation.

The read output data XrO is compared with the reference setting value 1sAvt to determine whether it falls within a predetermined range (±a) or not. That is, it is determined whether the data Xro'a exceeds the reference setting value Dmuv10 by a predetermined amount (step 5=3). If Xro ) DAVI + δ (: affirmative), reduce the offset adjustment term 0FFr) AI by a predetermined minute amount (step 3!5), step 32
Move to 7. If a negative determination is made in step 323 (X
r・≦DAVI −1-8), then the data XrQ
It is determined whether or not ' is less than the reference setting value DAVI minus the predetermined amount (step 329). If affirmative judgment (X
If ro<DAVI−δ), the offset adjustment term 0FFD
After increasing AI by a predetermined minute amount (step 331), the process returns to step 3154C and repeats the above-described operation. In other words, (lO
) Perform calculations according to the formula (step 317) 0th order -
Then, the read output data Xr obtained in step 3rl
If O is l Xro DVAI l )-, then D
After decrementing (step 325) or incrementing (step 3m1) the offset adjustment term 0FFDAI of /m conversion, the above-described operation is repeated in a loop.

If it converges within the range of l Xro -DVAI l <, δ, an affirmative determination is made in step 329, and the loop is extracted.

As a result, the D/mu converter CDmu and the output section #DR
Offset calibration of the D/MU converter of output 1 included in 1 is performed.

By repeating simple calculations in the arithmetic processing unit CPU in this manner, offset adjustment of the set value in D/MU conversion is unnecessary, and it is possible to compensate for changes over time.

With the offset term 0FFDAI of D/A conversion being calibrated, the output child data Xr is output in the arithmetic processing unit CPU.
t' DAVIK () DAVI) K setting (x - r rough 35L). Scolding him, step 363
, execute subprogram 2 shown in Figure 3 (II).The output data xO at that time is: Xo = KADI (DAVIK - DAVI) +
DAVl +0FFI)Al. This data
The C-based analog output signal 801V1 is digitized by the A/D converter G via the multiplexer MPXv. The voltage of the digital signal 801 is read. Next, the 1 arithmetic processing unit CPU performs calculations according to (1) 2 (Q
The reading output data XrO is determined using the subgrograph ^IK shown in (step 35s). This data Xre is the setting value DAV previously set in step 381.
It is determined whether IKllj% is correct. That is, first, it is determined whether the data XrO is larger than the set value DAVIK (
Step S67), il constant judgment (Xrl)) D
AVl, K) Narach, D/A conversion gain KDAI
V is reduced by a minute amount (step 3511), and step 3
51 K go back. Further, in step 357, a negative determination (X
If ro < DAVIK ), then it is determined whether the data XrO is smaller than the set value DAVIK (step 3
61). If the determination is affirmative (Xro (DfflK)), the D/A conversion gain KDAI is increased by a very small amount (step 363), and the process returns to step 351.

Based on the value of the new gain KDAI that was decremented or incremented in step 3811 or 363, new data XO''4I: is determined in step 353 according to equation (10).
Based on this, in step 355, read output data xor is obtained. The above operation is repeated in a loop until this data XOr becomes equal to the set value DAVK1. When the read output data XrO becomes equal to the set value Dmu■l, step 3
At 61, a negative judgment is made, and a loop extraction is issued. As a result, the D/mu converter C and output drive 11DR1yL-
The gain KDAI in the included D/A converter is calibrated.

　　　.

In this way, by performing simple calculations in the arithmetic processing unit CPU, the gain tone of the D/MU conversion can be set to 11t-unnecessary, and it is also possible to cope with changes in gain characteristics over time.

@S The operations shown in diagrams (2) to (Q)
Output 1c) with PX as channel 4 CH4) Offset of D/mu conversion path) 0FFDAI and gain Dmuzo calibration 't'. A similar calibration operation is performed by switching multiplexer 1 to channel 5 CH5 and output driver 2...
Offset of D/mu conversion path at power 2) is also possible for 0FFDmu2 and gain Dmu2. If it is an output type, it is 8 in the flow chart of Iris 3 (2), and step 5x
In step 351, select the set value DAV2][V for the output 2, and set the se initialization to the gain KDAI and OR to the output j.
) to (Q). Therefore, for 11 and output 2, channel 4C of the D/mu converter CDM, output driver, and multiplexer MPX.
The offset and gain of the D/A conversion path in H4 can be calibrated.

As described in detail above, according to the present invention, it is possible to eliminate the drawbacks of the conventional technology and to realize an advantageous device that can be applied to electronic devices that perform A/D conversion and D/M conversion, for example.

[Brief explanation of the drawing]

111all is an analog-digital device to which the present invention is applied
(f) is a flowchart showing the operation of the iris 1 diagram. . SI - Analog input signal, MPX... Multiplexer, EVI, 1! v2...Reference voltage,
CMX...control signal, CAD...analog-digital converter, ODA...digital-analog converter, C
PU...Arithmetic escape unit, DRI, DR2...
・Output drive unit. Patent applicant: Canon Co., Ltd. (A)

Claims (1)

[Claims] l) Arithmetic processing after converting the analog input signal into a digital signal using an analog-to-digital converter! In an analog-to-digital converter processing by 1iIs, 2
two reference voltage sources and a multiplexer are provided, the input signal and two reference voltages of the two reference voltage sources are switched and selected by the multiplexer, and the selected signal is supplied to the analog-to-digital converter. An analog-to-digital converter that controls the gain characteristics of the converter according to the two reference voltages.