JPS5842255A - Semiconductor mounting substrate having multilayer wiring and manufacture thereof - Google Patents

Semiconductor mounting substrate having multilayer wiring and manufacture thereof

Info

Publication number
JPS5842255A
JPS5842255A JP14061381A JP14061381A JPS5842255A JP S5842255 A JPS5842255 A JP S5842255A JP 14061381 A JP14061381 A JP 14061381A JP 14061381 A JP14061381 A JP 14061381A JP S5842255 A JPS5842255 A JP S5842255A
Authority
JP
Japan
Prior art keywords
film
60min
insulating film
heated
conductor wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14061381A
Other languages
Japanese (ja)
Inventor
Atsushi Endo
厚志 遠藤
Toshio Yada
矢田 俊雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14061381A priority Critical patent/JPS5842255A/en
Publication of JPS5842255A publication Critical patent/JPS5842255A/en
Pending legal-status Critical Current

Links

Landscapes

  • Weting (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain high reliable multilayer wiring structure having no crack and pin hole by a method wherein after an insulating film consisting of heat resisting high polymer is covered with a chemically resistive film of photo resist, etc., and patterning is performed, openings are formed by selective etching. CONSTITUTION:After the Toreyneece film 9 of heat resisting high polymer resin on a semiconductor mounting substrate 8 is dried for 60min at 90 deg.C in the nitrogen atmosphere, it is heated for 60min at 180 deg.C, and is heated for 60min at 380 deg.C in succession in the same atmosphere to be hardened. Then aluminum is evaporated on the film 9, and patterning is performed to form the first layer conductor wiring layer 10. The Toreyneece film 11 is formed thereon, it is heated for 60min at 90 deg.C, and for 60min at 180 deg.C in the nitrogen atmosphere, and after it is hardened once, selective etching is performed to remove the film, and the opening parts 12 are formed. The photo resist is removed, and is heated for 30min at 380 deg.C in the nitrogen atmosphere to perform the hardening treatment, and the second layer conductor wiring layer 13 is formed according once more to the process mentioned above.

Description

【発明の詳細な説明】 この発明は多層配線をもつ半導体装基板とその製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor substrate having multilayer wiring and a method for manufacturing the same.

半導体集積回路は1枚の半導体基体内に、トランジスタ
、ダイオード、抵抗などの回路素子を多く集積して構成
するために、基体表面に必要な配線を一平面で形成する
と、配線が長くなって大暑な両横を必要としたシ、交叉
によって配線自体が不可能になる場合がToシ、このた
めに従来は必要な配線を、眉間絶縁膜の介在で多層に形
成するようにしてお〉、同様な理由でセラミック基板、
プリント基板などに多層配線を形成し、その上に7リツ
プチツプlンデイングなどで半導体素子を実装するよう
にしている。
Semiconductor integrated circuits are constructed by integrating many circuit elements such as transistors, diodes, and resistors in a single semiconductor substrate, so if the necessary wiring is formed on one plane on the surface of the substrate, the wiring becomes long and causes heat waves. However, in some cases, the wiring itself becomes impossible due to crossing, so conventionally, the necessary wiring was formed in multiple layers with an insulating film between the eyebrows. Ceramic substrate for reasons,
Multilayer wiring is formed on a printed circuit board or the like, and semiconductor elements are mounted thereon by 7-lip chip mounting or the like.

従来Oこのgo多層配**造につき、半導体集積回路を
Hにとって第1図に示す。すなわち、この従来例では、
トランジスタ、ダイオードなどの半導体素子を組み込ん
だシリコンウェハ(1)上に、保護膜としての所定位置
に接続用開口をあけた二酸化シリコン膜(2)を形成さ
せ、かつこの上にアルミニラムなどの導体金属の蒸着と
そのパターニング、蝕刻除去により第1層目の金属被膜
による導体配線層(3)を形成させ、さらにその上に気
相成長あるいは高周波スパッタにより、層間絶縁膜とし
ての二酸化シリコン膜(4)を介して第2層目の導体配
線層(5)を同様に形成させており、配線層(3) 、
 (5)間は接続用開口(6)によ〉接続させるように
している。
The conventional multilayer structure is shown in FIG. 1, with the semiconductor integrated circuit designated as H. That is, in this conventional example,
A silicon dioxide film (2) with connection openings formed at predetermined positions as a protective film is formed on a silicon wafer (1) incorporating semiconductor elements such as transistors and diodes, and a conductive metal such as aluminum is formed on this film. A conductive wiring layer (3) is formed by vapor deposition, patterning, and etching to form a first layer of metal film, and then a silicon dioxide film (4) is formed as an interlayer insulating film by vapor phase growth or high-frequency sputtering. A second conductor wiring layer (5) is similarly formed via the wiring layer (3),
(5) is connected through a connection opening (6).

と\でこのような従来の多層配線構造では、導体配線層
(3) 、 (5)間の層間絶縁膜として二酸化シリコ
ン膜(4)を形成させるのに、最低450℃の温度条件
を必要とすること、i九これによって下層の配線層を形
成しているアルミニウムなどにヒルロックなどの微小突
起を生ずることのために次のような問題点がある。
In such a conventional multilayer wiring structure, a temperature condition of at least 450°C is required to form the silicon dioxide film (4) as an interlayer insulating film between the conductor wiring layers (3) and (5). However, this causes the following problems because minute protrusions such as hillocks are formed on the aluminum forming the underlying wiring layer.

すなわち、第1には、微小突起のために、その上に堆積
される二酸化シリコン膜(4)に多数のピンホールを生
じさせて、両導体配線層(a) 、 (5)間を短絡さ
せる点でLJ)、また第2には、温度条件から、ウェハ
(1)、二酸化シリコン膜(2) 、 (4)および導
体配線層(3) 、 (5)O相互の熱膨張係数の差異
により亀裂を生ずる点で、特に二酸化シリコン膜+2>
 、 (4)を厚く堆積させたときに問題となる。そし
て第3には、二酸化シリコン膜(2) 、 (4)にあ
けられる開口(6)の壁面が、ウェハ(1)K対して垂
直に近い形状となるために、導体金属の蒸着が充分厚く
なくて、この部分で配線層(3) 、 (5)が断線す
る場合がある点でアシ、さらに第4には、導体配線層(
3)の凹凸のために、二酸化シリコン膜(4)がその段
差部分(7)で充分に堆積せず、両配線層(a) 、 
(5)間が短絡する慣れが多ることである。
That is, first, the microprotrusions cause a large number of pinholes in the silicon dioxide film (4) deposited thereon, causing a short circuit between the two conductor wiring layers (a) and (5). point LJ), and secondly, due to the temperature conditions, due to the difference in thermal expansion coefficient between the wafer (1), the silicon dioxide films (2), (4), and the conductor wiring layers (3), (5)O. In particular, silicon dioxide film +2>
, (4) becomes a problem when deposited thickly. Thirdly, since the walls of the openings (6) formed in the silicon dioxide films (2) and (4) have a shape close to perpendicular to the wafer (1) K, the conductive metal is deposited sufficiently thickly. There is a problem in that the wiring layers (3) and (5) may break at this part, and fourthly, the conductor wiring layer (
Due to the unevenness of 3), the silicon dioxide film (4) is not sufficiently deposited on the stepped portion (7), and both wiring layers (a),
(5) There is a tendency for short circuits to occur.

従ってこの発明の目的は、従来の多層配線構造のこのよ
うな欠点を改善し九多層配線をもつ半導体装基板とその
製造方法を提案することであシ、この目的を達成する丸
めに、この発明では導体配線層間の絶縁膜として、ポリ
イミド、ポリアミドなどの耐熱性、熱硬化性高分子物質
を用い、かつその熱処理を制御するようにしたものであ
る。
Therefore, an object of the present invention is to improve such drawbacks of the conventional multilayer wiring structure and to propose a semiconductor board having multilayer wiring and a method for manufacturing the same. In the present invention, a heat-resistant, thermosetting polymeric material such as polyimide or polyamide is used as the insulating film between the conductive wiring layers, and the heat treatment thereof is controlled.

こ\でこの種の高分子物質は、耐熱性、熱硬化性である
tlかに耐薬品性に富み、かつ化学的に安定した材料で
あるが、この材料によって得られた層間絶縁膜としての
高分子樹脂膜については、導体配線層間の電気的導通を
とるだめの開口部エツチングを制御性よく形成する手段
がなかった。そこでこの発明では、特に熱硬化処理を工
夫して配線構造を改良したものである。
This type of polymer material is heat resistant, thermosetting, chemical resistant, and chemically stable; Regarding polymer resin films, there has been no means for forming etched openings with good controllability to establish electrical continuity between conductive wiring layers. Therefore, in this invention, the wiring structure is improved by particularly devising the heat curing process.

以下、この発明の一実施例について詳細に説明するO まず配線構造の改良と密接に関係する高分子樹脂膜の加
工性につき、特に熱処理の観点から述べる。
Hereinafter, one embodiment of the present invention will be described in detail. First, the processability of the polymer resin film, which is closely related to the improvement of the wiring structure, will be described from the viewpoint of heat treatment in particular.

よく知られているように熱硬化性高分子樹脂膜は、未硬
化の樹脂を熱処理によや硬化させて形成しており、この
処理には2′:)の目的がおる。その1つは樹脂中に含
まれている溶媒を蒸発させることでアリ、他の1つはポ
リアミック状態で存在している樹脂に脱水反応を生じさ
せてポリイミドを形成させることである。そしてこの熱
処理を適正になさないと、得られる樹脂膜の加工性に関
して次のような問題を生ずる。すなわち、熱処理を低温
(80℃以下)で行なうと均一な被膜を形成できず、そ
の結果として多くの場合、被膜に対するエツチング速度
が早くなって、開口部が過剰にエツチングされ、その制
御性が悪化する不利があり、また熱処理を高温(400
℃以上)で行なうと、溶媒蒸発あるいはイミド化による
水の発生で被膜中に気泡を生じ、かつ表面に凹凸があら
れれるもので、この現象は未硬化の樹脂を、樹脂中溶媒
の沸点以上の温度に一巻なシ装置したときにも同様(ト
レニースの場合、溶媒dN−N’ジメチルアセトアミド
、沸点は163℃)で、その結果として被膜の加工性を
低下させ、多く0場合、開ロ部のエツジあるいはコーナ
ーのきれ、断面形状などのノ(ターニング性が悪化する
ことになる。
As is well known, a thermosetting polymer resin film is formed by partially curing uncured resin by heat treatment, and this treatment has the purpose of 2':). One method is to evaporate the solvent contained in the resin, and the other method is to cause a dehydration reaction in the resin existing in a polyamic state to form polyimide. If this heat treatment is not carried out properly, the following problems will occur regarding the workability of the resulting resin film. In other words, if heat treatment is performed at low temperatures (below 80°C), a uniform film cannot be formed, and as a result, in many cases, the etching rate of the film increases, resulting in excessive etching of the openings and poor controllability. There is a disadvantage in that the heat treatment is carried out at high temperature (400℃).
℃ or higher), water generation due to solvent evaporation or imidization causes bubbles to form in the film and unevenness to the surface. The same thing happens when the device is heated to a certain temperature (in the case of TRENICE, the solvent is dN-N' dimethylacetamide, the boiling point is 163°C), and as a result, the processability of the coating is reduced, and in many cases, the opening part is Sharp edges or corners, cross-sectional shapes, etc. (turning performance will deteriorate).

第3図はFレニース被膜のエツチング速度の硬化時間依
存性につき、硬化温ltTを)くラメータにとりて示し
たものであシ、エツチング液としてはヒドラジン100
IIjとエチレンジアミン400wLlとからなる混合
液を用いて20℃一定とした。この第3図からも、熱処
理温度が高い場合、エツチング速度が著るしく遅くなる
ことが判る。そしてこのエツチング速度の低下は、前記
したように開口部のエツジ、コーナーのきれ、断面形状
を悪くすると同時に作業性の低下を招くもので、さらに
熱処理時間を短かくした場合、溶媒蒸発が不充分になっ
て、その結果、被膜の均一性が悪くなり、同様に加工性
を低下させるものであった。
Figure 3 shows the curing time dependence of the etching rate of the F-lenice coating, using the curing temperature ltT as a parameter.
A mixture of IIj and 400 wLl of ethylenediamine was used to maintain a constant temperature of 20°C. It can also be seen from FIG. 3 that when the heat treatment temperature is high, the etching rate becomes significantly slow. As mentioned above, this decrease in etching speed causes the edges of the openings, sharp corners, and poor cross-sectional shape, as well as a decrease in workability.Furthermore, when the heat treatment time is shortened, the solvent evaporates insufficiently. As a result, the uniformity of the coating deteriorated, and processability was similarly reduced.

このように高分子樹脂膜の熱処理については種々の問題
点があるので、耐熱性高分子樹脂からなる絶縁被膜で被
覆した多層配線をもつ半導体装基板の製造に際しては、
これらの各点に留意して製造方法を定める必要がある。
As described above, there are various problems with heat treatment of polymer resin films, so when manufacturing semiconductor substrates with multilayer wiring covered with an insulating film made of heat-resistant polymer resin,
It is necessary to take these points into consideration when determining the manufacturing method.

次に第2図に示す一実施例に基き、特に耐熱性高分子樹
脂からなる絶縁被膜の選択的加工手段に注目して詳細に
述べる。
Next, a detailed description will be given based on an embodiment shown in FIG. 2, focusing in particular on selective processing means for an insulating coating made of a heat-resistant polymer resin.

まず半導体装基板として30■口のセラミック基板(8
)〔京都セラミック社製〕を用い、これを通常の方法で
洗浄し、この基板(8)上に耐熱性高分子樹脂であるト
レニース(樹脂分17−2粘度1.000cp) (東
洋レーヨン社製、半導体グレード〕時間60秒)で形成
し九のち、直ちに窒素雰囲気中で90℃、60分間乾燥
して、大部分の溶媒(N−N’−ジメチルアセトアミド
)を蒸発させてから、同雰囲気中で180”060分間
、 ツいf380’o。
First, a 30-inch ceramic substrate (8
) [manufactured by Kyoto Ceramic Co., Ltd.], washed in a normal manner, and placed on this substrate (8) a heat-resistant polymer resin, Trenice (resin content 17-2, viscosity 1.000 cp) (manufactured by Toyo Rayon Co., Ltd.). , semiconductor grade] for 60 seconds), and then immediately dried in a nitrogen atmosphere at 90°C for 60 minutes to evaporate most of the solvent (N-N'-dimethylacetamide), and then dried in the same atmosphere. At 180"060 minutes, Tsui f380'o.

60分間加熱して硬化させる。これによって得られた被
膜(9)の厚さは約6 pmであった。
Heat and cure for 60 minutes. The thickness of the coating (9) thus obtained was approximately 6 pm.

ついで前記基板(8)の被膜(9)上に、アルミニウム
を通常の方法で蒸着させ、これを同様に通常の写真蝕刻
法によシ所定の配線パターンにパターニングして厚さ約
o、7I1mの第1層目の導体配線層(11を形成する
。セしてまえその上には前記と同様のトレニース被膜(
11)をスピン塗布法(回転数4.00Orpm、回転
時間60秒)で形成させ、同様に窒素雰囲気中で90℃
、60分間オヨび180”o、60分間加熱して一旦硬
化させ、約3μm厚さの被膜aυを得る。さらにこの上
には、フォトレジストOMB ’83〔ネガ型東京応化
社製、粘度lo cp)を用い、周知の写真製版法によ
シ所定のパターンを形成させ、トレニース被膜a1)の
所要部分をこの約0.55声m厚さのフォトレジストで
覆ったのち、ヒドラジン100−とエチレンジアミン1
00−からなるエツチング液(液温20℃)に約3分間
浸漬し、露出部分のトレニース被膜を選択的にエツチン
グ除去して開口部(lIJを形成する。さらに続いて通
常の方法でフォトレジストを除去した上で、窒素雰囲気
中で380℃、30分間加熱して硬化処理し、かつさら
にもう一度前記手順によシ第2層目の導体配線層−を形
成する。すなわち、このようにして層構造の配線層をも
つ半導体装基板を製造した。
Next, aluminum is vapor-deposited on the coating (9) of the substrate (8) by a conventional method, and this is similarly patterned into a predetermined wiring pattern by a conventional photolithography method to a thickness of approximately 0.7 mm. A first conductive wiring layer (11) is formed.Before this, a trenice film (11) similar to that described above is applied.
11) was formed by a spin coating method (rotation speed 4.00 rpm, rotation time 60 seconds), and similarly coated at 90°C in a nitrogen atmosphere.
, heated for 60 minutes at 180" o and heated for 60 minutes to once cure to obtain a film of about 3 μm thickness. Furthermore, on top of this, a photoresist OMB '83 [negative type manufactured by Tokyo Ohka Co., Ltd., viscosity lo cp ) was used to form a predetermined pattern by a well-known photolithography method, and the required portions of the trenise film a1) were covered with this photoresist with a thickness of about 0.55 mm, and then hydrazine 100 and ethylenediamine 1
00- (solution temperature: 20°C) for about 3 minutes to selectively remove exposed portions of the trenise film to form openings (lIJ). After removal, the layer structure is cured by heating at 380° C. for 30 minutes in a nitrogen atmosphere, and a second conductive wiring layer is formed by the above procedure again. A semiconductor circuit board with a wiring layer of

仁のようにして得られる半導体装基板は、それぞれに形
成される被膜(9)、αυの表面が平坦であシ、このた
めに被膜(11)を介して交叉する各導体配線層a呻、
(13の部分a◆にはとんど段差がなく、従って段差に
よる配線の断線を生ずることがない。また高分子樹脂に
よる被膜は、導電材料とその熱膨張係数が真なっていて
も、その違いによって生ずる内部応力を充分に吸収する
から、実用上充分なに亀裂を生ずることもない。さらに
絶縁性、耐熱性につめても充分な籠を有していて、信頼
性の高い配線構造体が得られる。
The semiconductor device substrate obtained in this manner has flat surfaces of the film (9) and αυ formed on each, and therefore, the conductor wiring layers a, which intersect through the film (11),
(There is almost no level difference in the part a◆ of 13, so there is no chance of wiring breakage due to the level difference.Also, even if the polymer resin coating has the same coefficient of thermal expansion as the conductive material, Since it sufficiently absorbs the internal stress caused by the difference, it does not cause cracks in practical use.Furthermore, it has sufficient insulation and heat resistance, making it a highly reliable wiring structure. is obtained.

なお前記実施例では、半導体装基板としてセラミック基
板を用いたが、プリント基板、ガラス基板などであって
よく、耐熱性高分子からなる絶縁被膜としても、トレニ
ースのほかにPIQ(日立化成社製) %t PYLA
L I N (Du −Po n を社製〕などのポリ
イミド樹脂、HI−600(日立化成社製〕などのポリ
アミトイζド樹脂を用いることができる。
In the above embodiment, a ceramic substrate was used as the semiconductor substrate, but it may be a printed circuit board, a glass substrate, etc. In addition to TRENICE, PIQ (manufactured by Hitachi Chemical Co., Ltd.) may be used as an insulating coating made of a heat-resistant polymer. %t PYLA
Polyimide resins such as LIN (manufactured by Du-Pon Co., Ltd.) and polyamide zeta resins such as HI-600 (manufactured by Hitachi Chemical) can be used.

ま九前記実施例で杜、多層配線を有する半導体装基板の
構造として、配線導体を2層としたが、技術的に容易に
予想されるように、よシ以上の多層配線にすることがで
き、同様に第1導体配線層を半導体容器上に直接形成す
ること、もしくは絶縁被膜上に直接形成することなどは
、基板表面の平坦性その他から適宜に選択できるところ
である。
In the above embodiments, the structure of the semiconductor circuit board having multilayer wiring was made with two layers of wiring conductors, but as can be easily expected from a technical standpoint, it is possible to have multilayer wiring with more than one layer. Similarly, forming the first conductive wiring layer directly on the semiconductor container or directly on the insulating film can be selected as appropriate depending on the flatness of the substrate surface and other factors.

さらに前記実施例では、導体配線層間の耐熱性高分子か
らなる絶縁被膜の厚さを3μmとしているが、絶縁破壊
強度、絶縁被膜に形成される開口寸法その他から、その
厚さを適宜に選択してよく、この被膜厚さは樹脂粘度、
スピナー回転数などの調節により容易に制御できる。
Further, in the above example, the thickness of the insulating film made of heat-resistant polymer between the conductor wiring layers is 3 μm, but the thickness can be selected as appropriate based on the dielectric breakdown strength, the size of the opening formed in the insulating film, etc. This coating thickness is determined by the resin viscosity,
It can be easily controlled by adjusting the spinner rotation speed, etc.

そしてまた導体配線層の材料としても、アルミニウムの
ほかに金、モリブデン、ニッケル、鋼。
In addition to aluminum, gold, molybdenum, nickel, and steel are also used as materials for conductor wiring layers.

白金、チタンなどの1)4るいは2つ以上を組み合わせ
九合金、もしくは2つ以上の多重膜としてもよく、これ
らはアルミニウム単独で用いるよりは機械的強度、熱的
安定性に優れている。
A combination of two or more of platinum, titanium, etc. may be used as an alloy, or a multilayer film of two or more of these materials has better mechanical strength and thermal stability than aluminum alone.

以上詳述したようにこの発明によれば、ポリイミド、ポ
リアミドイミドなどの耐熱性高分子からなる絶縁被膜を
用い、この絶縁被膜をホトレジストなどの耐薬品性の被
膜でパターニング被覆した上で、選択的にエツチング開
口させるから、同開口部での絶縁被膜の傾斜角を制御で
き、併せてこの開口を通して接続される上下各導体配線
層の段差部における断線を解消し得られ、しかも絶縁被
膜は熱処通によって生ずる内部応力を吸収し得るから亀
裂、ピンホールがなく信頼性の高−多層配線構造を構成
でき、さらに絶縁被膜は周知の写真製版技術によ抄形成
できるために従来の設備をそのまま利用できるなどの特
長がある。
As detailed above, according to the present invention, an insulating film made of a heat-resistant polymer such as polyimide or polyamide-imide is used, and this insulating film is patterned and coated with a chemical-resistant film such as photoresist, and then selectively Since the opening is etched in the opening, it is possible to control the inclination angle of the insulating film at the opening, and it is also possible to eliminate disconnections at the stepped portions of the upper and lower conductor wiring layers that are connected through this opening. Because it can absorb internal stress caused by wiring, a highly reliable multilayer wiring structure can be constructed without cracks or pinholes.Furthermore, the insulating coating can be formed by papermaking using well-known photolithography technology, so conventional equipment can be used as is. It has features such as being able to

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の方法による多層配線構造の半導体基板を
示す断面図、第2図はこの発明方法の一実施例を適用し
た多層配線構造の半導体装基板を示す断面図、第3図は
耐熱性高分子からなる絶縁被膜の加工性を示す説明図で
ある。 (8)・・・・セラミック基板、(91、(Jυ・・・
・絶縁被膜、Q(1、Q3・・・・導体配線層、oz・
・・・開口部。 代理人 葛野信−(#1が1名) 第1図 第2図 第3図 刃穴化澗朋(を)
FIG. 1 is a cross-sectional view showing a semiconductor substrate with a multi-layer wiring structure made by a conventional method, FIG. 2 is a cross-sectional view showing a semiconductor substrate with a multi-layer wiring structure to which an embodiment of the method of the present invention is applied, and FIG. 3 is a heat-resistant FIG. 2 is an explanatory diagram showing the workability of an insulating coating made of a synthetic polymer. (8) Ceramic substrate, (91, (Jυ...
・Insulating coating, Q(1, Q3...conductor wiring layer, oz.
···Aperture. Agent Makoto Kuzuno - (#1 is one person) Figure 1 Figure 2 Figure 3 Kanatomo Haana

Claims (1)

【特許請求の範囲】[Claims] (1)基板上に耐熱性高分子からなる絶縁被膜を介して
導体配線層を多層に形成すると共に、これらの各導体配
線層間を絶縁被膜に形成した開口部を通して接続したこ
とを特徴とする多層配線をもつ半導体装基板。 (刀基板上に耐熱性高分子からなる第1の絶縁被膜を形
成する工程と、この第10絶縁被膜上の少なくとも一部
に所定パターンO第1の導体配線層を形成する工程と、
この第1の導体配線層上に耐熱性高分子からなる第2の
絶縁被膜を形成する工程と、この第2の絶縁被膜に選択
的に導体間接続のためO開口部を形成する工程と、この
開口部を含んで第2の絶縁被膜上に少なくとも一部が嬌
在する所定パターンの第20導体配線層を形成する工程
とを備えたことを特徴とする多層配線をもつ半導体装基
板の製造方法。
(1) A multilayer structure characterized in that conductor wiring layers are formed in multiple layers on a substrate via an insulating film made of a heat-resistant polymer, and each of these conductor wiring layers is connected through an opening formed in the insulating film. A semiconductor board with wiring. (A step of forming a first insulating film made of a heat-resistant polymer on the sword substrate, and a step of forming a first conductive wiring layer in a predetermined pattern O on at least a portion of this tenth insulating film,
forming a second insulating film made of a heat-resistant polymer on the first conductor wiring layer; selectively forming an O opening in the second insulating film for connection between the conductors; and forming a 20th conductor wiring layer having a predetermined pattern, at least a portion of which is present on the second insulating film, including the opening. Method.
JP14061381A 1981-09-07 1981-09-07 Semiconductor mounting substrate having multilayer wiring and manufacture thereof Pending JPS5842255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14061381A JPS5842255A (en) 1981-09-07 1981-09-07 Semiconductor mounting substrate having multilayer wiring and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14061381A JPS5842255A (en) 1981-09-07 1981-09-07 Semiconductor mounting substrate having multilayer wiring and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5842255A true JPS5842255A (en) 1983-03-11

Family

ID=15272775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14061381A Pending JPS5842255A (en) 1981-09-07 1981-09-07 Semiconductor mounting substrate having multilayer wiring and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5842255A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS611028A (en) * 1984-05-18 1986-01-07 Fujitsu Ltd Manufacture of semiconductor device
JPS611027A (en) * 1984-05-18 1986-01-07 Fujitsu Ltd Manufacture of semiconductor device
JPH02503576A (en) * 1987-05-18 1990-10-25 イギリス国 Coated near-α titanium product
JPH02504289A (en) * 1987-05-18 1990-12-06 イギリス国 Coated near-α titanium product
JPH036359A (en) * 1989-06-02 1991-01-11 Sugitani Kinzoku Kogyo Kk Powdery metal thermal spraying material, its manufacture and its use
JPH0394052A (en) * 1989-09-05 1991-04-18 Sugitani Kinzoku Kogyo Kk Powdery metallic thermal spraying material, its production, and its use

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS611028A (en) * 1984-05-18 1986-01-07 Fujitsu Ltd Manufacture of semiconductor device
JPS611027A (en) * 1984-05-18 1986-01-07 Fujitsu Ltd Manufacture of semiconductor device
JPH037146B2 (en) * 1984-05-18 1991-01-31 Fujitsu Ltd
JPH037145B2 (en) * 1984-05-18 1991-01-31 Fujitsu Ltd
JPH02503576A (en) * 1987-05-18 1990-10-25 イギリス国 Coated near-α titanium product
JPH02504289A (en) * 1987-05-18 1990-12-06 イギリス国 Coated near-α titanium product
JPH036359A (en) * 1989-06-02 1991-01-11 Sugitani Kinzoku Kogyo Kk Powdery metal thermal spraying material, its manufacture and its use
JPH0517304B2 (en) * 1989-06-02 1993-03-08 Sugitani Kinzoku Kogyo Kk
JPH0394052A (en) * 1989-09-05 1991-04-18 Sugitani Kinzoku Kogyo Kk Powdery metallic thermal spraying material, its production, and its use
JPH0517305B2 (en) * 1989-09-05 1993-03-08 Sugitani Kinzoku Kogyo Kk

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