JPS5842087A - Display interpolator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interpolation circuit for displaying characters and graphics to be displayed when dot patterned characters and graphics are displayed on a display such as a CRT.

Conventionally, dot patterned characters and figures @1ft
When displayed on a display such as a cRT, so-called serrations occur in the characters and figures, making them look unnatural and difficult to see compared to the original pattern of the characters and figures.

Solutions to the above problems include increasing the resolution by increasing the frequency of the display lock, and blunting the edges of the rising and falling edges of the display signal. However, with these methods, considering the increase in memory capacity due to higher resolution and the adaptability of individual figures due to the blunting of edges, etc., they lead to circuit complexity and cost increases, and displays such as CRTs are not common in the information society. This cannot be said to be an appropriate method as the world continues to evolve.

Also, the 4 dots that are in phase with each other on the top, bottom, left and right in the dot pattern.
For example, when the positional relationship is as shown in Figure 2, interpolation is performed as shown in Figure 2, and when the positional relationship is as shown in Figure 3, interpolation is performed as shown in Figure 4. There is a way to do it. In this method, different interpolations are performed for the first field and the second field, respectively, and the area ratio as a whole is interpolated by V4 dots.

Although this method is visually superior, because of the interpolation method, one field is shifted by IH between the original display position that does not pass through the interpolation circuit and the display position that passes through the interpolation circuit. For this reason, if the coloring is performed in blocks, the luminance pattern signal and the coloring signal must be matched in position, and a circuit for IH delaying the coloring signal is required.

An interpolation method that provides substantially the same effect as the above-mentioned interpolation method, does not require a circuit for IH delaying the colored signal, and does not cause a vertical display position shift will be described below. Fifth
The figure shows the case where FIG. 1 is interpolated, and FIG. 6 is the case where FIG. 3 is interpolated.

The present invention relates to an apparatus for realizing the interpolation method as shown in FIG. 5 and FIG. 6.

The off-line diagram is an embodiment of the display device according to the present invention. In the OFF diagram, the display signal 12 is obtained by shifting the display signal 1 by one dot interval using the clock signal CKI in the shift register 1, and the display signal 13 is obtained by delaying the display signal 11 by one line in the line memory 2. The display signal 14 is shifted by one dot interval using the clock signal CK1 in the shift register 3.The signal indicating whether it is the 11 field or the fan 2 field is the field display signal FI, and the field display signal FI, display signal 11, display signal 12, Display signal 13, display signal 14, and clock signal CK 1
, the above six types of signals are used as address signals of the storage means 4, and the signal output from the storage means 4 is used as the display signal s1.
, display signal I2, and display signal S2 as shift register 5.
The clock signal CK2, which is synchronized with the clock signal CK1 and has twice the frequency, is shifted by one clock, that is, 0.
．． The display signal S3 is delayed by 5 dots, and the display signal 33 is
is delayed by one clock of the clock signal CK2 by the shift register 6 to produce a display signal S4, and the logical sum of the display signal 1 and the display signal 94 is determined by the OR circuit 7 and output as the display signal IO.

The algorithm shown in Figure-17 will be explained below.

FIG. 8 shows the display signal 11. Display signal 12, display signal 13,
The positional relationship on the pattern of the display signals 14 is shown. 9th
The figure shows the positional relationship shown in FIG. 8 on a display such as a CRT.

For each pattern of ll, 12.13 and 14 in Fig. 8, 1lal, 12al, 13al and 14
al is α field no each left half, 1larJ 12a
r, 13ar and 14ar are the right half of the a field, jlhi, 12hl, 13H and 114bl are the left half of the b field, ll1hr, 12hr
.

13 br and 64 hr, respectively, are the right half of the Fib field. - In the case of the pattern shown in Figure 5, Oal: 13ar
.

13b12.113br, 12ar', 111al
0 where l, l'2bl and 12br are 111. Also, in the case of a turn like the one shown in Fang 6, 14J, 14
ar.

14bl, 114br, 12ar, 11al,
1lhl and 11br become 111.

As shown in Fig. 10, only 12 and 13 out of the four dots are 11 'l and there is a donotha turn on the side of 12, unlike the case shown in Fig. 5, as shown in Fig. 11. It can be said that it is a more natural pattern if the 12al part is also set at 11°. Similarly, as shown in Figure 12, if only 11 and 14 of the four dots are 1'11 and there is a four-turn doraton on the right side of ll, unlike the case shown in Figure 6, the part 11ar is also 1'11. 11 would be a more natural) turn.

Whether or not 12αl is displayed in Fang 11 is determined by the 10th
It is determined not by the positional relationship of the four dots surrounded by the broken line in the figure, but by the relationship of the four dots one dot before. That is, the portion indicated as 12αl is output two clocks before the clock signal CK2, is shifted by the shift register 5-6, and then input to the OR circuit 7.

Further, 12ar is outputted from the storage means 4 and inputted to the sum/double circuit 7 without passing through the shift register 5.6.

Similarly, in Figure 13, whether or not 11ar is displayed is determined not by the positional relationship of the four dots surrounded by the broken line in Figure 12, but by the positional relationship of the four dots one dot apart. , l 1 al.

12ar is determined by the positional relationship of the four dots surrounded by broken lines.

As is clear from the above explanation, in the present invention,
11.12. Focusing on the display positional relationship of the four dots in 13 and 14, the signal that should be directly output from the storage means to the OR circuit and the signal that is shifted by 0.5 dot twice in the shift register and output to the OR circuit are calculated. By separating the power signal and using the logical sum of these two types of signals as an interpolation display signal, an excellent effect can be obtained in that an effective interpolation signal can be generated with a small number of circuits.

[Brief explanation of drawings]

1, 3, 8, 10, and 11 are diagrams showing displayed dot patterns, FIG. 2, FIG. 4, FIG. 5,
6, 9, 12, and 13 are diagrams showing dot patterns displayed on a display such as a CRT, and off-line diagrams are diagrams showing one embodiment of the present invention. 1, 3.5.5 ・・・Song・Shift register・・
2...Tune line memory, 4...Tune storage means, 7...4...OR circuit. Patent applicant: Matsushita Electric Industrial Co., Ltd.Figure 1Figure 3Figure 5Figure 2Figure 4Figure 6

Claims (1)

[Claims] One signal for any dot on any line, and three signals each delayed by one dot interval, one line interval, and one line and one line interval and one dot interval, respectively.
A display that transmits a signal containing an interpolated signal by having means for creating four types of signals, and having a means for providing an interpolated signal to either the first field or the second field. In the interpolation device for use, six types of signals consisting of the four types of signals, the first and second field switching signals, and the clock signal are used, and means is provided for storing in advance the contents of a truth table of the six types of signals. , by using the six types of signals as address signals of the storage means and combining at least two types of output signals of the storage means, an image containing an interpolation signal in either the first field or the second field is created. A display interpolation device characterized in that it creates a signal.