JPS5841599B2 - Matrix circuit using MIS field effect transistors - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a plurality of nXm unit circuits M182M1□...
・Mlm;M212M22...M2m:...;Mn
12Mo2...Mnm, in this case the unit circuit M
ij (however, i=1.2・n; j=1.2”・m
) is a series circuit consisting of a current control circuit composed of MIS field effect transistors and a current responsive circuit through which the required current is supplied, while unit circuits M10, M21...M , 1; Ml, , M21...
Mn2:...:M1rn1M2rr1...Mnf
One end of the series circuit of f1 is connected to the first common column line Al:
A2;...:Am is connected to the second common column line B1:B2:...Bm at the other end, and the first and second common column lines A and B are selected. unit circuit Mi1
, Mi2...Mim, the MIS field effect transistors of the current control circuits are controlled, so that the unit circuit M...
M designed to supply the required current to the current responsive circuit of
This invention relates to improvements in matrix circuits using IS field effect transistors.

A matrix circuit using this kind of MIS field effect transistor has a current-responsive circuit of its unit circuit Mij made of polycrystalline silicon, which has a property of irreversibly changing from a high resistance state to a low resistance state when energized. A fuse that has the property of irreversibly changing from a non-fused state to a fused state when energized; a fuse that has the property of irreversibly changing from a non-shorted state to a shorted state by destroying the internal junction when energized By using a diode or the like having , it becomes a read-only memory circuit in which the unit circuit Mij becomes a read-only memory element.A conventional matrix circuit using this type of MIS field effect transistor is shown in FIG. As in, a plurality of nXm unit circuits M1□, M1□...
Mlm;M27, M2□...M2m;...;M
M...M, in this case unit circuit Mij(
However, i = 1.2-n; j = 1.2"m) is a current control circuit composed of one MIS field effect transistor as shown in Fig. 2, and the required current is supplied through this. It preferably consists of a series circuit F with an MTS field effect transistor Q and a current responsive circuit H connected in series, and thus unit circuits M11, M21.''Mn1: M12
, M22...Mn2;...;M1m1M2m...
One end of the series circuit F of Mnm, that is, the side opposite to the current responsive circuit H side of the current control circuit, respectively, is connected to the first common column line A.
I: A2:...Am, the other end, that is, the side opposite to the current control circuit side of the current responsive circuit H, is connected to the second common column line B, :B2;...;Bm, respectively, and the unit Circuit Mi
1, Mi2, . . . Mim, the gates of the field effect transistors Q in the power supply circuit are connected to the common row line Wi.

However, according to such a matrix circuit using conventional MIS field effect transistors, the first and second common column lines A
Select ・and B・ and connect the required power supply between them (not shown)
By connecting , selecting the common row line Wi and applying a required control voltage to it, it becomes a MIS field-effect transistor in the current control circuit of the unit circuit M, and controls the required current in the current responsive circuit H. flows, so that the current-responsive circuit H is in a low resistance state if it is the above-mentioned resistance element, in a blown state if it is the above-mentioned fuse, and in a short-circuited state if it is the above-mentioned diode, Information has been written to the unit circuit Mij, and therefore the unit circuit Mij becomes a read-only memory circuit that makes the unit circuit Mij a read-only memory element.In this case, the MIS electric field effect of the current circuit of the unit circuit Mij Generally speaking, as shown in FIG. 3, for example, two semiconductors as a source or drain having a conductivity type opposite to that of the semiconductor substrate 1, that is, an N type, are placed in a P-type semiconductor substrate 1 from its main surface 2 side. Regions 3 and 4 are formed to form a channel region 5 between them, and an electrode T as a gate is arranged on the channel region 5 with an insulating layer 6 interposed therebetween; The electrode 7 as the MIS field effect transistor date of the unit circuits Mi1, Mi2...Mim is generally the third
As shown in the figure, the conductive layers 8 are connected in series so as to become part of a linearly extending conductive layer 8 as a common row line Wi.

For this reason, when the resistance R1 of the conductive layer 8 as all the common row lines Wi is assumed to be the associated capacitance, the common row line Wi is RC
/2, and therefore, by selecting the common row line Wi and applying the required control voltage to it, it becomes the MIS field-effect transistor in the current control circuit of the unit circuit Mij. When the operation is delayed, especially when the current value required for the current responsive circuit H is large, the width T of the MIS field effect transistor channel region 5 is increased accordingly. As a result, the length of the conductive layer 8 as the common row line Wi increases, and the resistance R and capacitance C increase accordingly, which cannot be ignored.

Therefore, although the present invention is based on the above-mentioned conventional matrix circuit using MIS field effect transistors, it is possible to reduce the above-mentioned operation delay, and furthermore, the entire structure can be monolithically formed on a semiconductor substrate in a small and compact manner. This will become clear from the detailed description below.

FIG. 4 shows an example of a matrix circuit using MIS field effect transistors according to the present invention. Corresponding parts to those in FIG. In the above-mentioned configuration, the current control circuit of the unit circuit M... is replaced by one MIS field effect transistor, but instead of using the same channel type first and second transistors connected in parallel as shown in FIG. The MIS field effect transistors Q1 and Q2 are configured to include the MIS field effect transistors Q1 and Q2, and the MI of the current control circuit of the unit circuits Mi□, Mi2, . . .
The first and second common row lines W1 and 1Q2 are respectively supplied with the same control signal.
It has the same configuration as the case of FIG. 1 except that it is connected to W21 and W21.

The above is an example of the configuration of a matrix circuit using MIS field effect transistors according to the present invention. According to this configuration, the first and second common column lines A and Bj are selected and the necessary By connecting a power source (not shown), selecting the first and second common row lines W1i and W2i, and simultaneously applying a required control voltage to them, the current control circuit of the unit circuit Mij can be controlled. MIS field effect transistor and 1Q
2 are both turned on, the required current can flow through the current-responsive circuit H, and therefore information is written to the unit circuit Mij as in the case of the conventional multiplex circuit shown in FIG. In this case, the current control circuit of the unit circuit Mij is connected to two M
The MIS field effect transistors Q1 and Q2 are generally configured with their main components in, for example, a P-type semiconductor substrate 11 as shown in FIG. Semiconductor substrate 11 from surface 12 side
3 as a source or drain of the opposite conductivity type, that is, N type.
The semiconductor regions 13, 14 and 15 are the semiconductor regions 13, 14 and 15.
and 14, and between 14 and 15 to form channel regions 16 and 17, respectively, and two electrodes 20 and 21 as gates are formed on channel regions 16 and 1T via insulating layers 18 and 19, respectively. It is assumed that the MIS field effect transistor Q2 has a structure including one conductor region 13 and 14, a channel region 16, an insulating layer 18, and an electrode 20, and the MIS field effect transistor Q2 is a semiconductor. The unit circuits Mi1, Mi
2-...Mim's MIS field effect transistor and 1
In general, the electrodes 20 as the gates may be connected in series to form part of a linearly extending conductive layer 22 as a common row line W11, as shown in FIG. , Mi2, . It is something.

Therefore, if the current responsive circuit H of the unit circuit Mij is supplied with the same current value as in the case of Fig. 1, the unit circuit M
The width T' of the MIS field effect transistor ij and the channel regions 16 and 17 of 1Q2 is defined as the unit circuit M in FIG.
By setting the width T of the MIS field effect transistor channel 5 to 1/2 of the width T of the MIS field effect transistor channel 5, the conductivity as the common row lines W1 and W2i can be set as follows. When the capacitance associated with the common row line Wi is C', the resistance R' and the capacitance C' can be close to 1/2 of the resistance R and capacitance C of the common row line Wi in the case of FIG. 1/ of the time constant RC/2 of the common row line Wi when the time constant approximated by R'C7/2 of the row lines W1i and W2i is as shown in FIG.
This value can be close to 4.

Therefore, by selecting the common row lines W1 and W2i and applying a required control voltage to them, the MIS field effect transistor and 1Q2 of the current control circuit of the unit circuit Mij are controlled.
Even if there is a delay in the operation when Mij is turned on, the delay is 1/4 of the delay in the operation of the MIS field effect transistor in the current control circuit of the unit circuit Mij in the case of Fig. 1. It could be something close.

Therefore, according to the configuration of the matrix circuit according to the present invention described above, the current responsive circuit H can be made to respond with a higher response speed than the conventional matrix circuit described above in FIG. It is.

Also, the two (7) MIS of the current control circuit of the unit circuit Mij
As shown in FIG. 6, the source or drain of the MIS field effect transistor Q2 and the source or drain of the MIS field effect transistor Q2 are configured by a common region 14. channels 16 and 17 of the current control circuit.
The width T of the two MIS field effect transistors and channels 16 and 17 of 1Q2 is smaller than the similar length in the case shown in FIG.
' can be made 1/2 of the width T of the MIS field effect transistor channel 5 in the case of FIG. 1, so the area occupied by the current control circuit on the semiconductor substrate can be gradually reduced to 3/4 of that in the case of FIG. Therefore, it has great features such as being able to be constructed as a whole on a semiconductor substrate in a so-called monolithic manner in a much smaller and more compact manner than in the case of FIG.

In addition, two MISs for the current control circuit of the unit circuit Mij
Since the field effect transistors and 1Q2 have the same channel type, their current control circuit can be constructed easily and compactly, and the control signals applied to the common row lines W1 and W2i can be the same. It also has

[Brief explanation of the drawing]

Fig. 1 is a systematic connection diagram showing a matrix circuit using conventional MIS field effect transistors, Fig. 2 is a connection diagram showing its unit circuit, and Fig. 3 A and B are diagrams showing the unit circuit shown in Fig. 2. FIG. 4 is a systematic connection diagram showing an example of a matrix circuit using MIS field effect transistors according to the present invention, and FIG. A connection diagram showing an example of the unit circuit, and FIGS. 6A and 6B are a line plan view and a sectional view thereof showing the general configuration of two MIS field effect transistors in the unit circuit shown in FIG. . In the figure, Mij (where i=1, 2・”n; j=1
, 2...m) it unit circuit, A. and B. are common column lines, WilWll and W2i are common row lines, F is a series circuit, D is a current control circuit, H is a current responsive circuit, Q, Ql and Q2 each represents a field effect transistor.

Claims (1)

[Claims] 1. A plurality of n x m unit circuits M18. M12・M
lm :M212M22...M2m;...;Mn1
Mn2...Mnm is provided, and the above unit circuit M... (however, i=1.2...n:j=1
．． 2...m) is a series circuit consisting of a current control circuit configured with MIS field effect transistors and a current responsive circuit through which the required current is supplied, and the unit circuit M119M21 is ...Mn1; M122M
22...Mn2:M1m2M2m...Mnm One end of the series circuit is connected to the first common column line A1:A2...A, respectively.
□, the other end is the husband and husband second common column line B1:B2...;B
m, and the first and second common column lines Aj and B
j is selected, and the unit circuit MittMi2...
In a matrix circuit using MIS field effect transistors, the MIS field effect transistor of the current control circuit of Mim is controlled to supply a required current to the current responsive circuit of the unit circuit Mij. The current control circuit of the unit circuit M... is configured to include first and second MIS field effect transistors of the same channel type connected in parallel, and the unit circuit Mi19
Mi2...The first and second M of the Mim current control circuit
The gates of the IS field effect transistors are connected to first and second common row lines W1 and W to which the same control signal is applied, respectively.
2. connected to the unit circuit Mi12Mi2...M
The first and second MIS field effect transistors of the current control circuit of im are simultaneously controlled by the same control signal applied to the first and second common row lines W1 and W2°, so that the unit circuit M An MIS characterized in that the required current is supplied to the current responsive circuit of...
Matrix circuit using field effect transistors.