JPS5840928A - Current converting josephson circuit - Google Patents
Current converting josephson circuitInfo
- Publication number
- JPS5840928A JPS5840928A JP56138574A JP13857481A JPS5840928A JP S5840928 A JPS5840928 A JP S5840928A JP 56138574 A JP56138574 A JP 56138574A JP 13857481 A JP13857481 A JP 13857481A JP S5840928 A JPS5840928 A JP S5840928A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- current
- positive
- input signal
- flows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
- H03K19/1954—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は正、負の方向を有する信号電流を、０゜１の信
号電流、即ち信号の有無、に変換するのに好適なジョセ
フソン素子を用いた回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit using a Josephson element suitable for converting a signal current having positive and negative directions into a signal current of 0°1, that is, the presence or absence of a signal.
ジョセフソン素子を用い、直流電源駆動の論理回路のひ
とつであるバッフル回路（Ａ、 Ｆ、Ｈｅｂｅｒｄ ；
ＩＥＥｇ、Ｔｒａｎ、Ｍａｇ、ＭＡＧ−１５，４０８（
１９７９））は第１図のごとく、ゲート電流源１０１（
ト）、１０２０＃ ジョセフソンゲート（単一接合ある
いは５Ｑ−ＵＩＤから成る）１０３，１０４、抵抗１０
５゜ｉ０６およびインダクタンス（出力線）１０９から
構成される。A baffle circuit (A, F, Heberd;
IEEEg, Tran, Mag, MAG-15,408 (
1979)), the gate current source 101 (
), 1020# Josephson gate (single junction or 5Q-UID) 103, 104, resistor 10
5° i06 and an inductance (output line) 109.
入力信号線１０７．１０８に相補（１０７が１の時１０
８は０．１０７がＯの時ｉｏｓは１）の入力信号電流を
入力する場合を考える。入力信号線１０７が１．１０８
が００時にはゲート１０３は電圧状態、１０４は零電圧
状態でおバグート′ｔ＊Ｉｔは抵抗１０５、インダクタ
ンス１０９、ゲート１０４を通って流れる。逆に１０７
が０．１０８が１の場合には、ゲート１０３が零電圧状
態、１０４が電圧状態にスイッチし、ゲート電流１１は
ゲートｉｏａ、インダクタンス１０９、抵抗１０６を通
って流れる。Complementary to input signal lines 107 and 108 (10 when 107 is 1)
Consider the case where 8 is 0.107 is O and ios is 1) input signal current. Input signal line 107 is 1.108
When is 00, the gate 103 is in a voltage state, 104 is in a zero voltage state, and the voltage 't*It flows through the resistor 105, the inductance 109, and the gate 104. On the contrary, 107
is 0.108 is 1, the gate 103 is switched to the zero voltage state, the gate 104 is switched to the voltage state, and the gate current 11 flows through the gate IOA, the inductance 109, and the resistor 106.
したがって、インダクタンス１′０９を流れる・−流、
すなわち出力信号（ｆｉは入力信号線１０７が１の場合
には矢印１１Ｇ、１０８が１の時には矢印１１１の方向
に流れることにな夛、このノーツフル回路で論理回路を
構成した場合にその信号電流は正、負で常に電流が流れ
ている。しかしながら、論理回路を構成する場合、０．
１の電流出力（例えばＯの時電流が零で、１の時一定の
一流値を示す出力）の方が置い易いことから、ノ・ツフ
ル回路の如くに正、負の信号を０．１の信号に変換する
ことが望まれる。Therefore, the current flowing through the inductance 1'09,
In other words, the output signal (fi flows in the direction of the arrow 11G when the input signal line 107 is 1, and in the direction of the arrow 111 when the input signal line 108 is 1. When a logic circuit is configured with this Noteful circuit, the signal current is Positive and negative currents always flow.However, when configuring a logic circuit, 0.
Since it is easier to set up a current output of 1 (for example, when the current is O, the current is zero, and when it is 1, the current shows a constant value), it is easier to set up a current output of 0.1. It is desirable to convert it into a signal.
本発明の目的は、正、負の信号電流を０．１に変換する
直流電源駆動ジョセ７ノン回路を提供することにある。An object of the present invention is to provide a DC power supply driven Jose7non circuit that converts positive and negative signal currents into 0.1.
以下、実施例で本発明を説明する。第２図に本発明の回
路構成を示す。電流注入形インターフェロメータ２０１
，２０２にそれぞれ抵抗２０３゜２０４を通して入力信
号が入力できるように給線し、さらにゲート成流工、は
インダクタンス２０５゜２０６を通して２０１．２０２
に供給される。第３図に電流注入形インターフェロメー
タ２０１゜２０２のしきい値特性を示す。このとき、原
点をふくむ２つの曲線に囲まれた領域では、零電圧状態
をとり、この領域外では電圧状態をとる。The present invention will be explained below with reference to Examples. FIG. 2 shows the circuit configuration of the present invention. Current injection interferometer 201
, 202 through resistors 203 and 204, respectively, so that input signals can be input, and the gate currents are connected through inductances 205 and 206 to 201 and 202.
is supplied to FIG. 3 shows the threshold characteristics of the current injection interferometers 201 and 202. At this time, a zero voltage state is assumed in a region surrounded by two curves including the origin, and a voltage state is obtained outside this region.
第２、第３図を用いて本発明の詳細な説明する。The present invention will be explained in detail using FIGS. 2 and 3.
入力信号がＯの場合、ゲート電１５！Ｉｇはインダクタ
ンス２０５，２０６を通シ等分に分流し、シ流注入形イ
ンターフエロメー゛夕２０１，２０２に流れ込む（動作
点は第３図の１，２）。この状態で正の入力１８号が供
給（１１０）されると、ゲート２０１は電圧状態（第３
図３）にスイッチし、２０２は零電圧状態（４）のまま
でおる。そうすると、ゲートに流Ｉｆ、入力電流Ｉ’ｍ
とも大部分ゲート２０２に流れるが、その状態において
も２０２は零電圧状態にある（第３図の５）。When the input signal is O, the gate voltage 15! Ig is equally divided through inductances 205 and 206 and flows into two-flow injection type interferometers 201 and 202 (operating points are 1 and 2 in FIG. 3). When positive input No. 18 is supplied (110) in this state, the gate 201 is in the voltage state (3rd
3), and 202 remains in the zero voltage state (4). Then, the current If in the gate and the input current I'm
Most of both flows to the gate 202, but even in that state, 202 is in a zero voltage state (5 in FIG. 3).
同様にして、入力信号端子が負（１１１）になった場合
にはゲートｆｌｌ流工、はゲート２０１側だけに流れる
。Similarly, when the input signal terminal becomes negative (111), the gate signal flows only to the gate 201 side.
したがって、入力１言号鑞流が正、負で与えられるとゲ
ート電流Ｉ、は２０１あるいは２０２側だけに流れ、イ
ンダクタンス２０５．２０６を出力線とするとその出力
電流は０か１になることが分る。Therefore, it can be seen that if the input word current is positive or negative, the gate current I flows only to the 201 or 202 side, and if the inductance 205 or 206 is used as an output line, the output current will be 0 or 1. Ru.
また、本発明の回路は第２図の入力信号端子２０７に複
数の入力信号線を接続すると、その入力信号の＋、−の
多いほうによって上述の動作が行なわれる。すなわちｍ
ａｊｏｒ口ｙ論理回路とじて用いることができる。Further, in the circuit of the present invention, when a plurality of input signal lines are connected to the input signal terminal 207 of FIG. 2, the above-described operation is performed depending on which of the input signals has more positive or negative signals. That is, m
It can be used as an ajor logic circuit.
なお、直列接続した電流注入形インター７エロメータに
公知の”ダンピング抵抗を挿入することは任意である。Note that it is optional to insert a known "damping resistor" into the series-connected current injection type inter-7 erometers.
本発明によれば、正、負の信号電流を０，１の信号電流
に変換でき、新しい機能をもつ回路を提供でき、その効
果は大きい。According to the present invention, positive and negative signal currents can be converted into 0 and 1 signal currents, and a circuit with new functions can be provided, which is highly effective.
第１図は従来例を示す図、第２図は本発明の実施例を示
す図、第３図は本発明に用いた電流注入形インターフェ
ロメータのしきい値特性を示す図である。
２０１．２０２・・・逸流注入形インター７エロメータ
、２０５．２０６・・・出力線（インダクタンス）。
代理人 弁理士 薄田利幸
第 １ 図FIG. 1 is a diagram showing a conventional example, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing threshold characteristics of a current injection type interferometer used in the present invention. 201.202... Escape injection type Inter 7 elometer, 205.206... Output line (inductance). Agent Patent Attorney Toshiyuki Usuda Figure 1
Claims (1)
ェロメータを直列に接続し、その中間点を接地し、かつ
直列接続体の他端にゲート−流を供給するための２つの
配線を設けてこの配線を出力端とし、上記２個の電流注
入形インター７エロメータに正負の入力信号゛電流を印
加することを特徴とする電流変換ジョセフソン回路。Two current injection interferometers using Josephson elements are connected in series, their midpoint is grounded, and two wirings are provided at the other end of the series connection for supplying gate current. A current conversion Josephson circuit characterized in that this wiring is used as an output end and positive and negative input signals (currents) are applied to the two current injection type inter-electrometers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138574A JPS5840928A (en) | 1981-09-04 | 1981-09-04 | Current converting josephson circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138574A JPS5840928A (en) | 1981-09-04 | 1981-09-04 | Current converting josephson circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5840928A true JPS5840928A (en) | 1983-03-10 |
Family
ID=15225308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56138574A Pending JPS5840928A (en) | 1981-09-04 | 1981-09-04 | Current converting josephson circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840928A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0505250A2 (en) * | 1991-03-19 | 1992-09-23 | Fujitsu Limited | Superconducting circuit having a rectifier for converting a bipolar signal to a unipolar signal |
-
1981
- 1981-09-04 JP JP56138574A patent/JPS5840928A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0505250A2 (en) * | 1991-03-19 | 1992-09-23 | Fujitsu Limited | Superconducting circuit having a rectifier for converting a bipolar signal to a unipolar signal |
| US5287057A (en) * | 1991-03-19 | 1994-02-15 | Fujitsu Limited | Superconducting circuit having a rectifier for converting a bipolar signal to a unipolar signal |
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