JPS5840879A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS5840879A
JPS5840879A JP56138327A JP13832781A JPS5840879A JP S5840879 A JPS5840879 A JP S5840879A JP 56138327 A JP56138327 A JP 56138327A JP 13832781 A JP13832781 A JP 13832781A JP S5840879 A JPS5840879 A JP S5840879A
Authority
JP
Japan
Prior art keywords
layer
electrode
auin2
emitting device
ingaasp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56138327A
Other languages
Japanese (ja)
Inventor
Ganzo Iwane
岩根　眼「あ」
Mitsuo Fukuda
光男 福田
Kenichiro Takahei
高幣　謙一郎
Sadao Adachi
定雄 安達
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56138327A priority Critical patent/JPS5840879A/en
Publication of JPS5840879A publication Critical patent/JPS5840879A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04252—Electrodes, e.g. characterised by the structure characterised by the material

Abstract

PURPOSE:To obstruct the intrusion of Au into a semiconductor, and to prevent the degradation of a light-emitting device by positioning AuIn2 between welding solder to a heat sink and an ohmic electrode. CONSTITUTION:The ohmic electrode 7 of the light-emitting device is formed, a constant-ratio intermetallic compound AuIn2 13 (53.8wt% In, 544 deg.C melting point) is attached through a sputtering method, and an Au plated layer 8 is stacked. Accordingly, the excessive section of the Au 8 or the welding solder In does not pass through the AuIn2 layer 13 at 300 deg.C or lower, the Au-Zn electrode 7 and an InGaAsP electrode forming layer 5 are not affected adversely, and a defect is not induced in InGaAsP 3, and the degradation of radiant power output is prevented.

Description

【発明の詳細な説明】 本発明は■−Ｖ族半導体発光素子の電極構成に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode structure of a ■-V group semiconductor light emitting device.

第１図は従来の半導体発光素子のヒートシンクへの組立
構成の一例である。半導体発光素子としてＩｄ　ＩｎＧ
ａＡｓＰ　／　ＩｎＰダブルへテロ接合半導体レーザと
する。基板ｎ−ＩｎＰｌ上に活性層Ｉｎ　Ｇａ　Ａｓ　
Ｐ３の上下に電気的中光学的閉じ込めＩＮ　ｎ　−Ｉｎ
Ｐ　２゜ｐ−ＩｎＰ４がある。４の上に電極形成層ｐ−
Ｉｎ　Ｇａ　Ａｓ　Ｐｂがある。６はｎ側電極Ａｕ　−
Ｓｎ（もしくはＡｕ　−Ｇｅ　−Ｎｉ　）、７はｐ側電
極Ａｕ　−Ｚｌｌ　（もしくＱま（Ａｕ　）ｐｔ　−Ｔ
ｉ　）で、８は土敷き鍍金層Ａｕである。一方９はヒー
トシンクのダイヤモンド（もしくは５ｊ）１１０はメタ
ライズ層Ａｕ　−Ｃｒ　（もしくはＡｕ−ＰＬ−Ｔｉ）
で、１１は融后半出金属Ｉｎ（もしくはＰｂ　−Ｓｎ　
）　　である。１２はリードワイヤＡｔ（もしくはＡｕ
　）であるＯ 以上のような構成でなる発光素子において従来上敷きＱ
ＩＶｌ金層Ａｕ　ｇの一部のＡｕもしくは融層半田剤Ｉ
ｎ　（もしくはＰｂ　−Ｓｎ　）　１１が電極層７の凹
凸や不均一、あるいは構成成分の不定比性や不安定性に
より、電極形成層ＩｎＧａＡｓＰ　５内部に侵入し、半
導体１ｎＧａＡｓＰ　５に欠陥を誘起することがあった
。FIG. 1 is an example of an assembly structure of a conventional semiconductor light emitting device onto a heat sink. IdInG as a semiconductor light emitting device
An aAsP/InP double heterojunction semiconductor laser is used. Active layer InGaAs on substrate n-InPl
Electrical and optical confinement IN n -In above and below P3
There is P2゜p-InP4. 4, an electrode forming layer p-
There is InGaAsPb. 6 is the n-side electrode Au −
Sn (or Au-Ge-Ni), 7 is the p-side electrode Au-Zll (or Qma(Au)pt-T
i), 8 is the soil plating layer Au. On the other hand, 9 is a heat sink diamond (or 5j) 110 is a metallized layer Au-Cr (or Au-PL-Ti)
11 is the molten metal In (or Pb-Sn
). 12 is a lead wire At (or Au
) is O. In the light emitting device having the above configuration, the conventional overlay Q
IVl Some Au of gold layer Au g or melting layer solder agent I
n (or Pb-Sn) 11 may invade into the electrode forming layer InGaAsP 5 due to unevenness or non-uniformity of the electrode layer 7 or non-stoichiometry or instability of the constituent components and induce defects in the semiconductor 1nGaAsP 5. there were.

その結果として欠陥が閉じ込め層ＩｎＰ４、さらには活
性層Ｉ　ｎ　Ｇａ　Ａｓ　Ｐ　３へも影響を及はし、発
光素子の出力劣化をきたすという欠点があった。As a result, the defects have an effect on the confinement layer InP4 and further on the active layer InGaAsP3, resulting in deterioration of the output of the light emitting device.

本発明はヒーＩ・シンクへの融着半田剤とオーミック電
極間にＡｕＩｎ、を挿入具備することを特徴とし、その
１」的は発光素子半導体内部へ、′電極構成金属油の侵
入による発光素子の劣化を防止することに４りる。The present invention is characterized in that AuIn is inserted between the soldering agent for heat I/sink and the ohmic electrode. There are four ways to prevent deterioration.

第２ＭＱｊ本発明の実施例であって、第１図と＋１１を
成り、ｌ；Ｉは同様であるか、第１図と異なるのは、電
極金用層７と土敷き鍍金層８の間に、　　ＡｕＩｎ２定
比金属間化合物層１３を挿入したことである。なお電比
金属間化合物ＡｕＩｎ１１３は融点５４４℃（５３，８
０重量％Ｉｎ　）である。従って半導体発光素子への形
成に際しては、オーミック電極７形成後、スパッタリン
グ等で当該電比金属間化合物Ａｕ　Ｉｎ、　ｌ（を伺着
し、しかる後上敷き鍍金層Ａｕ８の形１１！、が一力法
として挙げられる。2nd MQj This is an embodiment of the present invention, and consists of +11 with FIG. 1, and l;I is the same or different from FIG. , an AuIn2 stoichiometric intermetallic compound layer 13 was inserted. The electrical intermetallic compound AuIn113 has a melting point of 544°C (53.8°C).
0 wt% In). Therefore, when forming a semiconductor light emitting device, after forming the ohmic electrode 7, the electrometric intermetallic compound AuIn, 1 is deposited by sputtering or the like, and then an overlay plating layer Au8 is formed in the form 11!, using the single-iron method. It is mentioned as.

このような構成に々つているから、少くとも３００℃以
下では上敷き層Ａ１１８もしくｄ融滑半ＩＬＩｊＷＩｎ
　（もしくはＰｂ　−Ｓｎ　）の余剰が、安定な電比金
属間化合物Ａｕ　Ｉｎ、を通過すること力く、電極層Ａ
ｕ−Ｚｎ７．電極形成層ＩｎＧａＡｓＰ５Ｎ二悪影４１
ヲ及はさない。従ってその効果として活性Ｍ　］　ｎ　
Ｇａ　Ａｓ　Ｐ３に欠陥ヲ訪起しないことである。Since it is based on such a structure, at least below 300°C, the overlay layer A118 or d melting layer ILIjWIn
(or Pb-Sn) passes through the stable electric ratio intermetallic compound AuIn.
u-Zn7. Electrode formation layer InGaAsP5N two bad shadows 41
I won't affect it. Therefore, the effect is active M ] n
It is important that no defects occur in GaAs P3.

以上説明したように、電比金楠間化自物Ａｕ１ｎｔの電
極層間への挿入により、発光素子の劣化ｅ　ＩＮＥ減す
る利点がある。As explained above, the insertion of the electrically conductive Au1nt between the electrode layers has the advantage of reducing the deterioration e INE of the light emitting element.

なお以上の説明はＩｎ　Ｇａ　Ａ８Ｐ／ＩＩＩ　Ｐ半導
体レーザを例にしたが、本発明は半導体レーザにとど盪
らずＩｎＰ’ｅ主体とする半導体素子全般に適用できる
。Although the above description has been made using an InGa A8P/IIIP semiconductor laser as an example, the present invention is applicable not only to semiconductor lasers but also to all semiconductor devices mainly made of InP'e.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の発光素子の構成断面図、第２図は本発明
の発光素子の構成断面図である。 ■・・・・・基板、２・・・・・・閉じ込め層、３・・
・・・・活性層、４・・・・・・閉じ込め層、５・・・
・・・電極形成層、６・・・・・・ｌｌ側ｔａｉ１．極
、７・・・・・・ｐ側’ｒｅｉ極、８・・・・・・上敷
き鍍金層、９・・・・・・ヒートシンク、１０・・・・
・・メタライズ層、１１・・・・・・融腐半１１１＠属
層、ＩＺ・・・・・・リードワイヤ、１３・・・・・・
金属間化合物層 特許出願人　日本電信電話公社 一〇　〇FIG. 1 is a sectional view of the structure of a conventional light emitting element, and FIG. 2 is a sectional view of the structure of the light emitting element of the present invention. ■... Substrate, 2... Confinement layer, 3...
...Active layer, 4...Confinement layer, 5...
. . . Electrode forming layer, 6 . . .ll side tai1. Pole, 7...P side'rei pole, 8...Overlay plating layer, 9...Heat sink, 10...
...Metallized layer, 11...Metalized half layer 111@metalized layer, IZ...Lead wire, 13...
Intermetallic compound layer patent applicant Nippon Telegraph and Telephone Public Corporation 10 〇

Claims (1)

【特許請求の範囲】[Claims] ヒートシンクへの融着半田剤とオーミック電極間にＡｕ
Ｉｎ１層を介在せしめるＩｎＰ系半導体素子。Au between the fusion solder to the heat sink and the ohmic electrode
An InP-based semiconductor device with an In1 layer interposed therebetween.
JP56138327A 1981-09-04 1981-09-04 Semiconductor element Pending JPS5840879A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56138327A JPS5840879A (en) 1981-09-04 1981-09-04 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56138327A JPS5840879A (en) 1981-09-04 1981-09-04 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS5840879A true JPS5840879A (en) 1983-03-09

Family

ID=15219304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56138327A Pending JPS5840879A (en) 1981-09-04 1981-09-04 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS5840879A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS573103U (en) * 1980-06-05 1982-01-08
EP1433564A1 (en) * 2002-12-24 2004-06-30 Agilent Technologies Inc System and method for hermetic seal formation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS573103U (en) * 1980-06-05 1982-01-08
JPH0232882Y2 (en) * 1980-06-05 1990-09-05
EP1433564A1 (en) * 2002-12-24 2004-06-30 Agilent Technologies Inc System and method for hermetic seal formation

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