JPH01138777A - Submount for optical semiconductor element - Google Patents
Submount for optical semiconductor elementInfo
- Publication number
- JPH01138777A JPH01138777A JP62298114A JP29811487A JPH01138777A JP H01138777 A JPH01138777 A JP H01138777A JP 62298114 A JP62298114 A JP 62298114A JP 29811487 A JP29811487 A JP 29811487A JP H01138777 A JPH01138777 A JP H01138777A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- submount
- solder layer
- optical semiconductor
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 230000003287 optical effect Effects 0.000 title claims description 19
- 229910000679 solder Inorganic materials 0.000 claims abstract description 49
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 20
- 239000000956 alloy Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 230000017525 heat dissipation Effects 0.000 claims description 11
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052745 lead Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 238000007747 plating Methods 0.000 abstract description 4
- 229910015363 Au—Sn Inorganic materials 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000009751 slip forming Methods 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 11
- 230000007547 defect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、光半導体素子のチップの実装に使用する光
半導体素子用サブマウントに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a submount for an optical semiconductor element used for mounting a chip of an optical semiconductor element.
第３図は従来の光半導体素子用サブマウントの断面図を
示し、第４図はＬＤチップを光半導体素子用サブマウン
トを介して、放熱用金属ブロックにダイボンドした際の
状態を示す図である。Fig. 3 shows a cross-sectional view of a conventional submount for optical semiconductor elements, and Fig. 4 shows a state in which an LD chip is die-bonded to a metal block for heat dissipation via the submount for optical semiconductor elements. .
これらの図において、１は半導体レーザチップ（通称Ｌ
Ｄチップという）、２は５ｉ（７）電気伝導性材料から
なるサブマウント基体、３は前記サブマウント基体２の
両面にメタライズされたバリヤ層で、第１層Ｔｉ層３１
．第２層Ｎｉ層３３．および第３層Ａｕ層３４かうなっ
ている。４は前記バリヤ層３上に形成されたＳｎ半田層
で、このＳｎ半田層４とＬＤチップ１および放熱用金属
ブロック５が接着されている。６．７は前記ＬＤチップ
１の裏面電極および表面電極、８は前記ＬＤチップ１の
表面電極７上に熱圧着された金ワイヤである。In these figures, 1 is a semiconductor laser chip (commonly known as L
D chip), 2 is a submount base made of 5i (7) electrically conductive material, 3 is a barrier layer metalized on both sides of the submount base 2, and a first Ti layer 31
．． Second layer Ni layer 33. and the third Au layer 34. 4 is a Sn solder layer formed on the barrier layer 3, and the LD chip 1 and the heat dissipating metal block 5 are bonded to this Sn solder layer 4. Reference numerals 6 and 7 are the back and front electrodes of the LD chip 1, and 8 is a gold wire thermocompressed onto the front electrode 7 of the LD chip 1.
上記のような従来例にあっては、ＬＤチップ１は図示は
していないが、ＧａＡｓ基板上に液相成長法によりＧａ
Ａｓ、Ｇａ、−ＸＡｎ、Ａｓの各層が順次積層され、ダ
ブルへテロ接合を形成している。また、内部ストライブ
構造により電流注入によるキャリアの閉じ込めが効率よ
く行われ、その結果、電子とホールの再結合により光が
発生する。発生した光は共振器端面での反射を繰り返し
、導波路内で増幅していき、結晶内部の吸収損失と同じ
になった所でレーザ発振を開始する。レーザ光は共振器
端面の微小な領域より放射されるため、結晶内部ではか
なりの発熱が起こる。発振後のレーザ特性を安定に得る
ためには、放熱が必須である。以下、第４図に基づき、
ＬＤチップ１が放熱用金属ブロック５の上にダイボンド
される過程を説明する。放熱用金属ブロック５の上にサ
ブマウント基体２がマウントされる。サブマウント基体
２の両面には、スパッタ法によりサブマウント基体２側
より順次第１層Ｔｉ層３１．第２層Ｎｉ層３３．第３層
Ａｕ層３４が積層されたバリヤ層３が形成されている。In the conventional example described above, although the LD chip 1 is not shown, Ga is grown on a GaAs substrate by liquid phase growth.
Each layer of As, Ga, -XAn, and As is sequentially laminated to form a double heterojunction. In addition, the internal stripe structure efficiently confines carriers by current injection, and as a result, light is generated by recombination of electrons and holes. The generated light is repeatedly reflected at the resonator end face and amplified within the waveguide, and laser oscillation begins when the absorption loss within the crystal becomes equal. Since the laser beam is emitted from a small area on the cavity end face, a considerable amount of heat is generated inside the crystal. Heat dissipation is essential in order to obtain stable laser characteristics after oscillation. Below, based on Figure 4,
The process of die-bonding the LD chip 1 onto the heat dissipation metal block 5 will be explained. A submount base 2 is mounted on the heat radiation metal block 5. On both sides of the submount base 2, one Ti layer 31. Second layer Ni layer 33. A barrier layer 3 is formed in which a third Au layer 34 is laminated.
さらに、バリヤ層３の上に、全面がＳｎ半田層４で覆わ
れるような形でメツキが施される。ＬＤチップ１は、こ
のサブマウント基体２の上にマウントされる。その後、
ＬＤチップ１がダイボンド中に動かないように、ある荷
重で加圧され、放熱用金属ブロック５の下方よりヒート
アップする。ある温度になると、ＬＤチップ１の裏面電
極６の金属および放熱用金属ブロック５の表面に施され
たＡｕ層と、サブマウント基体２の両面に施されたＳｒ
ｉ半田層４との間でＡｕ−３ｎ （Ｓｎ ｒｉｃｈ）
の半田層が形成されて接合される（ダイボンド完了）。Furthermore, plating is applied on the barrier layer 3 so that the entire surface is covered with the Sn solder layer 4. The LD chip 1 is mounted on this submount base 2. after that,
In order to prevent the LD chip 1 from moving during die bonding, it is pressurized with a certain load and heats up from below the heat dissipation metal block 5. When a certain temperature is reached, the metal of the back electrode 6 of the LD chip 1 and the Au layer applied to the surface of the heat dissipation metal block 5 and the Sr layer applied to both sides of the submount base 2
Au-3n (Sn rich) between i solder layer 4
A solder layer is formed and bonded (die bonding completed).
ここで使用しているＳｉからなるサブマウントは、ダイ
ボンドする際の半田剤的なものであるとともに、ダイボ
ンド中の放熱用金属ブロック５の熱膨張によるＬＤチッ
プ１の歪を緩和するために、非常に重要な部品である。The submount made of Si used here is used as a solder agent during die bonding, and is also used to alleviate distortion of the LD chip 1 due to thermal expansion of the heat dissipation metal block 5 during die bonding. It is an important part.
上記のように構成された光半導体素子用サブマウントは
、サブマウント基体２の最表面のＳｎ半田層４がメツキ
により形成されているため、Ｓｎ半田層厚がばらつき、
安定なＡｕ−５ｎの共晶半田が形成されず、機械的強度
（接合強度）のばらつきが大きかった。また、ＬＤチッ
プ１の発光点がサブマウント基体２との接合面に近いよ
うな組立方式（Ｊｕｎｃｔｉｏｎ−ｄｏｗｎ組立方式）
においては、半田表面状態、すなわち、サブマウント表
面のＳｎ半田層厚が厚めにメツキされた場合には、ＬＤ
特性の１つであるモニタ電流Ｉｍ特性不良、半田のＰ−
Ｎ接合への付着によるショート不良等が発生する問題点
があった。In the optical semiconductor device submount configured as described above, since the Sn solder layer 4 on the outermost surface of the submount base 2 is formed by plating, the Sn solder layer thickness varies.
A stable Au-5n eutectic solder was not formed, and the mechanical strength (joint strength) varied greatly. In addition, an assembly method in which the light emitting point of the LD chip 1 is close to the joint surface with the submount base 2 (junction-down assembly method)
In the solder surface condition, that is, when the Sn solder layer on the submount surface is plated thickly, the LD
Poor monitor current Im characteristic, which is one of the characteristics, solder P-
There was a problem in that short-circuit defects and the like occurred due to adhesion to the N junction.
この発明は、上記のような問題点を解消するためになさ
れたもので、サブマウント基体の両面にバリヤ層を形成
し、さらに、その上に半田層を形成することにより、最
表面の半田層の厚みを細か〈制御できるようにし、かつ
安定した機械的強度を得ることができるとともに、高品
質の光半導体素子用サブマウントを得ることを目的とす
る。This invention was made to solve the above-mentioned problems, and by forming a barrier layer on both sides of a submount base and further forming a solder layer on top of the barrier layer, the solder layer on the outermost surface is removed. The purpose of the present invention is to obtain a high-quality submount for an optical semiconductor device, which can finely control the thickness of the substrate and obtain stable mechanical strength.
（問題点を解決するための手段）
この発明に係る光半導体素子用サブマウントは、サブマ
ウント基体をＳｉの電気伝導性材料で構成するとともに
、サブマウント基体の両面に第１層Ｔｉ層、第２層ｐｔ
層からなるバリヤ層を設け、さらに、バリヤ層上に半田
層を形成したものである。(Means for Solving the Problems) A submount for an optical semiconductor device according to the present invention has a submount base made of an electrically conductive material of Si, and a first Ti layer and a first Ti layer on both sides of the submount base. 2 layer pt
A barrier layer is provided, and a solder layer is further formed on the barrier layer.
この発明における光半導体素子用サブマウントは、第１
層Ｔｉ層、第２層ｐｔ層からなるバリヤ層をサブマウン
ト基体の両面に形成し、さらにその上に半田層を形成し
たことから、このサブマウントを介してＬＤチップを放
熱用金属ブロックに接着する際には、サブマウント基体
の電気伝導性を損なうことなく、接着溶融時にＬＤチッ
プの裏面電極と放熱用金属ブロック表面との間で安定し
た密着性の非常に優れた接合が得られる。The submount for optical semiconductor elements in this invention has a first
A barrier layer consisting of a Ti layer and a second PT layer was formed on both sides of the submount base, and a solder layer was further formed on top of the barrier layer, so the LD chip was bonded to the heat dissipation metal block via this submount. In this case, stable and highly adhesive bonding can be obtained between the back electrode of the LD chip and the surface of the heat dissipating metal block during adhesive melting without impairing the electrical conductivity of the submount base.
以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例を示す光半導体素子用サブ
マウントの断面図であり、２はサブマウント基体、９は
半田層で、例えばＡ ｕ −Ｓ ｎ（金８０％、５ｎ２
０％）の合金半田層である。FIG. 1 is a cross-sectional view of a submount for an optical semiconductor device showing an embodiment of the present invention, 2 is a submount base, 9 is a solder layer, for example, A u -S n (gold 80%, 5n2
0%) alloy solder layer.
１０は前記合金半田層９の上に形成されたＡｕ層、３１
は第１層Ｔｉ層、３２は第２層Ｐｔ層で、バリヤ層３０
を形成している。10 is an Au layer formed on the alloy solder layer 9; 31
is the first Ti layer, 32 is the second Pt layer, and the barrier layer 30
is formed.
第２図はこの発明のサブマウントを介して、ＬＤチップ
が放熱用金属ブロック５にダイボンドされた状態を示す
図であり、ダイボンドされる過程は従来技術と全く同様
である。FIG. 2 shows a state in which the LD chip is die-bonded to the heat dissipation metal block 5 via the submount of the present invention, and the die-bonding process is completely the same as in the prior art.
ここで、バリヤ層３０の上に半田層として、Ａｕａ。−
５ｎ２ｏ（重量％）の合金半田層（厚み師５０００人）
９．その上に薄＜Ａｕ層（約５００人）１０が連続的に
、例えば蒸着により形成される。従来のサブマウントと
違って、ＡｕとＳｎの合金半田層９を蒸着により形成し
、さらに、合金半田層９の最表面に薄＜Ａｕ層１ｏを形
成したことで、■常温でも形成されるＡｕ−５ｎの合金
半田層９の表面酸化に起因するダイボンド後の合金半田
層９表面の外観不良（半田の盛り上がり）が著しく低減
される。■接着強度においても、最表面にＡＵ層１０を
形成したことで、従来のＳｎメッキ厚のばらつきによる
Ａ ｕ −Ｓ ｎの配合ズレによる接着性の低下が著し
く改善される。■蒸着により形成されているために、合
金半田層９の厚みのばらつきが十分に抑えられ、特にジ
ャンクションダウン組立法においては、発光点より放射
されたレーザビームが合金半田層９によりけられるとい
うモニタ電流１１特性不良、半田付着によるショート不
良等が著しく低減される。Here, Aua is formed as a solder layer on the barrier layer 30. −
5n2o (weight%) alloy solder layer (thickness master 5000 people)
9. A thin <Au layer (approximately 500 layers) 10 is formed thereon in succession, for example by vapor deposition. Unlike conventional submounts, the alloy solder layer 9 of Au and Sn is formed by vapor deposition, and a thin Au layer 1o is formed on the outermost surface of the alloy solder layer 9. -5n alloy solder layer 9 has a surface oxidation that causes poor appearance (solder swelling) on the surface of alloy solder layer 9 after die bonding, which is significantly reduced. (2) In terms of adhesive strength, by forming the AU layer 10 on the outermost surface, the conventional deterioration in adhesion due to a mismatch in the Au-Sn composition due to variations in Sn plating thickness is significantly improved. ■Since it is formed by vapor deposition, variations in the thickness of the alloy solder layer 9 are sufficiently suppressed, and especially in the junction down assembly method, the laser beam emitted from the light emitting point is eclipsed by the alloy solder layer 9. Current 11 characteristic defects, short circuit defects due to solder adhesion, etc. are significantly reduced.
なお、上記実施例では、合金半田層９としてＡｕとＳｎ
とを用いたが、ＰｂとＳｎであっても同様の効果が得ら
れる。In the above embodiment, Au and Sn are used as the alloy solder layer 9.
However, similar effects can be obtained using Pb and Sn.
以上説明したようにこの発明は、サブマウント基体をＳ
ｔの電気伝導性材料で構成するとともに、サブマウント
基体の両面に第１層Ｔｉ層、第２層ｐｔ層からなるバリ
ヤ層を設け、さらに、バリヤ層上に半田層を形成したの
で、ダイボンド後の半田層表面の半田の盛り上がり等の
外観不良が著しく低減され、また、十分な接着強度を有
する接合が得られ、かつ半田層厚のばらつきが抑えられ
、ＬＤ特性の１つであるモニタ電流Ｉ。特性不良、さら
には半田付着によるショート不良等が著しく低減される
効果がある。As explained above, the present invention allows the submount base to be
A barrier layer consisting of a first Ti layer and a second PT layer was provided on both sides of the submount base, and a solder layer was formed on the barrier layer, so that after die bonding, Appearance defects such as solder swelling on the surface of the solder layer are significantly reduced, a bond with sufficient adhesive strength is obtained, variation in solder layer thickness is suppressed, and monitor current I, which is one of the LD characteristics, is reduced. . This has the effect of significantly reducing characteristic defects and short-circuit defects due to solder adhesion.
第１図はこの発明の一実施例を示す光半導体素子用サブ
マウントの断面図、第２図はこの発明のサブマウントを
介してＬＤチップを放熱用金属ブロックにダイボンドし
た状態を示す図、第３図は従来の光半導体素子用サブマ
ウントの断面図、第４図は従来のサブマウントを介して
ＬＤチップを放熱用金属ブロックにダイボンドした状態
を示す図である。
図において、１はＬＤチップ、２はサブマウント基体、
３０はバリヤ層、３１は第１層Ｔｉ層、３２は第２層ｐ
ｔ層、５は放熱用金属ブロック、９は合金半田層、１０
はＡｕ層である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
第２図
第３図
第４図
手続補正書（自発）
１、事件の表示 特願昭６２−２９８１１４号２、
発明の名称 光半導体素子用サブラウンｌ−訊補正を
する者
代表者志岐守哉
三菱電機株式会社内
こ ７ ・。
５、補正の対象
明細書の発明の詳細な説明の欄
（１） 明細書第８頁５〜６行の「最表回に−Ｊ＝−
ｖ層１０を形成したことで、」を削除する。
（２）同じく第９頁２〜３行の［バリヤ層上に半田層を
形成しなので、」を、「バリヤ層上に合金半田層を、さ
らにその上にＡｕ層を蒸着により形成したので、」と補
正する。
以 上FIG. 1 is a cross-sectional view of a submount for an optical semiconductor element showing an embodiment of the present invention, FIG. FIG. 3 is a sectional view of a conventional optical semiconductor element submount, and FIG. 4 is a diagram showing a state in which an LD chip is die-bonded to a heat dissipation metal block via the conventional submount. In the figure, 1 is the LD chip, 2 is the submount base,
30 is a barrier layer, 31 is a first layer Ti layer, 32 is a second layer p
t layer, 5 is a metal block for heat dissipation, 9 is an alloy solder layer, 10
is an Au layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure 4 Procedural amendment (voluntary) 1. Indication of the case Patent Application No. 1988-298114 2.
Name of the Invention: Person who performs sub-row correction for optical semiconductor devices Representative: Moriya Shiki, Mitsubishi Electric Corporation, Uchiko 7. 5. Detailed explanation of the invention in the specification subject to amendment (1) Page 8 of the specification, lines 5-6, “-J=-
Since the V layer 10 has been formed, "" is deleted. (2) Similarly, on page 9, lines 2 to 3, [because a solder layer was formed on the barrier layer] was replaced with "because an alloy solder layer was formed on the barrier layer, and an Au layer was formed on it by vapor deposition." ” he corrected. that's all
Claims (4)
熱用金属ブロックに接着する光半導体素子用サブマウン
トにおいて、サブマウント基体をＳｉの電気伝導性材料
で構成するとともに、前記サブマウント基体の両面に第
１層Ｔｉ層、第２層ｐｔ層からなるバリヤ層を設け、さ
らに、前記両面のバリヤ層上に半田層を形成したことを
特徴とする光半導体素子用サブマウント。(1) In a submount for an optical semiconductor element in which a chip of an optical semiconductor element is bonded to a metal block for heat dissipation via a submount, the submount base is made of an electrically conductive material such as Si, and both sides of the submount base are made of an electrically conductive material such as Si. A submount for an optical semiconductor device, characterized in that a barrier layer consisting of a first Ti layer and a second PT layer is provided on the substrate, and a solder layer is further formed on the barrier layer on both surfaces.
金層上にＡｕ層を形成したことを特徴とする特許請求の
範囲第（１）項記載の光半導体素子用サブマウント。(2) The submount for an optical semiconductor device according to claim (1), wherein the solder layer is made of an alloy layer of Au and Sn, and an Au layer is formed on the alloy layer.
金層上にＡｕ層を形成したことを特徴とする特許請求の
範囲第（１）項記載の光半導体素子用サブマウント。(3) The submount for an optical semiconductor device according to claim (1), wherein the solder layer is made of an alloy layer of Pb and Sn, and an Au layer is formed on this alloy layer.
とを特徴とする特許請求の範囲第（１）項記載の光半導
体素子用サブマウント。(4) The submount for an optical semiconductor device according to claim (1), wherein the barrier layer and the solder layer are formed by vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62298114A JPH01138777A (en) | 1987-11-25 | 1987-11-25 | Submount for optical semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62298114A JPH01138777A (en) | 1987-11-25 | 1987-11-25 | Submount for optical semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01138777A true JPH01138777A (en) | 1989-05-31 |
Family
ID=17855349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62298114A Pending JPH01138777A (en) | 1987-11-25 | 1987-11-25 | Submount for optical semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01138777A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03148192A (en) * | 1989-11-02 | 1991-06-24 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| EP0622837A1 (en) * | 1993-04-27 | 1994-11-02 | Nec Corporation | An optical semiconductor device and a method of manufacturing the same |
| JP2007266369A (en) * | 2006-03-29 | 2007-10-11 | Kyocera Corp | Wiring board |
| KR100781859B1 (en) * | 2003-09-22 | 2007-12-03 | 가부시끼가이샤 도시바 | Method of manufacturing semiconductor laser device |
| JP2010074195A (en) * | 2002-03-28 | 2010-04-02 | Osram Opto Semiconductors Gmbh | Luminescent diode chip to be flip-chip mounted on carrier, and method for production thereof |
| EP2521173A2 (en) | 2005-03-18 | 2012-11-07 | DOWA Electronics Materials Co., Ltd. | Submount and method of manufacturing the same |
-
1987
- 1987-11-25 JP JP62298114A patent/JPH01138777A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03148192A (en) * | 1989-11-02 | 1991-06-24 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| EP0622837A1 (en) * | 1993-04-27 | 1994-11-02 | Nec Corporation | An optical semiconductor device and a method of manufacturing the same |
| EP0622837B1 (en) * | 1993-04-27 | 2000-10-11 | Nec Corporation | A method of manufacturing an optical semiconductor device |
| JP2010074195A (en) * | 2002-03-28 | 2010-04-02 | Osram Opto Semiconductors Gmbh | Luminescent diode chip to be flip-chip mounted on carrier, and method for production thereof |
| KR100781859B1 (en) * | 2003-09-22 | 2007-12-03 | 가부시끼가이샤 도시바 | Method of manufacturing semiconductor laser device |
| EP2521173A2 (en) | 2005-03-18 | 2012-11-07 | DOWA Electronics Materials Co., Ltd. | Submount and method of manufacturing the same |
| EP2521174A2 (en) | 2005-03-18 | 2012-11-07 | DOWA Electronics Materials Co., Ltd. | Submount and method of manufacturing the same |
| US8472208B2 (en) | 2005-03-18 | 2013-06-25 | Dowa Electronics Materials Co., Ltd. | Submount and method of manufacturing the same |
| US8581106B2 (en) | 2005-03-18 | 2013-11-12 | Dowa Electronics Materials Co., Ltd. | Submount |
| JP2007266369A (en) * | 2006-03-29 | 2007-10-11 | Kyocera Corp | Wiring board |
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