JPS5840754B2 - Key line display method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line display method in a display device, and particularly to a line display method suitable for a character display device.

Conventionally, various methods have been considered for displaying the line in a display device.

The first method is to perform a line display in a 7-code manner, and when a beam reaches a predetermined position, it is detected and a predetermined line video signal is output.

However, this method has the disadvantage that the wires are fixed and various wires cannot be displayed.

Furthermore, if you try to display the type A line, the hardware will become larger, more complicated, and more expensive.

The second method is to store various wire patterns together with character patterns in a pattern memory, read out the wire patterns by commanding the code data string of the wire patterns, and write them into the refresh memory together with the character patterns. This is a method that displays a line by refreshing it.

With this method, various complex line displays can be performed using command data, but the disadvantage is that the length of the command data becomes long, and the line pattern must be written to the refresh memory each time, making high-speed display impossible. There is.

Another drawback is that the capacity of the pattern memory is extremely limited.

Thus, it is an object of the present invention to eliminate the drawbacks of the conventional technology, to provide a high-speed display method, and to provide a wire display method capable of displaying complicated wires. In , the screen is the first one consisting of n, Xm1 elements.
The first region is further divided into 12×m2 (n
2Zn , m2Zm1) pixels, and the line pattern of the first area is configured with the second area as a unit and stored in a line memory provided separately from the screen memory. At least, this is achieved by a wire display method in which the wire pattern is read out from the wire memory and the wires are displayed in synchronization with the refreshing of the screen memory.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit block diagram for realizing the wire display method according to the present invention, and 1 is a circuit block diagram for processing wire input information sent from the center CNT according to a pre-stored program, and a memory address signal MAS. and a microcomputer that outputs the line information KI; 2 is a control unit that converts the line information KI from the microcomputer into a data string suitable for writing into the line memory and outputs it; 3゜4
are a Y-line memory and an X-line memory that store a Y-direction C-line pattern and an X-direction C-line pattern, respectively;
5 is an address buffer that temporarily stores the address of the wire memory output from the microcomputer; 6 is the address buffer 5 which is a refresh counter for refreshing the refresh memory (screen memory);
and a gate circuit that passes any information from the refresh counter 6: 8 is an address register that stores the address of the wire memory; 9. IQ is a matrix/1/multiplexer; 11 and 12 are Y-register and X-register, respectively.

Note that a CRT screen (not shown) is composed of 1024×1024 pixels, and one character is composed of 32×32 pixels.

Therefore, 32 lines and 32 characters per line can be displayed on one screen, and any character can be displayed by refreshing pattern information stored in a screen memory provided in correspondence with the pixels.

Now, in the K-line display according to the present invention, <1024×1024 pixels are divided into a first region group consisting of 8×32 dots, as described in conjunction with FIGS. 2 and 3.
Further, the first area is divided into a second area group consisting of 8.times.8 dots, and the line pattern to be displayed is compressed and stored in the second area as a unit.

Figure 2 is a diagram showing the correspondence between the X-direction line display and the pixels, and CR is the area allocated to display one character (
32×32 pixels), A1 to A1□ are each 8×
The first area consisting of 32 pixels and B1 to B4 are the second areas each consisting of 8×8 pixels, and the diagonally shaded area is a gray line.

FIG. 3 is a diagram showing the correspondence between the gray line display and the pixels in the Y direction. Similarly to FIG. 2, CR is an area (32×32 pixels) allocated to display one character, A, ~ A12
9 is the first region each consisting of 8×32 surface elements, B
1 to B4 are second regions each consisting of 8/8 pixels, and the shaded area is the Y-direction line.

As shown in the figure, the explanation will be made assuming that the X-direction key line has a thickness of 1 pixel and is displayed every 8 pixels in the Y direction, but the present invention is not limited to this, and the Y-direction key line also has a thickness of 1 pixel. Although the description will be made assuming that the image is displayed every 8 pixels in the X direction with the thickness of the pixel, the invention is not limited to this.

Figure 4 is a diagram in which one screen is divided into the first area, A1
~A4oge is a symbol specifying the first area.

Referring back to FIG. 1, the present invention will be explained in detail.

The X-ray line memory 4 and the Y-ray line memory 3 each have 4096 addresses, and each address consists of 4 bits. The X-ray pattern of area A1 is the X-ray pattern of the first area A1 in FIG. 4 at address 2, and the X-ray pattern of area A1 of FIG.
Similarly, the X-ray line pattern of the first area A4096 in FIG. 4 is stored at the address 4096, as well as the X-ray line pattern of the area A33.

Here, the X-ray line pattern of the first area is a 4-bit data string created depending on whether or not there is an X-ray line in each of the four second areas that make up the first area.
If there is an X-K line in the area, it is expressed as "1", otherwise it is expressed as "0".

That is, the X-K line pattern is 1111 in the first area A of FIG. 2, 1000 in the first area A33, 0100 in the first area A65, 0010 in the first area A97,
In the first area A129, it can be expressed as 0001.

On the other hand, in each address of the Y-wire memory 3, the Y-
Key line patterns are memorized.

Here, the Y-K line pattern of the first area is a 4-bit data string created depending on whether or not there is a Y-K line in each of the four second areas that make up the first area.
If there is a Y-key line in the area, it is expressed as "1", and if it is absent, it is expressed as "0", and the line pattern of the first area A1 in FIG. 3 is 1100.

Now, when writing the K-line pattern, when the center CNT commands the start address of the K-line and the length of the K-line, the microcomputer stores the start address in the X-K line memory according to a pre-stored program. It is converted into an address and sent to the address buffer 5.

At the same time, the microcomputer controls the cable length in the controller 2.
Send to.

Now, assume that the start address is 1.1 and the X-K line length is 32 bits.

Note that 1,1 indicates the position of the pixel in the left corner when the screen is divided into 1024×1024 pixels.

The control unit 2 determines that the command is to write the X-K line and the length of the K-line, and writes a 6-bit data string, that is, 11100.
Outputs 0.

Here, the first bit of the above data string indicates whether to write to the X-K line memory or the Y-K line memory, and '
If it is 1", it is X-K line memory, if it is '0", it is Y-
Write to the line memory.

The second bit indicates whether to write 1 or 0 to the position indicated by the 3rd to 6th bits, and 3
The 6th to 6th bits indicate which second area in the first area corresponds to the address specified by the address register 8.

That is, if we focus on the first area A1 in FIG. 2, the second area B1. B2゜B3. The positions of B4 are each represented by 10001010010010.0001.

On the other hand, since the gate 7 operates to store the contents of the address buffer 5 in the address register 8 during writing of the line pattern, the address register 8 contains OOO...
...01 is set.

Note that the address register 8 consists of 12 bits, and the lower 5
The bits correspond to the coordinates of the first region in the X direction, and the upper seven bits correspond to the coordinates of the first region in the Y direction.

However, first, a READ command is issued from the control section 2, and the contents of address 1 of the X-ray line memory are read out and inputted to the multiplexer 10.

At the same time, the control section 2 outputs the aforementioned data 111000 to the multiplexer 10.

The multiplexer 10 receives the X −
From V1deo and the output of the control section, set "1" to the 12-bit position of the X-register corresponding to the second area B1, that is, the first bit, and set "1" to the X-register 1202 to 4 bits.
-V Set the contents of bits 2 to 4 of 1deo.

After that, a WRI T E command is issued from the control unit 2,
The contents of the X-register (1000) are stored at address 1.

As a result, the C line of the second area B1 of the first area A1 is stored in the X-C line memory.Next, the control unit 2 issues a READ command and reads out the contents (iooo) at address 1 again. .

At the same time, the control unit 2 outputs data 110100.

The multiplexer 10 sets "1" to the bit position of the X-register corresponding to the second area B2, that is, the second bit, and sets X-A to the 1.3.4 bits of the X-register 12 by the same operation as described above. ide.

The contents of bits 1, 3, and 4 of (1000) are set respectively.

After that, ■[F]ITE command is issued from the control unit 2 and
- The contents of the register (1100) are written to address 1.

Thereafter, similar operations are repeated, and with the fourth WRITE command, 1111 is written to address 1, and the writing based on the command from the center is completed.

Incidentally, when the length command of the gray line from the center is 32 bits or more, it is sufficient to advance the address in the address register by one and write the gray line in the same way.

Thereafter, the wire pattern of the first areas A1 to A40g6 can be written in the X-wire memory 4 in the same manner, and the wire pattern can be written in the Y-wire memory 3 in exactly the same manner. can.

Next, the display of the X, Y-line pattern will be explained with reference to FIGS. 5 and 6.

Gate 7 in Figure 1 is used for CRT display of the C-line pattern.
functions to store an address based on the contents of refresh counter 6 in address counter 8.

The refresh counter 6 has an X-counter and a Y-counter (10-bit binary counter) each having a capacity of 1024, the contents of which always indicate the heel coordinate position in units of pixels.

However, the coordinates of each pixel are converted into the coordinates of the first area and stored in the address register 8.

That is, the first area is divided into 32 pixels in the X direction, so the top 5 rows of the X-counter are divided, and in the Y direction, it is divided into 8 pixels, so the top 7 rows of the Y-counter are By storing each pixel in parallel in the address register 8, coordinates in units of pixels can be converted and stored into coordinates in the first area.

FIG. 5 is a Y-K line development diagram, and FIG. 6 is an X-K line development diagram. 51 to 54, 101 to 104, and 107 are gates; 55, 105 is a shift register; and 106 is a flip-flop; w'rp is write timing pulse;
MSK is a mask signal: X-Video is a 4-bit X-
Line pattern: YVideo is a 4-bit Y-line pattern.

When an address is set in the address register 8, the X-key line pattern X-V 1deo and the Y-key line pattern Y-V 1deo of the address are simultaneously read out.

The first bit of the Y-key line pattern YVide□ consisting of 4 bits is sent to the gate 51, the second bit is sent to the gate 52,
The third bit is input to gate 53, and the fourth bit is input to gate 54.

On the other hand, the output terminals of gates 51 to 54 are connected to shift register 55.
The write timing pulse wfrp is input to the other input terminals of the gates 51-54.

However, when the write timing pulse WTP is generated at the same time as the Y-key line pattern is read out from the Y-key line memory 3, the Y-key line pattern is transmitted through the respective gates 51 to 54 to the shift registers 1, 9, 17, . Written to 25 bits.

After that, the shift register 55 is set to 1 in synchronization with refresh.
If you output while shifting bit by bit, the CRT KY line will be displayed.

When the 32-bit shift is completed, the contents of the address counter 8 in FIG. 1 are immediately incremented by one step, and the Y/K line pattern stored at that address is read out and set in the shift register 55 again.

Thereafter, the operation is similar, and the CRT displays a line pattern corresponding to the line pattern stored in the Y-line memory.

Next, the X-Qui line display will be explained in terms of °C.

X consisting of 4 bits read from the X-ray memory 4
- The first bit of the X-Vide□ line pattern is input to the gate 101, the second bit to the gate 102, the third bit to the gate 103, and the fourth bit to the gate 104.

On the other hand, the write timing pulse WTP is input to the other input terminals of gates 101 to 104.
The output of gate 103 is sent to bits 1 to 9 of shift register 105, the output of gate 102 is sent to bits 9 to 17 of shift register 105, and the output of gate 103 is sent to bits 1 to 9 of shift register 105.
17 to 25 bits, the output of K1-104 is shifted to the shift register 105, 25 to 32 bits, and a flip described below.
It is input to flop 106.

The input terminal of the 1st bit of the shift register 1050 is connected to the set terminal of the gate 101 and the flip-flop 106 through the OR gate 110, and the input terminal of the 9th bit is connected to the gates 101 and 102 through the OR gate 112.
The input terminal of the 25th bit is connected to gates 102 and 103 via an OR gate 113, and the input terminal of the 25th bit is connected to gates 103 and 104 via an OR gate 114.

Since the gates 101 to 104 are intercepted so that if "1" is inputted to each gate, "1" is outputted to each output line.
At the same time as the X-ray pattern in the first area A1 is read out from the X-ray line memory 4, a write timing pulse WTP is applied.
When generated, the X-ray pattern is transferred to the shift register 105.
Also, the clip flop 106 is set or reset according to the fourth bit information of the X-ray pattern.

After the above write, shift register 1 is updated in synchronization with refresh.
If you output 05 while shifting it one bit at a time, the CRT
The KX-K line will be displayed.

When the 32-bit shift is completed, the contents of the address register 8 in FIG. 1 increments by one step and becomes 2, and the X-ray pattern of the first area A2 stored at the address is read out, and the same operation is performed thereafter. , 1. on the CRT. All X-K lines for the shipment are displayed.

When the line display for one line is completed, that is, when the refresh for one line is completed, the address register 8 becomes 1 again, and the X-line pattern in the first area A1 is read out and written to the shift register 105 in the same way. It will be done.

Thereafter, the data is output while being shifted one bit at a time in synchronization with refresh, but since the X-K line pattern is not displayed on the second to eighth rows, the gate 107 is closed by the mask signal MSK. 4. The output signal of the shift register is not given to the brightness control section of the CRT.

Here, the mask signal MSK is a signal that is set to "1" by a timing circuit (not shown) every eight refreshed rows and only during the refresh time of one row.

If it is desired to display a line pattern with a width of two lines (width of two pixels), the mask signal may be set to "1" every 8 refresh lines and only for the Frenonyu time of 2 lines.

FIG. 7a is an example of displaying the C1 line according to the present invention.
〜C4 is the or gate 111-1 in FIG.
14, this is the portion that is displayed due to the presence of the clip/flip 106.

When these OR gates 111 to 114 and the flip-flop 106 are thrown, the K line is displayed as shown in Fig. 7, that is, the K line is displayed at the corner portions C1 to C4 formed by the Y-K line and the X-K line. It doesn't look good.

However, in the present invention, when converting the X-ray line pattern in the first region into a line pattern on a pixel basis, a part of the line pattern on a pixel basis is obtained additively.

That is, the first bit of the line pattern in the first area is made to correspond to the 1st to 9th bits of the line pattern row for each pixel, and
The bits are made to correspond to the 9th to 17th bits of the line pattern string in each pixel, the third bit to the 17th to 25th bits in the line pattern string in each pixel, and the fourth bit to the 25th to 32nd bits in the line pattern string in each pixel. The contents of the fourth bit are also stored in the flip-flop 106.

Also, the output of the flip-flop 106 is inputted to the OR gate 111 together with the output of the gate NO1, and the gates 101 and 1 are connected to each other.
02 to the OR gate 112, gate 1
Connect one output line each of 02 and 103 to the OR gate 113,
One output line each of gates 103 and 104 is connected to OR gate 1.
14, and then input each OR gate 111 to 11.
Since the outputs of 4 are input to the 1-bit, 9-bit, 17-bit, and 25-bit shift registers, respectively, C1 to C4 shown in FIG. This results in a good K-line display.

As described above, according to the present invention, the line pattern to be displayed is stored in advance in a line memory provided separately from the screen memory, and the line pattern is output in synchronization with refresh, so that the control is controlled. can be displayed easily and quickly.

In addition, it is equipped with an X-key line memory and a Y-key line memory as key line memories, and these are equipped with an X-direction line pattern and a Y-line pattern.
By pre-memorizing unidirectional key line patterns, various and complex key line displays can be made.

Furthermore, since the wire pattern is stored in the wire memory after being compressed to 1/64 (8×8) of the pattern in the screen memory, the capacity of the wire memory can be significantly reduced and costs can be reduced.

In addition, since the C line can be displayed even in the corner portion consisting of the X-K line and the Y-K line, visually pleasing C line display can be achieved.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the K-line display method according to the present invention, and the second embodiment
The figure shows the correspondence between the X-direction C-line display and the pixels.
The figure shows the correspondence between the C-line display in the Y direction and the pixels.
The figure shows one screen divided into the first area, Figure 5 is a Y-K line display development diagram, Figure 6 is an X-K line display development diagram, and Figure 7
The figure is an example of the display of the key line according to the present invention. In the figure, 1 is a microcomputer, 2 is a control unit, and 3 is Y
-K line memory, 4 is X-K line memory, 5 is reflex counter, I is gate, 8 is address register, 1
1.12 are X, Y registers, A, ~A4o96 respectively
is the first area, B1 to B4 are the second area, C1 to C4 are corner guide lines, 55°105 is a shift register, 10
6 is a frisono flop, and MSK is a mask signal.

Claims (1)

[Claims] 1. The screen is divided into a first region consisting of n, xm pixels, and the first region is further divided into n2 Xm2 (n2.ffn
1, rn2%rn1), and the line pattern of the first area is configured with the second area as a unit, and is stored in a line memory provided separately from the screen memory. A wire line display method characterized in that the wire pattern is stored in advance and the wire pattern is read out from the wire memory and displayed in synchronization with refreshing of the screen memory. 2. The line display system according to claim 1, wherein the line memory includes an X-direction line memory and a Y-direction line memory. 3. The system according to claim 1, wherein the cable pattern read out from the cable memory is converted pixel by pixel, stored in a shift register, and then outputted while being shifted bit by bit. Line display method. 4. The line display method according to claim 1, wherein m1 is the number of pixels in the X direction allocated to display one character. 5 Divide the screen into a first region consisting of nlXm1 pixels, and further divide the first region into n2Xm2 (n2≦
(n1, m2≦m,); and a key line memory provided separately from a screen memory, wherein the key line pattern of the first area is configured with the second area as a unit. The key line pattern is read out from the key line memory in synchronization with the refresh of the screen memory, converted into pixel units, stored in a shift register, and then outputted while shifting one focus at a time. A line display method characterized in that the output of the shift register is gated when a line that does not need to be displayed is refreshed. 6 Divide the screen into a first region consisting of n1×m1 pixels, and further divide the first region into n2 Xm2 (n2.ffn
. m2. ffm1), and the line pattern of the first area is configured with the second area as a unit and stored in a line memory provided separately from the screen memory. In the D-line display method, in which the D-line pattern is read out, converted into a D-line pattern in units of pixels, stored in a shift register, and then outputted while being shifted one bit at a time, the second area is used as a unit. When converting a line pattern into a pixelated line pattern, convert the line pattern of pixels forming the boundary between one second region and another second area adjacent to this one and the other second area. A C-line display method characterized in that the C-line pattern is obtained additively from the C-line pattern in the second area.