JPS5840647A - Data processing system - Google Patents

Abstract

PURPOSE:To shorten a processing time by providing two pairs of memories and data processors, and processing two-way queue in parallel. CONSTITUTION:A data processing circuit A10 and a data processing circuit B20 have the same constitution. A microprogram sequencer (MPS) 40 which controls and indicates operations of the data processing circuits A10 and B20, etc., is connected to a memory 21, an address register 22, and a data register 23. A connecting circuit (SW) 50 performs switching between output buses A17 and B27, and input buses A14 and B24. When a slave indication 41 is received from the MPS40, the data processing circuit A10 and data processing circuit B20 perform parallel operation and when there is not the S indication, only the data processing circuit B20 performs processing in sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system, and more particularly to a data processing system for processing bidirectional keys.

A bidirectional queue 1 is created in order to cope with the case when a processing request for various resources such as an input/output device, a process, etc. is received and the resource is not available. This two-way queue is fully formed! ! When it is necessary to take out the ixt from the bidirectional queue in order to give priority processing to the previous element, the element is deleted. This is called bidirectional queue processing.

Conventionally, the above-mentioned method for processing bidirectional keys is based on so-called point-by-point processing, in which one memory and one data processing device are installed to perform processing in one direction and then to process the other direction. This method has the disadvantage that the processing time for the two-way key is long.

The object of the present invention is to eliminate all of the above-mentioned drawbacks and to provide a data processing system that is equipped with two sets of memories and data processing devices and processes two-way keys in parallel, thereby reducing the processing time by half. .

The data processing method according to the present invention includes a memory for storing data, an address register for determining the address of the memory, and at least one data register for temporarily storing the processing result of the data.

An input path connecting each input of these 3al devices,
a first data processing means comprising the memory and an output bus on which a friend output is selectively retrieved from the data register; and a second data processing means having the same configuration as the first data processing means. and the above-mentioned No. 1. connection means for interconnecting each said output bus and each said input bus of said second data processing means; Second
The invention is characterized in that it can provide instruction means for operating the data processing means in parallel.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a state diagram showing before and after processing of a bidirectional queue according to an embodiment of the data processing method of the present invention. In the figure, 1.5 is a head address, This is a pointer that indicates the tail address. Also, 2, 3.4 are elements of a bidirectional queue (hereinafter referred to as queue 1).
! ) and the numbers shown outside these queues 2.3.4 @1000'', @2000'.

@3000" is the start address of each queue element 2, 3.4, and the numbers ""1000", "2000", "3000" shown in queue g1 element 2, 3.4 are the start addresses of each queue element 2, 3.4, ! This is an address that is included in the original address. A queue in one direction is formed in the order of queue elements 2, 3.4, and a queue in the other direction is formed in the order of queue elements 4, 3.2. First, in the one-way queue, when pointer 1 points to the start address @1000 of queue element 2, queue element 2
Queue 1 due to address "2000" in! The start address of element 3 @2000'' is further changed to the start address of element 4 by address @3000'' in queue element 3.
3000'''. In the queue in the other direction, pointer 5 points to the start address of queue element 4 "3".
000'', address @2 in key, -* prime 4
000'' causes the start address of queue element 3 to be ``2000''.
" is further specified in the order of the start address @1000" of queue element 2 by the address @1000" in queue element 3. Here, as an example, the process of deleting queue 'Jt' 3 from the bidirectional key, - It is clear that the bidirectional queue after processing is formed by Ki, -g!82 and queue element 4 as shown in FIG. 1(b).

Next, Figure 1 (C1, (di is a diagram showing the arrangement in memory for explaining the bidirectional queue processing method in Figure 1 (al, (bl), which shows before and after bidirectional queue processing, respectively. In the figure, 6, 7.8 are keys of the one-way keys indicated by head address 11'', address ``''t'', and tail address 16'', respectively.

- element, 9 indicates the key in the other direction indicated by address 1, - queue g, and 11°21 indicates memory A and memory Bi, respectively, and the leftmost numbers 1 to 6 indicate the memory input, indicates the address of B. Therefore, memory All
Contents of 13″, 16″.

@θ″ is the key in one direction in Figure 1), - key, -gI
Corresponding to the contents of element 2, 3.4, respectively, Makumemory B2
'l(D content @3'', ``'', ``0''fl FIG. (shown in FIG. 1(a)) from the bidirectional queue, the addresses of memory All and memory B21 @
The respective contents "6' and @1" shown in No. 1 are deleted from the t-memory array and put into the array shown in FIG.
The contents of the tail address of the memory B210 will be rewritten from "3" to @6", and the contents of the tail address of the memory B210 will be rewritten from @3" to @1.Next, this rewriting operation will be explained.In memory All, the contents of queue element 7 1 °6" to the address indicated by the previous queue element, that is, the address indicated by queue element 6 (write address). In this case, it is necessary to write the chain By looking at the contents of the address indicated by the queue element 9 @ls tube, we know the address @1'' of the memory All, which is the write address, and write that address. All you have to do is write @6” to the contents of the address.Similarly, memory B2
1, it is sufficient to write "1" to the contents of the tail address by tracing the chain ■ backwards and isometrically adding the chain ■1 to the chain ■1.

Next, FIG. 2 depicts one implementation of the data processing scheme of the present invention.

That is, the data processing circuit AIO includes a memory A (hereinafter referred to as MA) 11 that stores data, an address register A (hereinafter referred to as ARA) 12 that is connected to MAll by an instruction line 18 and determines and instructs the address of MAll, and a memory A (hereinafter referred to as ARA) 12 that stores data. Data register A (hereinafter referred to as RNA) that temporarily stores
)13, MALLl, ARI2. It consists of an input bus A14 that connects each input of RNA13, a ratio output gate 16 that is connected to MAII and is connected to output gate 15 and RNA13, and an output bus A17 that connects the outputs of output gates 15 and 160. Similarly, data processing circuit B
20 is a memory B (hereinafter referred to as MB) 21, an instruction line 28, an address register B (hereinafter referred to as ARB) 22, a data register B (hereinafter referred to as RNB) 23, an input bus B24, output gates 25, 26, and an output bus. It consists of B27. Data processing circuit AIO, 8 by Maku micro program
A micro program sequencer (hereinafter referred to as MPS) 40Fi, MB21. ATtB
22° Connected to RNB23 and game) 30, 31.3
2 are connected to one of the input sides of each write signal 35.
．． 36, 371'', connected to output gates 25, 26, and one of the input sides of gates 33 and 34 to give read signals 38 and 39, respectively.
The other input side of 0 to 34 is multi-connected and MP84
0 and receives a slave instruction (hereinafter referred to as S instruction) 41. The output sides of gates 30°, 31, and 32 are MAI, respectively.
1. ARA12゜RNA13 and W! The outputs of gates 34 and 35 are connected to output gates 15 and 16, respectively, to provide a write signal. In addition, the connection circuit (hereinafter referred to as sw) 50 is the output bus A17.
B27 and input bus A14. It has a function to switch and connect between the MP840 and the MP840, and according to the normal/exchange instruction (hereinafter referred to as the N/E instruction) from the MP840, when the N instruction is issued, connections c-a, d-b'Jk are made, and when the E instruction is made, the connections are made c-a, d-b'Jk. is Wc continuation c
-b, d-ai is executed, MP840 is executed in parallel (parallel operation), and when there is no S instruction 41, data processing circuit B2
Only 0 works. The latter is a conventional data processing method that uses one data processing circuit for point-by-point processing (serial operation).
is the same as

In this embodiment, both the parallel operation and serial operation can be performed as necessary.

Table 1 shows the main operations when there is an S instruction in this embodiment.
The sequence of forward motion is shown. In the same table, this is @Figure 1 (
As shown in C), the key indicated by the address "1", -*
It is basic.

Table 1 Next, specific manufacturing of each step of the main operation and forward operation will be explained. First, in the main operation, in the first step Lf
Set in the ARB 22 by the second light signal 36 (first
(address 13'' is set in C1), in the second step, ARB22 indicates MB2 indicated by instruction line 28.
1 address (address 13” in Figure 1 (C))
The data (Fig. 1 (data @l'' in C1) pWIt is extracted by the t read signal 38, and this is sent to the write signal 37.
By MB21-output gate 25-output bus B27-
8W50 (cm) - RNB via human powered bus B24
Write on 23.

The third step is the RNB written in the second step.
23 data is read by the read signal 39, and this Q
A write signal from MP840 via gate 31 causes RNB23-output gate 26-output bus B27-8W5.
0 (C-b) - Girlfriend (AI't12 through A14)
write to. In the fourth step, the data written in the RN823 in the second step is read out using the read signal 39, and the data is read out by the write signal 35 to the RNB23-output gate 26-output (SB27-8W50(c-a)-
This address is 4 indicated by the instruction line 28 in AlB12, so it is address 16'' in FIG. Specific movements similar to each step and step of the main movement are performed, so explanations are omitted (,
Since there are 8 instructions, the main operation and slave operation are performed in parallel, and the contents of the head address of MAI 1 are from @3'' to 16'.
Then, the contents of the tail address of 9MB21, tl@3', are rewritten to ``l''.

If the time for memory access is predominant, the time for this rewriting process is the time t for two memory accesses.

In this embodiment, each data processing circuit has one data register, but a plurality of data registers may be provided as required.

Next, Table 2 shows a so-called serial operation sequence in which bidirectional keys and - are processed not by the method of the present invention but by the conventional method. t & FIG. 3 is a diagram showing an arrangement on a memory for explaining a method of processing bidirectional keys and - in Table 2.

Table 2 - In Table 2 and Fig. 3, Bl, B2Fi are realized bidirectional keys, - are the addresses immediately before each start address, M is memory, AR is memory address register, R
O and R1 are general-purpose registers. Here, it is assumed that the contents of each address of Satomemine in FIG. 3 correspond to the friends shown in FIG. 1(C). The specific operations of each step and step of the serial operation in Table 2 are based on Table 1, so a detailed explanation will be omitted.This serial operation is a one-way key.

- Since processing and queue processing in the other direction are executed on one memory M, the processing time is the time 'ti for four memory accesses, assuming that memory access time is dominant.

As is clear from the above explanation, according to the data processing method of the present invention, by performing the processing of the memory and the data processing device &t2 sets of bidirectional keys, - in parallel, the processing time can be reduced compared to that of the conventional method. This has the great effect of reducing the amount by half compared to the previous year.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are state diagrams showing before and after processing, respectively, of bidirectional keys and - according to an embodiment of the data processing method of the present invention; FIG. Diagram (a)
, (A diagram showing a memory arrangement for explaining the method of processing bidirectional keys, - in BL, FIG. 2 is a block diagram showing an embodiment of the data processing method of the present invention, and FIG. 3 is a diagram showing the conventional It is a diagram showing an arrangement on memory for explaining the method of processing bidirectional keys according to the method. 1.5... Pointer, 2, 3, 4, 6. to 9.
...ki, -*element, 10,20...data processing circuit, 11.21...memory, 12.22
...Address register, 13.23...
・Data register, 14°24...Input lotus,
15, 16, 25.26... Output gate, 17
．． 27... Output path, 18.28...
Instruction line, 30-34...game), 35, 36° 37...write signal, 38.39...read signal, 40...micro program sequencer%41 ...Slave instructions, 42...
Normal/exchange instruction, 50...Connection circuit. 21 Figure #2 1 1 1 #3

Claims (1)

[Claims] A memory that multiplies data t-S, an address register that determines the address of the memory, and at least one data register that temporarily stores the processing result of the data, and a connection between each of these three types of devices. a first data processing means consisting of an output bus on which outputs alternatively outputted from the memory and the data register are carried; The second with the configuration
data processing means; and the first data processing means. connection means that enables mutual connection between each of the output buses and each of the long distance buses of the second data processing means; A data processing method comprising: instruction means for operating the second data processing means in parallel.