JPS5840433Y2 - Photocurrent amplifier circuit - Google Patents

Photocurrent amplifier circuit

Info

Publication number
JPS5840433Y2
JPS5840433Y2 JP9449577U JP9449577U JPS5840433Y2 JP S5840433 Y2 JPS5840433 Y2 JP S5840433Y2 JP 9449577 U JP9449577 U JP 9449577U JP 9449577 U JP9449577 U JP 9449577U JP S5840433 Y2 JPS5840433 Y2 JP S5840433Y2
Authority
JP
Japan
Prior art keywords
photoelectric conversion
transistor
blocks
transistors
npn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9449577U
Other languages
Japanese (ja)
Other versions
JPS5422428U (en
Inventor
健太郎 時国
Original Assignee
日本電信電話株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電信電話株式会社 filed Critical 日本電信電話株式会社
Priority to JP9449577U priority Critical patent/JPS5840433Y2/en
Publication of JPS5422428U publication Critical patent/JPS5422428U/ja
Application granted granted Critical
Publication of JPS5840433Y2 publication Critical patent/JPS5840433Y2/en
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は、多数個の微小電流出力形の光電変換素子列の
走査駆動回路ふ・よび根電流増幅回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scanning drive circuit and a root current amplification circuit for a large number of small current output type photoelectric conversion element arrays.

従来、この種の光電変換単位素子の充電流増幅回路とし
ては、第1図asbに示すように光電変換素子1を、ト
ランジスタ2のベース側に接続し、光入力によりベース
電流を変調し、これによって相隔されたコレクタ電流を
得る増幅回路があった。
Conventionally, as a charge current amplification circuit for this type of photoelectric conversion unit element, a photoelectric conversion element 1 is connected to the base side of a transistor 2 as shown in FIG. There was an amplifier circuit that obtained collector currents spaced by .

本考案は、これら単位光電流相隔回路の組み合わせを用
いて、マトリックス化された光電変換素子の引出し線を
走査駆動するようにしたもので、その目的は、マトリッ
クス化による回路規模を縮小し、更に微小電流を増幅し
て出力するにある。
The present invention uses a combination of these unit photocurrent spaced circuits to scan and drive lead lines of photoelectric conversion elements arranged in a matrix.The purpose of this invention is to reduce the circuit scale due to matrixing, and further Its purpose is to amplify and output a minute current.

第2図は多数個の光電変換素子をマトリックス結線する
場合の接続例であって、片側の端子列は左端の素子から
n本づつmブロック化され(これをn側と呼ぶことにす
る)、もう片側の端子列はn本おきに接続されnブロッ
ク化される(これをY側と呼ぶことにする)。
FIG. 2 is a connection example when a large number of photoelectric conversion elements are connected in a matrix, and the terminal row on one side is divided into m blocks of n terminals each starting from the leftmost element (this will be referred to as the n-side). On the other side, every n terminal rows are connected to form n blocks (this will be referred to as the Y side).

第3図はX・(l≦j≦m;整数)−Yj(1] ≦j≦n;整数)間のマトリックス成分を書き出したも
ので、Trl s Tr3はPNP s Tr2Tr
4はNPNの各トランジスタ、Rij(isj)の光電
変換素子の抵抗、R1sR2は増幅回路負荷抵抗、R3
sR4はスイッチングTr3 。
Figure 3 shows the matrix components between X.
4 is the resistance of each NPN transistor, Rij (isj) photoelectric conversion element, R1sR2 is the amplifier circuit load resistance, R3
sR4 is switching Tr3.

Tr4 のベース入力抵抗、R5−R7はスイッチング
動作を完全にするためのバイアス用抵抗である。
The base input resistance of Tr4, R5-R7, is a bias resistance to complete the switching operation.

xi 、y、/I′iマトリックス選択信号入力端子、
P//i増幅出力端子である。
xi, y, /I′i matrix selection signal input terminal;
P//i is the amplification output terminal.

次にこれを動作するにはXiを論理ロウ、Y。Next, to operate this, set Xi to a logic low, Y.

を論理ハイとする。is a logical high.

このときTr3 s Tr4がそれぞれオンし、トラ
ンジスタT r 1のエミッタは十Vccへ、トランジ
スタT r 2のエミッタはGND〜くイアスされ、こ
れによってトランジスタT r 1のベース電流jBが
(] IJ)の光電変換素子の抵抗Rijからトランジ
スタT r 2のベースへと流れ、トランジスタTr1
のコレクタ電流は)1feiBとなり、増幅された出力
電圧R1hfe1BがP端子に得られる。
At this time, Tr3 and Tr4 are turned on, and the emitter of the transistor Tr1 is connected to 10 Vcc, and the emitter of the transistor Tr2 is connected to GND, so that the base current jB of the transistor Tr1 becomes (]IJ). Flows from the resistor Rij of the photoelectric conversion element to the base of the transistor Tr2, and the transistor Tr1
The collector current becomes )1feiB, and an amplified output voltage R1hfe1B is obtained at the P terminal.

x、、y、が上記論理レベル以外のときは(j、j)の
光電変換素子の抵抗Rijへの電流の流入端、または流
出端が開放されるため、(itj)の光電変換素子の抵
抗R,,には電流が流れず、P点はGND電位の11と
なる。
When x,, y, are at other than the above logic level, the inflow end or outflow end of the current to the resistor Rij of the photoelectric conversion element (j, j) is opened, so that the resistance of the photoelectric conversion element (itj) No current flows through R, , and point P becomes 11, which is the GND potential.

以上光入力がある場合の動作であるが、光入力がない場
合は(j、j)の光電変換素子の抵抗Rij→ωとなる
ため、jB−+Oとなり、P点電位もGNDレベルとな
る。
The above is the operation when there is optical input, but when there is no optical input, the resistance Rij of the photoelectric conversion element of (j, j) becomes ω, so it becomes jB−+O, and the potential at point P also becomes the GND level.

従って光入力によ!1ljBが変調されればP点電位も
IBに応じて変調増幅されることとなる。
Therefore, use optical input! If 1ljB is modulated, the potential at point P will also be modulated and amplified according to IB.

また出力端子をトランジスタT r 2のコレクタに設
ける方法もあるが、出力に直流成分が重畳されるため、
=般には使用しにくい。
There is also a method of providing the output terminal at the collector of transistor T r 2, but since a DC component is superimposed on the output,
= Generally difficult to use.

第4図は第3図の単位回路を第2図に示したマトリック
スに構成するための接続を示したもので、X側単位回路
m個、Y個単位回路n個を、光電変換素子のマトリック
ス化された各引出し線に接続シ、増幅用トランジスタT
r 1のm個のコレクタを共通にして抵抗R1を共通
し、P点を出力端子とする。
Figure 4 shows the connections for configuring the unit circuits in Figure 3 into the matrix shown in Figure 2. connected to each lead line connected to the amplification transistor T.
The m collectors of r1 are shared, the resistor R1 is shared, and the point P is used as an output terminal.

以上説明したように本考案により、複数個の微小電流出
力形の光電変換素子をマトリックス化して走査駆動する
ことができ、かつ充電流増幅も併せて行なうことができ
るから、走査回路の回路規模縮小が期待でき、充電流増
幅回路を新たに設ける必要がないなどの利点がある。
As explained above, according to the present invention, multiple microcurrent output type photoelectric conversion elements can be arranged into a matrix and scan-driven, and charge current amplification can also be performed, thereby reducing the circuit scale of the scanning circuit. This method has the advantage that it is not necessary to newly provide a charging current amplification circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a s bは従来例、第2図乃至第4図は本考案
の光電流纒回路の実施例を示す。 R□・R7・・・抵抗、Ri、・・・(itj)の光電
変換素子の抵抗、Tr1〜Tr4 ・・・トランジス
タ、X4 pY3・・・マトリックス選択信号入力端子
1A and 1B show a conventional example, and FIGS. 2 to 4 show examples of the photocurrent wiring circuit of the present invention. R□・R7...Resistor, Ri,...(itj) photoelectric conversion element resistance, Tr1 to Tr4...Transistor, X4 pY3...Matrix selection signal input terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] シリコンフォトダイオード、cds光導電体などの光電
変換素子をアレイ状に多数個並べた固体光電変換装置を
順次走査する場合において、各光電変換単位素子の各2
本の引出し線のうちの一方を端からn本づつmブロック
に、他方をn本おきにnブロックに結線しmXnのマト
リックスとなし、かつm個のブロックは各々m個の増幅
用PNPトランジスタのベースに接続し、n個のブロッ
クは各々n個のNPN)ランジスタに接続し、かつ各P
NP)ランジスタのエミッタと十電源間にマトリックス
選択用PNP)ランジスタを接続し、各NPN)ランジ
スタの工□ツターGND間にマトリックス選択用NPN
)ランジスタを接続するようになし、さらに各増幅用P
NP )ランジスタのコレクタを共通にし負荷抵抗1本
でGNDへ接続し、この抵抗のコレクタ側を出力端子と
することを特徴とする光電流増隔回路。
When sequentially scanning a solid-state photoelectric conversion device in which a large number of photoelectric conversion elements such as silicon photodiodes and CDS photoconductors are arranged in an array, two of each photoelectric conversion unit element are scanned.
One of the lead wires of the book is connected to m blocks every n from the end, and the other is connected every n to n blocks to form an mXn matrix, and each m block is connected to m blocks of amplifying PNP transistors. the n blocks are each connected to n NPN) transistors, and each P
Connect the PNP) transistor for matrix selection between the emitter of the NP) transistor and the power supply, and connect the NPN for matrix selection between the terminal and GND of each NPN) transistor.
) to connect the transistors, and each amplification P
NP) A photocurrent amplifier circuit characterized in that the collectors of transistors are shared and connected to GND through a single load resistor, and the collector side of this resistor is used as an output terminal.
JP9449577U 1977-07-18 1977-07-18 Photocurrent amplifier circuit Expired JPS5840433Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9449577U JPS5840433Y2 (en) 1977-07-18 1977-07-18 Photocurrent amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9449577U JPS5840433Y2 (en) 1977-07-18 1977-07-18 Photocurrent amplifier circuit

Publications (2)

Publication Number Publication Date
JPS5422428U JPS5422428U (en) 1979-02-14
JPS5840433Y2 true JPS5840433Y2 (en) 1983-09-12

Family

ID=29026550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9449577U Expired JPS5840433Y2 (en) 1977-07-18 1977-07-18 Photocurrent amplifier circuit

Country Status (1)

Country Link
JP (1) JPS5840433Y2 (en)

Also Published As

Publication number Publication date
JPS5422428U (en) 1979-02-14

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