JPS5840211B2 - Kiokusouchichiseigiyohoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device control system in which the number of information holding circuits including an interface circuit and a storage control circuit is smaller than the number of independently operable storage modules.

Storage devices used in information processing systems are configured in such a way that a single storage unit covers the storage capacity required at the maximum scale of the system, which would result in higher prices for small-scale systems, and the electricity consumption of the storage devices. When considering physical performance, manufacturability, and the cost of installing a spare storage unit as a countermeasure against failure, it is often economically advantageous to divide the power into appropriately sized storage units. For this reason, a configuration in which the storage unit is divided into multiple sets of storage units is generally used.

The configuration within the storage unit includes a storage module section for storing information and other devices such as a central processing unit (CP).
The reception of information with U) is classified into an interface circuit that performs the transfer and a storage control circuit that controls the storage operation of the storage module section.

In conventional storage devices, an interface circuit and a storage control circuit are provided for each storage unit.
Even if storage module parts are made smaller and cheaper due to the adoption of semiconductor integrated memory, etc., the proportion of the two circuits mentioned above in the storage device is high and becomes a factor that hinders the miniaturization and price reduction of the storage device. ing.

An object of the present invention is to provide a storage device control system in which the number of information holding circuits including an interface circuit and a storage control circuit is smaller than the number of independently operable storage modules.

The principle and embodiments of the present invention will be explained in detail below.

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, and is an explanatory block diagram showing connections between a storage device 2 and other devices such as a central processing unit (CPU) 1 surrounded by chain lines.

In the same figure, reference numerals 131, 132 and 133 indicate the storage module section (MEMl, 2.3), and 110, 112 and 121.12□ indicate an interface circuit (INT
1, 2) and a storage control circuit (CTLl, 2), respectively, and two sets of information holding circuits 1 capable of holding and controlling input/output information to the storage module sections 131 to 133 for a certain period of time.
00,10□.

Interface circuit 11. , IL, is the central processing unit 1
It consists of an address register for holding address information from the central processing unit 1, a data register for holding accumulated data from the central processing unit 1, and a data register for holding read data from the storage module section, etc. A connection line 14 branches between the register of each interface circuit 111.11□ and each storage module section, and an AND gate 31 in the storage module section 131.132.133 is connected.
, 33.35, and are branched from the connection line 15 to form a storage module section 13.35. , A within 132°133
They are connected to ND gates 32, 34, and 36, respectively.

The storage control circuits 120 and 12□ are composed of circuits that select storage module units based on address information from the central processing unit 1, and the outputs of these circuits are sent from the circuit 121 to connection lines as selection signals for the storage module units. 21
, 22.23 through the storage module section 131.132.
The AND gates 31, 33, and 35 in the memory module sections 130, 13□, and 133 are connected to the AND gates 31, 33, and 35 in the memory module sections 130, 13, and 133 from the circuit 122 through the connection lines 24, 25, and 26, respectively.
Connected to gates 32, 34, and 36, respectively.

FIG. 2 is an explanatory diagram of the operation of the embodiment of the present invention shown in FIG.

Figure a shows the memory access request from the central processing unit 1; The operating status is shown in the same figure C-■Usagi is the storage module section 131, 13□
.

133, respectively.

In the same figure, if the minimum access interval for information is T, then the memory cycle time of each storage module is 2.
It is assumed that memory access requests issued by the central processing unit occur every integer multiple of T.

Hereinafter, an example of the operation of the storage device according to the present invention will be described with reference to FIGS. 1 and 2 using abbreviations and numbers for simplicity.

(MEMl) 1' emitted from central processing unit 1
Access information for 31 is (lNT1') 11
．． (CTLl) 12. by (ME
AN via the connection line 21 by the selection signal of MI) 13.
D gate 31 is opened and (INTl)11. and (MEM
l) 131 is connected.

In this case (lNT1) 11° and (CTLl) 12
．． is occupied by (MEMl) 131 by a memory cycle time of (MEMl) 131.

For the next memory access request (INTl)
11, and (CTL)12□ is (MEMl)131
Since it is exclusively owned by (INT2) 11□, it is received by
M3) 133 is connected.

In this case (MEM3') only memory cycle time of 133 (lNT2) 112 and (CTL2) 12□
is exclusively occupied by (MEM3)133.

Similarly, subsequent memory access requests 0°[F],
For [F] and [F], (lNT1)111 and (lNT2)11□ are (MEMl)13. ~(ME
M3) 133, each storage module section 131~
133 is the interface circuit 111, 11□ and the memory control circuit 121, 12 for the memory cycle time.
□.

In this way, the memory of the storage module units 13, - 133
If a certain time relationship exists between the cycle time and the memory access request interval from the central processing unit 1, the number of storage modules can be reduced without installing an interface circuit and a storage control circuit for each storage module. By simply preparing a small number of common interface circuits and storage control circuits, each storage module unit can operate independently.

The output AND gate 37 is connected to the memory module section 13 . The interface circuit 11. controls information from the interface circuit 11. or 11□
connected to.

Similarly, the mountain gates 38 and 39 are controlled by the selection signals on the connection lines 22.25 and 23.26, respectively, so that the information of any one of the storage module sections 131 to 133 is sent back to the central processing unit 1. .

FIG. 3 is an explanatory diagram showing the configuration of another embodiment of the present invention.

In the figure, the storage device 2 includes multiple sets of storage module units (ME
MI~MEMN)13. ~13N and a plurality less than this number, for example 4 interface circuits (INT
I-INT4) 11□-114 and corresponding storage control circuits (CTL1-CTL4) 12. The information holding circuits 101 to 104 each include information holding circuits 101 to 124.

The structure and function of this storage device 2' are similar to those already described in FIGS. 1 and 2.

This embodiment further includes a configuration in which a plurality of sets of information holding circuits are connected to part or all of a plurality of central processing units.

That is, in the storage device 2 described above, the information holding circuit 1
Each interface circuit 111 to 114 of 0□ to 104
Of these, the interface circuit 11 and the interface circuit 114 are connected to only one of the central processing units 11 and 12, respectively, and the interface circuit 11□ and the interface circuit 113 are connected to both edges of the central processing units 11 and 12.

With such a configuration, two systems of the information processing system consisting of the central processing unit and the storage device of the present invention shown in FIG. Not only that, but the number of interface circuits in the overlapped portions has increased, so central processing units 1□, 1
The frequency of memory access can be increased by alternately accessing the memory in the 2 memory cells during normal operation.

Furthermore, as an advantage of the circuit of this embodiment, it can be particularly emphasized that a redundant backup circuit in an information processing system requiring a high reliability area can be implemented by partially overlapping these two systems.

FIG. 4 is an explanatory diagram of the operation of the embodiment of the present invention shown in FIG.

Figure a shows the central processing unit 1. ．． 12 shows the memory access request when accessing alternately as described above,
In accordance with this access request, the operating states of the interface circuits 111 to 114 and the corresponding storage control circuits 121 to 124 are determined by the circuit connections shown in FIG. 3, respectively.

■, [phase], shown in ■, storage module parts 131 to 13
The operating status of N is shown in C in the same figure, ■, ■, [phase], ■, ■,...
- Shown in [Phase].

In this case, the minimum access interval T. The memory cycle time 2T of each storage module section is as shown in FIG. 1, and since access requests from both central processing units are made alternately, the interval is T/2 as shown.

In this way, the interface circuit 11 shown in FIG.
Storage module unit 13 specified using □ to 114,
~13N can be selected.

All of the interface circuits 111 to 114 can be used during normal operation, but if one of these circuits fails, it is desirable to further provide a backup circuit (INT5) in order to continue processing as usual. but,
The related problem is the increase in hardware.

On the other hand, according to the method of this embodiment, as shown in Table 1 below, even if a failure occurs in either the interface circuit (INT) or the memory control circuit (CTL), the processing capacity will be slightly reduced. The lower the access frequency from the single-edged central processing unit, the more the processing capacity of either central processing unit can be maintained at the same level as during normal operation.

As explained above, according to the present invention, the number of information holding circuits including interface circuits and storage control circuits can be made smaller than the number of storage modules, and smooth memory access from the central processing unit is possible. The number of information holding circuits required can be reduced, and the objectives of miniaturization and cost reduction can be achieved.

Furthermore, by partially duplicating the two systems of the present invention including the central processing unit, access frequency can be increased during normal operation, and a redundant backup circuit that is effective in the event of a failure in one of the information holding circuits can be prepared. This has an extremely significant practical effect on information processing systems that require high reliability.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the embodiment of the present invention shown in FIG. 1, and FIG. 3 is a diagram showing the configuration of another embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation of the embodiment of the present invention shown in FIG. 3. In the figure, 1, 10, 12 are central processing units, 2, 2' are storage devices, and 101, 10□. 103.104 are information holding circuits, 111, 11□. 113 and 114 are interface circuits; 12. . 12□, 123.124 are storage control circuits; 13. . 13. 13..., 13N indicate the storage module section 3.

Claims (1)

[Scope of Claims] 1. It has a plurality of storage module sections that can operate independently and a plurality of information holding circuits that can hold input/output information to the storage module sections for a certain period of time, and In a memory accessible storage device, a plurality of sets of information holding circuits smaller than the number of storage module units are provided,
Each information holding circuit and each storage module section are made connectable under the same conditions, and the selected storage module section and any information holding circuit are connected for each memory access command information, and other information The holding circuit is
A storage device control type characterized in that it is kept on standby for access. 2. The storage device is accessible from a plurality of central processing units, each of the central processing units is connectable to part or all of the plurality of information holding circuits, and the central processing unit that issued the memory access command information is 2. A storage device control system according to claim 1, wherein the selected storage module unit is connected to any information holding circuit that can be used by the central processing unit.