JPS5839385B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory with a high degree of integration and a fast read/write speed.

Static induction transistor (hereinafter referred to as SIT).

) Dynamic RAM (Rand=o
Regarding mAccess MemoryK, special application was made in 1972.
No. 18465 “Semiconductor Memory”
3330), Japanese Patent Application No. 52-20653 "Semiconductor Memory Device" (Japanese Unexamined Patent Publication No. 53-105986), Japanese Patent Application No. 1983-105986
No. 35956 “Semiconductor Memory” (Japanese Patent Application Laid-Open No. 53-1203
40), Patent Application No. 52-36304 “Semiconductor Memory”
(Japanese Unexamined Patent Publication No. 57-32436).

RAM that can be written with light and can store images
This is described in detail in Japanese Patent Application No. 52-37905 "Semiconductor Memory" (Japanese Patent Publication No. 57-32437).

Regarding non-volatile memory, some of it was
No. 18465 “Semiconductor Memory” (Unexamined Japanese Patent Publication No. 53-103
No. 330), a patent application for the improved version of the original was filed in 1972-7235.
No. 2 "Semiconductor Memory" (Japanese Unexamined Patent Publication No. 54-15683) and Japanese Patent Application No. 52-83226 "Semiconductor Memory" (Japanese Unexamined Patent Publication No. 54-18284).

What is common to the memory cell structures of these semiconductor memories is that the memory cells are configured in a three-dimensional structure, such as by providing cells inside the semiconductor rather than on the semiconductor surface.
The reason is that the degree of integration is high.

At the same time, because it uses bulk conduction rather than surface conduction, one of its features is that it has high carrier mobility and faster writing and reading speeds.

Figure 1 shows a specific example of these semiconductor memories, where a is a plan view, 'b' is a cross-sectional view taken along line A-A' in figure a, and C is a cross-sectional view taken along line n-B' in figure a. It is a diagram.

Of the two main electrodes 11 and 13, which are n+ regions, 11 is a floating electrode surrounded by a p@ region 15.

Here, 11 is called a source and 13 is called a drain.

The p@ region 14 serves as the gate of a static induction transistor (SIT).

P region 15 is a substrate, 13' is an electrode metal connected to drain 13 and serves as a bit line, and 14' is a word line connected to gate 14.

15' is a contact electrode of the substrate, 16 is S i 02yS i
It is an insulating layer such as 3N4, Al2O3, or a composite insulating layer combining a plurality of these, and 17 is an insulating layer of these or an insulating resin such as polyimide.

The configuration is such that SITs with leases serving as floating electrodes are arranged at each intersection of word lines and bit lines.

The impurity density of each region is 11 from 1017 to 1021Cr
IL-3 degree, 12 is 101°, 1016CIIL-
About 3, 13 changes by about 1018-1021CrrL-3,
14 is about 10"~10"art', 15 is about 10
It is about 14-1O18cIrL-3.

The width of the channel portion quadrupled with the gate 14 is the n-region 12.
It is determined by the impurity density of , and is set so that the channel is completely pinch-on and in a cut-off state only by the diffusion potential between the gate and channel region.

Of course, even if charge is accumulated in the source region 11, which is also a storage capacitor, and the potential rises to a certain level, electrons will not flow from the drain 13 toward the source 11 unless a readout voltage is applied from the outside. The dimensions and impurity density must be chosen such that a degree of potential barrier is created in the channel.

For example, if the impurity density in the n-region is 1 × 10 cm
, lXl0"crrL', and lXl0 cm, the channel widths are selected to be appropriate values of 20μ, 6μ, and 2μ or less, respectively.

When data is stored in memory cells,
This does not apply in the case of an operation in which a reverse voltage is applied to the gate and the voltage is set to O voltage during reading and writing, for example.

The shorter the distance between the source and the drain, the shorter the travel time of electrons during writing and reading, which is desirable.

For example, it is about 0.5 to 1.5μ. Figure 1 a, b
, c can be expressed as shown in FIG. 1f.

18 is a storage capacity.

In Figures 1a, b, and e, the storage capacitance is the area 11 and the substrate 15.
It consists of the junction capacitance between .

When writing data, a predetermined positive voltage is applied to the bit line 13'.

At the same time, a positive voltage is applied to the gate (word line) to lower the height of the potential barrier created in the channel, so that electrons flow from the source region 11 to the drain.

As the electrons flow out, the source 11 becomes positively charged and the potential becomes positive and high. When the write voltage and the source potential are balanced, the flow of electrons stops, and when the write voltage is removed, the charged state of the source region 11 changes. 11 are retained.

There are two types of write addressing depending on the configuration of the channel section.

If the channel width is narrow and the impurity density is set low enough to create a sufficiently high potential barrier in the channel (a), simply applying a positive voltage to the bit line will not raise the potential barrier sufficiently. Therefore, when a voltage is applied to the bit line to the gate of the memory cell to be written, a forward voltage is simultaneously applied to the word line to lower the potential barrier and write is performed.

In this case, data is not written to memory cells to which no voltage is applied to the word line.

It goes without saying that the signal to be written to the word line should be suppressed to a voltage at which minority carrier injection from the gate can be almost ignored.

If the channel section is in such a state that applying a positive voltage to the bit line is enough to cause electrons to flow out from the source (b), write a word to the gate of the memory cell to which data is not written. It is sufficient to apply a reverse voltage through the wire.

In the case of (a), data can be read by applying a forward voltage (positive voltage in this example) to the word line, or by returning it to the O voltage if it was biased in the reverse direction, from the drain 13 to a positive potential. Electrons flow into the source 11 in the state, and whether or not data is accumulated is detected based on the presence or absence of current at that time.

In other words, since the channel is opened and conduction occurs between the source and drain, the potential of the source region is read out to the outside.

In the structure of FIG. 1 btc, when electrons flow out from the source region 11 and the potential of the source region increases, the source region 1
The depletion layer extending from 1 to the substrate 15 side gradually expands, the storage capacitance C decreases, and the potential Q/C with respect to the amount of charge Q charged in the source region suddenly increases.

If such a change in potential is undesirable, a high resistance region 11 is formed between the source region 11 and the substrate 15, as shown in FIG. 1d.
Just insert 9.

In this example, the high resistance region 19 is a single layer of P, but n
The impurity density and thickness are selected such that the diffusion potential of the source region 11 and the substrate 15 forms a depletion layer.

In this way, the storage capacitance C is independent of the potential of the source region.
is kept constant, and for the charge Q flowing out from the source,
The source potential is simply given by Q/C.

Of course, it is also effective to provide an impurity distribution between the source region 11 and the substrate 15 so as to cause a desired potential change with respect to the amount of charge flowing out from the source.

In FIG. 1d, an isolation n region 20 is provided between the gates of each memory cell.

This is to prevent punch-through current from flowing between the gates of adjacent memory cells.If punch-through current flows between the gates of adjacent memory cells, this isolation region 20 Just insert .

A memory cell with much the same operation as described above can also be constructed with bipolar transistors in which the pace is mostly or completely punch-through.

An example thereof is shown in FIG. 1e.

It has already been shown in Japanese Patent Application No. 52-15879 "Semiconductor Device and Semiconductor Integrated Circuit" (Japanese Unexamined Patent Publication No. 53-100783) that a bipolar transistor whose base is almost in a punch-through state operates in a manner similar to an SIT. Special request 1972
-17327 “Semiconductor integrated circuit”
420).

When the impurity density of the P- region 14' is sufficiently low and its thickness is sufficiently thin, the operation will be as in the case described above, and when the impurity density of the P- region is high or thick, the operation as described above will occur. This is the operation in case (a).

In the embodiment shown in FIG. 1, consideration must be given to prevent punch-through current from flowing between the substrate and the gate, and to ensure that the charges accumulated in the source region are retained for a sufficiently long time. A limitation exists in that a higher potential can be applied to each region.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that overcomes these drawbacks and enables high-speed writing and reading by applying a desired potential to each region.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 shows a specific example of the present invention.

Figure 2 a is a plan view, Figure 2 is a sectional view taken along line AA', Figure 2 C is a sectional view taken along line BB', Figure 2 d
is another cross-sectional structure of the memory cell of the present invention.

Figure 2. As is clear from the cross-sectional view at C, each memory cell is separated by an insulator region 21 such as 5i02.

By introducing the isolation insulator region 21, no punch-through current flows between the gates of adjacent memory cells and between the gate 14 and the substrate 15.

At the same time, the gate capacitance is reduced, and the word line capacitance is also reduced, further increasing speed.

The gates of each memory cell are connected by a wiring 14' made of metal such as AA or Mo or low resistance polysilicon to form a word line.

The write, store, and read operations and the impurity density dimensions of each region are almost the same as described with respect to FIG.

A storage capacitor is formed between the floating region 11 and the substrate 15.

The dimensions of the floating region and the impurity density of the substrate are selected such that the storage capacitance is the desired value, for example 0.18 pF.

It is also effective to interpose a high resistance layer between the substrate and the floating region as shown in FIG. 1d.

In order to achieve a capacitance of 0.18 pF when the write voltage is, for example, IOV in a memory cell of about 20 μm square, the impurity density of the substrate should be about I x 1017t, x-3.

If the capacitance of the bit line can be further reduced, the value of the storage capacitance of the memory cell can also be further reduced, and the value of the floating region can also be reduced.

For example, by increasing the thickness of the insulating layer 16,
If the bit line capacitance is halved, the area of the floating region will be halved.

Fig. 2d shows another specific example of the present invention, in which the area between the two main electrodes 11 and 13 was composed of a double head region and a high resistance head region of the same conductivity type, but a high resistance head region of the opposite conductivity type. This is an example composed of a resistance region.

The base region 14' operates in a substantially or completely punch-through condition.

The operation is almost the same as that of the bpcO shown in FIG.

The embodiment shown in FIG. 2 shows a specific example of the semiconductor memory of the present invention, and is not limited to these! not.

Even a device with a structure in which one conductivity type is reversed will operate in the same way if the polarity of the applied voltage is reversed.

In addition, although all gates are shown as junction type, gates are not limited to junction type, and include Schottky type, MOS-MI type, etc.
Any material that exhibits rectification properties such as S type may be used.

Further, as a specific example, although the semiconductor memory of the present invention has been mainly explained using SIT, field effect transistor J (FET
) is of course a good thing.

Two main electrodes are configured three-dimensionally, one of which is a floating region inside the semiconductor, and the outflow and inflow of carriers between the two main electrodes is controlled by a gate electrode, that is, a control electrode, and each memory cell Any material may be used as long as it is separated by an insulator.

Although the structure of the channel is limited to a rectangular one, it may be of any shape such as circular, elliptical, or striped.

In addition, although only the gate that completely surrounds the channel is shown, the gate may be divided into multiple gates and the desired gate among them may be connected to the lead wire as a drive gate, or the gate may be of medium size. A medium-sized gate formed at the center of the channel may be connected to the word line as a drive gate.

The structure of the specific example of the present invention can be easily manufactured by making full use of conventionally known techniques such as selective growth, selective diffusion, ion implantation, microfabrication, selective etching, plasma etching, sputtering, thermal oxidation, and CVD. can.

The semiconductor memory of the present invention uses bulk conduction and moves carriers using an electric field, resulting in faster write and read speeds.The semiconductor memory of the present invention has a three-dimensional structure, allowing for large capacity, and each memory cell is separated by an insulator. Because of this, there are no restrictions on the selection of operating potentials, word line capacitance and bit line capacitance are reduced, and extremely high-speed operation can be performed, and its industrial value is extremely high.

[Brief explanation of the drawing]

Figure 1 a to f are conventional SIT memories, Figure 2 a to d
is a semiconductor memory of the present invention.

Claims (1)

[Claims] 1. Two main electrodes made of high impurity density regions of the same conductivity type are provided on the surface and inside of the semiconductor, respectively, substantially perpendicular to the semiconductor surface, and the main electrode provided inside the semiconductor is used as a floating electrode. None, a potential barrier existing between the two electrodes is to be controlled by a control electrode, an isolation insulator region is provided between the memory cells configured to control the inflow and outflow of carriers through the floating electrode, and the control electrode A semiconductor memory comprising the memory cell at at least a part of the intersection point of a matrix consisting of word column lines and matrix lines of bit row lines connected to main electrodes provided on the surface. . 2. A patented semiconductor memory characterized in that a gate surrounding a channel is divided into at least two parts, the divided gate is used as a drive gate, and the drive gate is used as a word line. 3 One of the two main electrodes consisting of a high impurity density region of the same conductivity type arranged in a direction substantially perpendicular to the semiconductor surface is used as a floating electrode, and a high resistance of the same conductivity type as the main electrode is connected between the two electrodes. 3. The semiconductor memory according to claim 1, wherein the third electrode is a junction type, Schottky type, or MIS type electrode. 4 One of two main electrodes consisting of high impurity density regions of the same conductivity type arranged in a direction substantially perpendicular to the semiconductor surface is used as a floating electrode, and a high resistance region of a conductivity type opposite to that of the main electrode is provided between the two electrodes. 3. The semiconductor memory according to claim 1, wherein the third electrode is a high impurity density region of the same conductivity type as the high resistance region of the opposite conductivity type.