JPS5838871B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides I2L (Integrated Injec
The present invention relates to an improvement of a semiconductor integrated circuit device having an array of memory cells constructed using tionLogic.

At present, memory cells constructed from 2L are regarded as revolutionary because of their high integration.

Figure 1 is an equivalent circuit diagram representing one bit of a memory cell configured with 2L, where Ql to Q6 are transistors, W+ is a + side word line, W- is a - side word line, Bo, Bo
indicates a bit line.

When the memory cell in Figure 1 is integrated and viewed in cross-section, the second
It is as shown in the figure, and when viewed in plan, it is as shown in Fig. 3.

In FIG. 2, parts corresponding to those explained in FIG. 1 are given the same symbols.

Further, in FIG. 3, the same symbols are attached to parts corresponding to the P and N regions in FIG. 2.

In FIG. 2, the p-type conductive region to which the word line W+ is connected is the injector, and as can be seen in comparison with FIG. 1, the lateral force direction pnp transistor Q1. Acts as a common emitter for Q2.

And this transistor Q1. By making active use of Q2 as a load and the reverse operation of the npn transistor Qs-Q4, that is, operating the collector of the normal operation as the emitter and the emitter as the collector, the p-type transistors Ql, Q2 and npn h transistor Q3. This allows the bulk, which is the common n-type conductive region of Q4, to be used as a so-called underbridge word line W-.

The word line W-, which is the bulk thereof, is not shown in the plan view of FIG.

Further, as shown by the narrow hatched area s1 in FIG. 3, a shallow isolation between cells is sufficient to prevent parasitic PNP.

The above is the reason why the 2L type cell is distantly related to higher density than the conventional cell.

Note that the wide hatched area ■8□ in FIG. 3 is a separation area between the cell arrays.

However, as shown in the equivalent circuit of the cell array in Figure 4, when a cell array is constructed using the cells in Figure 1, the conventional cell array
Compared to the array, the parasitic resistance valve (bulk resistance) rO and capacitance (junction capacitance between the word line W- and the substrate) co parasitic to the word line W- made of the bulk are large, and the characteristics of the RAM made of this cell array are This has the negative effects described below.

FIG. 5 shows a main circuit when a RAM is constructed using the cells shown in FIG. 1.

In FIG. 5, Q A yQB is a word line driving transistor, and □ is a current source for supplying a holding current to the cell.

The cell contents are held by storage transistors Q3 and Q4.
This is done by turning one side on and the other off.

To write the contents of the cell, a write current is applied to either one of the bit lines BφB1 to determine the contents of the cell.

For example, when Q3 is on and Q4 is off, by flowing a write current to the bit line Bφ, the cell contents are inverted so that Q3 is off and Q4 is on.

Note that the threshold value of the write current is indicated by the word line W+ in FIGS. 2 and 3.
Since the write current is proportional to the injector current flowing to the P1 region, and the write current is also shunted to other non-selected cells to become the injector current, the write current is determined taking such points into consideration.

Next, the cell contents are read through a pair of bit lines Bφ.

When a read current ■□ is applied to Q3.B1, the memory cell storage transistor Q3. According to the on/off state of Q, the bit line Bφ? Since the voltage values appearing on B1 are different, the potential difference is detected by the sense amplifier SA.

For example, if transistor Q3 is now on and Q4 is off,
The potential of bit line BφjB1 is transistor Qs = Q
Since the bit line Bφ is determined by the base potential of 4, the bit line Bφ has a high potential and the potential FB has a low potential.

By the way, in the I2L memory cell, as shown in FIG. 1, the load of the memory cell is PNP h transistor Q1. Q
2, and when the load is viewed from the cross-coupled transistors Q3jQ4, it appears as a nearly constant current source, so the transistors Q3. All base potentials of Q4 are determined predominantly from the word line W-.

Therefore, the potential difference between the bit lines Bφl and B during reading is the same as that of the storage transistor Q3. Determined by Q4 on/off,
Also, the transistor Q3 which determines whether it is on or off. Q4
The base potential of is determined by the word line W-.

For this reason, a particular problem arises when the word line W- of a certain cell array changes from a selected state to a non-selected state.

At the time of falling, the electric charge of the parasitic capacitance C6 of the word line W- is discharged by the holding current □ through the parasitic resistor ro, so its falling characteristic deteriorates, and the recovery of the bit line BφtB follows. Become slow.

This means that if the content of the cell to be read is opposite to the content of the previously read cell, the content of the previous cell is
, B1 becomes longer, which means that the read time (access time) becomes slower.

The time chart in FIG. 6 shows the situation.

(1) is the base potential of the word line driving transistors QA and QB in FIG. 5, and (2) is the word line W of the cell arrays A and B.
-2WB-, (3) is the bit line Bφ, B
1, respectively.

First, assume that the base potential of transistor QA is at a high potential level and one of the memory cells in cell array A is selected and its contents are read out.

Assume that at time T1, the base potential of transistor QA changes to a low potential level, and the base potential of transistor QB changes to a high potential level, and memory cell CeB of cell array B is selected.

Furthermore, assume that the contents of memory cells CeA and CeB are different.

In such a case, the potential of the word line WA- falls because cell array A changes from the selected state to the non-selected state, but as mentioned above, this characteristic is accumulated in the parasitic capacitance of the word line WA-. Due to the discharge of charge, the rate becomes slow as shown in FIG.

Following this, the characteristics of the bit lines Bφ and B1 (in this example, the falling of B1) also become slower.

Actual reading is performed at a point where the response potential difference between the bit lines Bφ and B1 is Δ■8 or more, so the read time (access time) in FIG. 6 is t.

The same holds true at time T2. This read time t
1, it is sufficient to shorten the time for discharging the word line WA-, and for that purpose, the holding current ■□ may be increased.

However, simply increasing the holding current ■□ will supply more holding current than necessary to the majority of unselected cells, resulting in an increase in wasted current.

This becomes a problem that cannot be ignored as the capacity of the RAM increases.

Another negative effect of the slow response of the word line W- is that there is a risk of erroneous writing.

That is, the storage transistor Q3. of the memory cell after changing from selected to non-selected. If the base potential of Q4 responds slowly following the falling characteristics of the word line W-, if the write current is supplied to the bit line before the potential has fallen sufficiently, it will become unselected. The write current Iw is also shunted to the memory cell that should have been written, creating the risk of erroneous writing.

■In the case of a 2L cell, current is passed through the ON side of the storage transistors Q3 and tQ4 to reverse the state, so the falling characteristics of the base potentials of transistors Qa and Q4, that is, the falling characteristics of the word line W-, are Error writing is also an important factor.

As explained above, in the conventional RAM using a 2L mesori cell array, the falling characteristic of the word line W- is slow, so the read time (access time) becomes slow.
There was a drawback that there was a risk of error writing.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, improve the falling characteristics of the word line W-, and provide a circuit for high-speed reading and error writing prevention in an array of 2L memory cells.

In a semiconductor memory device in which a plurality of 2L memory cells are connected by negative word lines made of semiconductor crystal to form an array, and a plurality of such arrays are provided, and the 2L memory cells are arranged in a matrix, This is achieved by providing a semiconductor memory device characterized in that discharge paths for discharging the charge of the negative word line when the line changes from selected to non-selected are distributed in the array.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIGS. 7, 8, and 9 show circuit diagrams in which word line discharge paths are connected to the word line W- in a plurality of distributed locations.

In FIG. 7, each word line discharge path is composed of a diode D, and in FIG. 8, the resistor r1100 is composed of a diode D and a resistor r, respectively.

One ends of these word line discharge paths are all connected to one discharge current source.

Therefore, in the steady state, current 9 flows to the word line W- of the selected cell array having the highest potential.

The current ■ゎ contributes as a discharge current because the cell
This is in a transient state where the array goes from a selected state to a non-selected state.

At this time, conversely, the current 9 is also shunted to the word line W- of the cell array which changes from a non-selected state to a selected state.

The operation at that time will be specifically explained with reference to the time chart shown in FIG.

As a specific example, the example used in the description of the conventional example will be used.

At time T1, the selected cell array moves from cell array A to cell array B, and at that time (
As shown in 4), a branch of the current {circle around (2)} moves from the word line W- to the word line WB-D A .

However, in this transient state, a word line discharge path is provided so that one current branch is delayed by a predetermined time.

Therefore, even after the cell array A changes from the selected state to the non-selected state at time T7, the current 1 is shunted to the word line W-, and the charge accumulated in the parasitic DA capacitance of the word line WA- is is discharged, so that the word line WA
The falling time of - is shortened as shown in FIG. 6 (5).

Then, as shown in (6), the bit line Bφ
Alternatively, the B1 fall time is also shortened, and the read time (access time) t2 becomes longer.

Naturally, the risk of error writing is also reduced.

In the case of reading, after time T1 to t2, bit lines Bφ and B1
When the potential difference between the voltage and the voltage becomes Δv4, the contents of the memory cell are detected by the sense amplifier.

Therefore, the word line discharge path must be designed such that the switching of the current 2 shunt occurs after the above-mentioned detection has taken place.

When the word line discharge path consists of a diode D as shown in FIG. 7, the above-mentioned current ■.

Since the switching gain of the shunt current is large and switches rapidly, there is a risk that the discharge current will stop flowing to the word line W- of the cell array that has become unselected before readout is detected. .

On the other hand, if the word line discharge path consists of a resistor r as shown in Figure 8, by appropriately selecting the resistance value and current ID, the current flowing through the resistor r of the cell array in the non-selected state will not flow backwards. If , the discharge current ゎ will continue to be shunted even after non-selection.

Moreover, the time constant of the fall of the word line W- is determined by the accumulation of the parasitic capacitance of the word line W- and the resistance value of the word line discharge path.

Therefore, the resistor r in FIG. 8 has a higher current ■ than the diode D in FIG.

The duration of the discharge effect is long, and the discharge effect continues until the word line W- reaches a sufficiently low level.

However, the resistance r and the current ■. Depending on the setting of , there is a risk that the current flowing through the resistor r flows backward into the word line W- of the cell array after non-selection, canceling out the holding current ■□ flowing through the word line W.

Therefore, if the word line discharge path is configured with a diode D and a resistor r connected in series as shown in Figure 9, the resistor r will delay the switching of the discharge current, and the diode D will prevent the discharge current from flowing backwards. be able to.

In the embodiment shown in FIG. 9, it is undeniable that the degree of integration is sacrificed compared to the embodiments shown in FIGS. 7 and 8.

Therefore, which of the three embodiments to implement is determined by the characteristics of the target RAM while taking into account the degree of integration.

When a cell array connected with word line discharge paths as described above is actually patterned, it becomes as shown in FIG. 10.

The shaded areas in FIG. 10 are the word line discharge paths, which are distributed at three locations.

However, it is known that when a word line discharge path is arranged between memory cells m and m+1 as shown in FIG. 10, a discontinuous portion occurs between both memory cells, resulting in non-uniform write characteristics.

This causes the concentration of injector current in memory cells m and m+1 during writing due to the parasitic resistance of the word line W- in the discontinuous part.
This results in a write pulse width that is short compared to other memory cells.

This phenomenon is most noticeable in memory cells 1 and n located at the ends of the cell array.

As a countermeasure to this problem, in Japanese Patent Application No. 53-56007 filed by Fujitsu Corporation and Nippon Telegraph and Telephone Public Corporation, it is proposed that each memory cell and a special dummy cell, which does not have a memory function, be placed at the end of the cell array. Methods have been proposed to alleviate the discontinuities.

Therefore, when actually providing a word line discharge path in a cell array,
If the above-mentioned dummy cell is also provided, the above-mentioned phenomenon can be prevented.

Specific examples thereof are shown in FIGS. 11, 12, and 13.

In both cases, a is an equivalent circuit and b is an integrated plan view.

Each dummy cell DCe has the same structure, and the dummy cell DCe, which is equivalent to the memory cell in FIG. Q6 and one of the storage transistors Q3 and Q4 is unnecessary, so in FIGS. Q2. It consists of Q3.

Each word line discharge path is connected to a diode D in FIG.
The region n5 in figure b. P4, in Fig. 12 it consists of a resistor r, and in Fig. b it consists of an area P4,
In FIG. 13, it is composed of a diode D and a resistor r, and is constituted by a region n5 y P4 +P in FIG. b.

Note that one end of each word line discharge path is connected to region n4 and automatically connected to the bulk word line W-.

As explained above, according to the present invention, 2L memory cells are connected by word lines W- made of semiconductor crystal to form an array. By providing a discharge path in the word line of the semiconductor memory device, the response of the falling characteristic of the word line W- can be shortened, and high-speed reading and error writing can be prevented.

In addition, by providing a dummy cell in the area where the discharge path is provided, the memory cells placed adjacent to the discharge path can be selected and the flowing write current can be shunted, reducing non-uniform write characteristics. It can be prevented.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of a memory cell configured on I2. FIG. 2 is a sectional view when the memory cells of FIG. 1 are integrated, and FIG. 3 is a plan view thereof. Figure 4 is an equivalent circuit diagram of the cell array. FIG. 5 is a circuit diagram of the main part of RAM. FIG. 6 is a time chart for explaining the operation of the RAM. FIG. 7, FIG. 8, and FIG. 9 show a RAM which is an embodiment of the present invention.
Main part circuit diagram. FIG. 10 is a schematic diagram of a cell array according to an embodiment of the present invention. FIG. 11, FIG. 12, and FIG. 13 are an equivalent circuit diagram and a plan view of a word line discharge path according to an embodiment of the present invention. In the figure, Q1 to Q6. QA, QB are transistors, W+,
W, WA+, WA-, WB+, WB- are word lines, Bφ
, B1 is the bit line, IH is the holding current, Iw is the write current, IR is the read current, ID is the discharge current, and DCe is the dummy current.
It is a cell.

Claims (1)

[Claims] 1. A semiconductor memory device in which a plurality of I2L memory cells are connected by negative word lines made of semiconductor crystal to form an array, a plurality of the arrays are provided, and the I2L memory cells are arranged in a matrix. , a semiconductor memory device characterized in that discharge paths for discharging charges of the negative word line when the negative word line changes from selected to non-selected are distributed in the array. 2. The semiconductor memory device according to claim 1, wherein one end of the discharge path is connected to a current source, and the other end is commonly connected to the array. 3. The semiconductor memory device according to claim 1, wherein the discharge path provided in the array is provided with a dummy cell similar to the 2L memory cell.