JPS583682U - Clamp pulse shaping circuit - Google Patents
Clamp pulse shaping circuitInfo
- Publication number
- JPS583682U JPS583682U JP9609781U JP9609781U JPS583682U JP S583682 U JPS583682 U JP S583682U JP 9609781 U JP9609781 U JP 9609781U JP 9609781 U JP9609781 U JP 9609781U JP S583682 U JPS583682 U JP S583682U
- Authority
- JP
- Japan
- Prior art keywords
- shaping circuit
- pulse shaping
- transistor
- clamp pulse
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Picture Signal Circuits (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１薗は従来のクランプパルス成形回路を示す回路図、
第２図は第１図の動作を説明するための各部の波形図、
第３図は本考案の一実施例を示す回路図、第４図は第３
図の動作を説明するための各部の波形図である。
２・・・・・・入力端、３・・・・・・ゲートパルス成
形回路、４・・・・・・クランプ回路、５・・・・・・
位相検波回路、６・・・・・・クランプパルス成形回路
、Ｑ、乃至Ｑ９・・・・・・トランジスタ、Ａ′・・・
・・・出力端。The first section is a circuit diagram showing a conventional clamp pulse shaping circuit,
Figure 2 is a waveform diagram of each part to explain the operation of Figure 1.
Fig. 3 is a circuit diagram showing one embodiment of the present invention, and Fig. 4 is a circuit diagram showing an embodiment of the present invention.
FIG. 4 is a waveform diagram of each part for explaining the operation of the figure. 2...Input end, 3...Gate pulse shaping circuit, 4...Clamp circuit, 5...
Phase detection circuit, 6... Clamp pulse shaping circuit, Q to Q9... Transistor, A'...
...output end.
Claims (3)
具備し、第１トランジスタのベースにバイアスを印加し
、負荷を接続して出力端とした第２トランジスタのべ一
刈ト信号を印加して波形成形された出力を取り出すよう
に構成されたクランプパルス成形回路において、前記第
２トランジスタのベースあるいは出力端に第１及び第２
のクランプ用の手段の少なくとも一方を設け、出力電圧
のローレベル側及びハイレベル側の少なくとも一方をク
ランプすることを特徴とするクランプパルス成形回路。(1) Equipped with first and second transistors that are connected differentially, a bias is applied to the base of the first transistor, a load is connected, and a signal is output from the second transistor, which is used as an output terminal. In the clamp pulse shaping circuit configured to take out a waveform-shaped output by applying a pulse, the first and second transistors are connected to the base or output terminal of the second transistor.
1. A clamp pulse shaping circuit comprising at least one of clamping means for clamping at least one of a low level side and a high level side of an output voltage.
ンジスタのコレクタを電源端に、そのベースを電源端ｉ
を抵抗で分割した分割点に、そのエミッタを抵抗を介し
て接地すると共に抵抗を介して前記第２トランジスタの
ベースに接続されて構成され之ことを特徴とする゛実用
新案登録請求の範囲第１項記載のクランプパルス成形回
路。(2) The first clamping means has the collector of the NPN transistor connected to the power source end, and the base connected to the power source end i.
The emitter is grounded via a resistor at a dividing point divided by a resistor and connected to the base of the second transistor via a resistor. Clamp pulse shaping circuit described in section.
ジスタのコレクタを電源端に、そのベースを電源端電圧
を抵抗で分割した分割点に、その □エミッタを前
記第一２トランジスタの出力端に接続されて構成される
ことを特徴とする実用新案登録請求の範囲第１項記載の
クランプパルス成形回路。 −(3) The second clamping means connects the collector of the NPN transistor to the power supply terminal, its base to the dividing point where the power supply terminal voltage is divided by a resistor, and its emitter to the output terminal of the first second transistor. 2. The clamp pulse shaping circuit according to claim 1, wherein the clamp pulse shaping circuit is connected to the circuit. −
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9609781U JPS583682U (en) | 1981-06-30 | 1981-06-30 | Clamp pulse shaping circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9609781U JPS583682U (en) | 1981-06-30 | 1981-06-30 | Clamp pulse shaping circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS583682U true JPS583682U (en) | 1983-01-11 |
Family
ID=29890978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9609781U Pending JPS583682U (en) | 1981-06-30 | 1981-06-30 | Clamp pulse shaping circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583682U (en) |
-
1981
- 1981-06-30 JP JP9609781U patent/JPS583682U/en active Pending
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