JPS5836541B2 - Denki Kairosouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electrical circuit means for detecting an input signal having a frequency within a predetermined frequency band.

According to this invention, in the electric circuit means for detecting an input signal having a frequency within a predetermined frequency band, the first and second sampling means each have an input terminal connected to an input signal source and a switching input terminal; , oscillating means having a control input terminal and first and second output means and adapted in use to generate the first and second switching signals;
The first and second output means of the oscillation means are respectively
and means for coupling a control signal to a control input terminal of the oscillating means, whereby the switching signal is coupled to a switching input terminal of each of the first and second sampling means. and a second sampling period,
An input signal is applied and operated, the frequency of the first sampling period has a set relationship with the frequency of the required band, and when the first sampling means is adapted during operation, the frequency of the required band is set. configured to generate a control signal indicative of a difference between said frequency within a desired band and an input signal frequency and/or a departure from a predetermined phase relationship between a first sampling period and an input signal; When a control signal representing an input signal having a signal is applied to the oscillating means, the first switching signal is changed to cause the first sampling period to have a predetermined frequency and phase relationship with the input signal, and the external force,
The second switching signal changes to cause the second sampling period to have another frequency and phase relationship with the input signal, and the second sampling period has the other frequency and phase relationship with the input signal, and the second sampling period has the other frequency and phase relationship with the input signal. Electric circuit means are obtained, characterized in that when the magnitude of the signal exceeds a predetermined value, said second sampling means are adapted to generate an output signal representing the detection of the input signal.

The frequency of the first sampling period is initially equal to twice said frequency within the predetermined band, but the frequency is increased to the extent that the upper and lower frequencies are respectively equal to twice the upper and lower frequencies within the set band. Preferably, it is variable.

Also, when the frequency of the first sampling period changes to a value equal to twice the input signal frequency, each first sampling period extends into a time period centered at or near the time when the polarity of the input signal changes. .

Preferably, the first sampling period is equal to twice the time between consecutive first sampling periods.

Furthermore, the second sampling period is also variable in a band, initially having a frequency equal to twice said frequency within a predetermined band, and having upper and lower frequencies equal to twice the upper and lower frequencies of that band. It is preferable that you can.

Preferably, each second sampling period spans twice the time period between successive second sampling periods.

The frequency of the second sampling period is 2 times the input signal frequency.
Suitably, each second sampling period begins and ends within a half cycle of the input signal when varied by a factor of two.

Preferably, the second sampling period occurs at a time when the polarity of the input signal changes.

This will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The electrical circuit of FIG. 1 is a device for detecting input signals within a predetermined narrow frequency band.

Note that the input signal is an alternating current signal whose polarity changes between positive and negative.

The device is designed to be insensitive to high levels of out-of-band noise and other signals, particularly harmonics of the set frequency.

This electric circuit consists of an oscillation circuit 1 and two sampling circuits 3.
and 5, and each of the sampling circuits 3 and 5 is configured to operate in response to a switching signal extracted from the oscillation circuit 1.

An input signal whose frequency is unknown is first applied to the first sampling circuit of the two sampling circuits, that is, the oscillator sampling circuit 3, and if the frequency of the input signal is within a set frequency band, a control voltage is generated.

A control voltage is applied to the oscillator 1 to maintain the frequency of the switching signal at a frequency that is a multiple of the input signal frequency, or
Change up to that frequency.

A further switching signal, generated at a frequency equal to a multiple of the input signal frequency, is fed to a second sampling circuit, word sampling circuit 5, which also receives the input signal.

This word sampling circuit 5 is an input signal in which the switching signal is locked in frequency and phase,
In the case of an input signal having an amplitude greater than or equal to a preset threshold, an output signal representing the detection result is provided.

Referring to FIG. 1, the oscillator sampling circuit 3 includes instantaneous capacitors C2A and C2B, and each capacitor C2
It includes MOS switching transistors TR2A and TR2B coupled with A and C2B.

Each capacitor C2A, C2B is grounded and each transistor T
It is connected between the source electrodes of R2A and TR2B.

The drain electrode of each transistor is connected to a resistor RV of the sampling circuit 3, and the resistor RV is connected in turn to an input signal source via a bias circuit 7 and an input capacitor CIN, which will be described below.

The connection point between each capacitor C2A, C2B and each transistor TR2A, TR2B connected to it is a differential amplifier A1.
is connected to the input terminal of

The output terminal of amplifier A1 is connected to the control terminal of oscillation circuit 1.

The oscillation circuit 1 consists of a voltage controlled oscillator VCO 1 dividing circuit D and a gate circuit G.

The oscillator VCO is a free-running oscillator that oscillates at a frequency determined by the ramp voltage generated within the oscillator.

Here, for convenience of explanation, the frequency of an input signal that provides a control voltage that causes the oscillator VCO to perform free-running oscillation will be referred to as a reference frequency.

This oscillation frequency can be varied by changing the magnitude of the lamp voltage using a control voltage applied from the differential amplifier A1 to the oscillation circuit.

Changes in the oscillation frequency are limited to upper and lower frequency bands that are six times the upper and lower frequency limits of a predetermined frequency band.

Divider circuit D has an input terminal coupled to the output of oscillator VOO and six output terminals.

When vibration is applied from the oscillator VOO, the dividing circuit D generates a pulse train.

Each pulse in the pulse train has a duration equal to the oscillation period of the oscillator VOO, the next pulse occupies the next time domain,
Appears at the next output terminal of circuit D.

The pulses from the dividing circuit D are applied to a gate circuit G which provides two trains of switching pulses at its output.

Among the two columns of switching pulses, the pulse φ2A in the first column
and φ2B appear alternately at the first phantom output terminal of the gate circuit G.

These output terminals are connected to transistors TR2A and TR2B.
are connected to each gate.

Similarly, pulses φ3A and φ3B of the second series of switching pulses
appear alternately at the second phantom output terminal of the gate circuit G.

These output terminals are connected to a word sampling circuit as described below.

Word sampling circuit 5 includes a pair of capacitors C3A and C3B coupled to each switching transistor TR3A and TR3B, respectively.

As with the capacitors in the oscillator sampling circuit 3, each capacitor C3A, C3B is connected between ground and the source electrode of the transistor 'l'R3A, TR3B.

The drain electrodes of transistors TR3A and TR3B are connected to resistor RW, the above-mentioned bias circuit 7 and input capacitor C.
is coupled to the unknown signal source via IN.

The gate electrodes of the transistors TR3A and TR3B are respectively connected to the second output terminal of the gate circuit G.

In the word sampling circuit 5, each capacitor C3
The connection points between A and C3B and transistors TR3A and TR3B are connected to respective input terminals of voltage comparator C.

If the voltage difference at each input terminal of comparator C exceeds a preset threshold and has a predetermined sign, the output of comparator C will change from the 10'' condition to
Switched to I' state.

In practice, comparator C has two operating thresholds.

First, the turn-on operation threshold causes the output to switch to the III' state when the differential input voltage reaches this threshold.

When this "1'l" state is reached, the threshold value is reduced to half of its previous value.

This provides equal turn-on and turn-off times when the human power is in the form of a burst signal.

The output of comparator C is connected to the data input terminal of a word counter WC of the type disclosed in GB 1279611.

This counter WC has a second input terminal to which the clock pulse φ1 from the fifth output terminal of the gate circuit G is applied, and an output terminal connected to a switch provided at the output terminal of the device via the drive circuit DC. It has

The bias circuit 7 comprises a differential amplifier A2 having a first input terminal connected directly to the output terminal in order to provide 100% negative feedback and obtain uniform gain throughout.

The output terminal of the differential amplifier A2 is connected to the terminals of the resistors RV and RW on the side remote from the capacitors C2A and C3A.

The second input terminal of the differential amplifier A2 in the bias circuit 7 is connected to the capacitor CIN and also to the midpoint of a resistor network (not shown) via a high resistance bias resistor RB.

This resistor network is connected between the negative terminal of the DC power supply and ground.

When using this device, the bias circuit 7 presents a high input impedance to the signal from the signal source, and this input impedance remains unchanged regardless of changes in the voltage level across the sampling circuit.

The bias circuit 7 applies a predetermined bias level equal to 1/2 of the DC power supply voltage to the capacitors CIN, C2A, C2B,
Give to each of C3A and C3B.

The signals applied to these capacitors cause voltage fluctuations above and below the bias level.

When power is supplied to the various circuits that make up this device and there is no input signal, the voltage controlled oscillator VOO performs electrical oscillation at a frequency that is six times the center frequency between the upper and lower limits in the band mentioned above. These vibrations are applied to the dividing circuit D, which generates two trains of switching pulses at each phantom output terminal of the gate circuit G.

Referring to FIG. 2b, the first row of switching pulses φ2A φ
2B each last for two cycles of oscillation from the oscillator VCO and are separated from the preceding pulse in each column by a time interval equal to one oscillation cycle.

Alternating pulses φ2A and φ2B are applied to transistors TR2A and TR2B, respectively, each pulse driving the gate electrode of the transistor in a negative state with respect to the source electrode.

This causes the transistor to conduct during the pulse period.

If the frequency of the input signal is equal to 1/6 of the oscillation frequency of the oscillator VOO, as shown in FIG. continue.

Between successive pulses there is a time interval corresponding to 1/6 the period of the input signal.

At the time when the polarity of the input signal changes, each switching pulse φ2A
When the center of and φ2B is positioned, the transistor T
R2A is conductive for one third of the input signal period, and at the midpoint of this period the polarity of the signal changes from positive to negative.

Similarly, transistor TR2B conducts for a period equal to 1/3 of the spaced input signal and changes from negative to positive polarity at the midpoint of this period.

Each switching pulse φ2A given to transistor TR2A
During the first half of , a small positive charge flows through transistor TR2A to capacitor C2A.

During the next half period of switching pulse φ2A, capacitor C2A
When the polarity of the voltage applied to is reversed, the 7 positive charge is removed from the capacitor.

Therefore, there is no net charge increase in capacitor C2A as a result of applying the switching pulse to transistor TR2A.

Similarly, a small negative charge charges capacitor C2B during the first half of the switching pulse φ2B applied to transistor TR2B, and that charge is removed during the second half of each pulse, resulting in a net charge on capacitor C2B. There is no increase or decrease in charge.

As long as the input signal has the frequency and phase described above with the switching pulse extracted from the oscillator, the voltage across capacitors C2A and C2B remains equal to the magnitude of bias voltage VB from the bias circuit.

These voltages VB are applied to each input terminal of differential amplifier A1, and an output voltage equal to VB is generated from the amplifier.

This output voltage VB applied to the control input terminal of the oscillator Vco maintains the oscillator ramp voltage at an oscillation frequency in the middle of the predetermined frequency band.

That is, the oscillation frequency is equal to six times the human signal frequency.

If the input signal is 1/6 or less of the oscillation frequency and within a predetermined frequency band, transistors TR2A and TR2B
The switching pulses φ2A and φ2B applied to the input signal vary in phase with respect to the input signal.

In this case, each switching pulse φ2A is the transistor TR2A
, the positive period of the input signal is longer than the negative period.

When each switching pulse φ2B is applied to the transistor TR2B, the negative period of the input signal is longer than the positive period.

As a result, the voltage on capacitor C2A becomes positive with respect to the voltage on capacitor C2B.

During other short periods of time, the voltage on capacitor C2A becomes negative with respect to the voltage on capacitor C2B.

The net effect is that, on average, there is a greater positive voltage on capacitor C2A than on capacitor C2B.

This causes the output voltage of differential amplifier A1 to become more positive, so that the oscillator ramp voltage increases and the oscillator oscillation frequency decreases until it is equal to six times the frequency of the input signal.

The time required for the frequency of oscillator VOO to reach this low value is determined by the time constants of the integral hold systems RV, C2A and C2B.

If the frequency of the human input signal is 1/6 or more of the oscillation frequency and within a predetermined frequency band, a low output voltage is generated from the amplifier A1, and a reduced ramp voltage is applied to the oscillator VOO.
The oscillation frequency increases accordingly.

The frequency of the input signal is }/6 of the oscillation frequency of the oscillator VOO
, and if the switching pulse is not centered at the time the input signal changes its polarity, the voltage at one force of capacitors C2A and C2B will be positive with respect to the other force.

This changes the control voltage applied to the oscillator VOO,
Change the oscillation frequency of the oscillator.

Such a change in frequency necessarily changes the phase between the switching pulse and the input signal, and this frequency change continues until the phase between the switching pulse and the input signal is in the preferred phase relationship.

．． At this point, the control voltage applied to the oscillator VOO returns to a value corresponding to the oscillation frequency of the oscillator VOO, and the oscillation frequency returns to a value equal to six times the frequency of the input signal.

As mentioned above, the lamp voltage of the oscillator VOO has upper and lower limits.

Therefore, if the frequency of the input signal is outside the predetermined frequency band, a control voltage is produced from amplifier A1 that cannot move the lamp voltage outside the upper and lower limits.

Therefore, the oscillation frequency cannot be set to a value equal to six times the input signal frequency.

Word sampling, assuming that the input signal has a frequency equal to the free-running frequency of the oscillator VOO, or that the frequency of the input signal is sufficiently close to the free-running frequency of the oscillator that is constrained to the input signal frequency in the manner described above. Consider the effects of other switching pulses φ and φ3B applied to the circuit.

As mentioned above, each of these other switching pulses has a duration equal to twice the oscillation frequency duration of the oscillator VCO;
Therefore, it has a period that is ⅓ of the period of the input signal.

Each pulse is separated from the next by a period of 1/6 of the input signal.

These pulses φ3A and φ3B are supplied to transistors TR3A and TR3B, respectively.

During the period when the switching pulse φ3A or φ3B is applied to the transistor TR3A or TR3B, the transistor is conductive and the output signal is transmitted to the capacitor C3 connected to it.
Transistor T such that the input signal transitions from negative to positive polarity at the beginning of each pulse applied to A or C3B
The phase of pulse φ3A given to R3A is selected in advance.

The pulse will last for 2/3 of the positive half cycle of the input signal.

In the case of transistor φ3B, each pulse φ3B occurs at the beginning of the negative half cycle of the input signal and lasts for 2/3 of that half cycle.

As a result, positive charge flows into capacitor CaA during a portion of each positive half-cycle of the input signal, and negative charge flows into capacitor C3B during a portion of each negative half-cycle of the input signal.

Assuming that the frequency of the input signal remains equal to 1/6 of the oscillation frequency of the oscillator VOO and the phase of the switching pulse is as described above, the positive charge is transferred to the capacitor C3.
An equal negative charge is accumulated on capacitor C3B.
is accumulated in

The voltage across capacitors C3A and C3B is applied to each input terminal of comparator C.

If the differential voltage between both input terminals has the correct sign and exceeds the set threshold to represent an input signal amplitude greater than a predetermined magnitude, the output of comparator C will be llO”
The state changes to the "1l+ state."

The output of comparator C is applied to the input terminal of a word counter WC of the type disclosed in GB 1279611.

As previously mentioned, counter WC has a clock input terminal for receiving clock pulse φ1 from the fifth output terminal of gate circuit G.

Each clock pulse .phi.1 has the same duration as the oscillation period of the oscillator VOO, and its repetition frequency is equal to 1/6 of the oscillation frequency of the oscillator, ie, the frequency of the input signal.

As described in British Patent No. 1279611, the output of counter WC is 11 if the output of comparator C is
1+, the first state is simply switched to a second state representing the detection of a signal having a frequency within a predetermined frequency band, and the counter WC receives a predetermined number of consecutive clock pulses φ1. It remains in that state for as long as it does.

This prevents transient input signals within a predetermined frequency band from providing output signals to the drive circuits and switches at the output of the device.

Due to the integral nature of the storage means in each sampling circuit, this circuit does not operate with high levels of noise and clocking frequencies outside the range determined by the oscillator VOO.

This circuit also does not work when tuned to harmonics of frequencies within the detection range.

For example, for an input signal having a frequency equal to twice the frequency in the predetermined range, each sampling pulse applied to the oscillator sampling circuit 3 spans two-thirds of one cycle of the input signal.

Therefore, when the frequency of the input signal changes, charges of the same polarity and magnitude are accumulated in the capacitors C2A and C2B.

In other words, the voltages applied to both input terminals of the differential amplifier A1 become equal in magnitude and phase, and the output voltage applied to the oscillator VCO cannot change.

Therefore, the oscillation frequency of the oscillator is not affected, and synchronization with the input signal cannot be maintained.

Regarding the sampling circuit 5, each sampling pulse applied to the circuit occurs at the same time in one cycle, the voltage applied to the comparator C remains equal in magnitude and phase {ζ, and the output of the comparator is ``1n Unable to switch state.

The same applies to the case where the harmonic has a frequency that is an even number multiple of the frequency within the predetermined frequency band.

For third harmonic frequencies within a predetermined range, the switching pulses applied to the oscillator and word sampling circuits 3 and 5 each span one complete cycle of the input signal.

Once upon a time, capacitors C2A, C2B, C3A and C
No net charge is stored on any of 3B and no change occurs in the control voltage of differential amplifier A1 or the output of comparator C.

For the fifth harmonic, the oscillator vco is locked to the input signal, but the polarity of the charge on capacitors C3A and C3B is of the opposite polarity to that required to give the output It 1 n state of comparator C.

In the case of the seventh high frequency, a voltage of magnitude and sine occurs that provides the control voltage from the differential amplifier A1, and the frequency of the oscillator VCO is locked to the frequency of the input signal.

Word sampling circuit capacitors C3A and C3B
The voltage from C also changes, and this voltage has the appropriate phase to switch the output of comparator C.

However, the amplitude of this change in voltage is 18 dB smaller than the change caused by an input signal of the same amplitude within a given frequency band.

The circuit shown in FIG. 1 can be changed by changing the phase of each switching pulse applied to the word sampling circuit 5.

As long as each pulse begins and ends during a single half-cycle of the input signal, and as long as each pulse has a duration twice the space between successive pulses, this circuit will work well for high frequencies. Do not work.

Regarding the switching pulses of the oscillator sampling circuit 3, even if the duration of the switching pulses changes, as long as each pulse is centered on the polarity change point of the input signal, it can respond to harmonics.

For example, one variation of the device of FIG.
adjusting the oscillation frequency of O such that each switching pulse applied to the word sampling circuit has a duration equal to 1/3 of one cycle of the input signal for all input signals having frequencies within the predetermined band; is raised.

Each pulse is centered between the maximum or minimum value of the human input signal.

Regarding the oscillator sampling circuit, each switching pulse of any circuit occupies the time gap between two phase-adjacent pulses of the word sampling circuit.

That is, the pulse period of the sampling circuit for the oscillator is equal to 1/6 of one cycle of the human input signal (/2o) This modified circuit is equal to 2 of the frequency within the predetermined zero band.
No operation is performed in response to an input signal having twice the frequency.

An input signal that is the third harmonic of a frequency within a predetermined band causes the frequency of oscillator VOO to lock to the input signal.

However, the polarity of the charge on the capacitor in the word sampling circuit takes an average value of zero, and the output of the comparator C does not change.

The influence of harmonics higher than the third harmonic can be eliminated by providing appropriate high-frequency attenuation at the input terminal of the circuit.

In the circuit shown in FIG. 1, when the oscillator VOO is locked to the human input signal, the variation in the net charge on capacitors C2A and C2B is very low and constant in value.

However, when a switching pulse is applied, the charge on each capacitor increases momentarily and decreases to zero during the time gap between successive switching pulses.

In this way, when the charge temporarily increases or decreases, the oscillator VCO
The oscillation frequency becomes unstable.

To prevent this instability, the output terminal of the differential amplifier A1 is coupled to the control input terminal of the oscillator VOO via a switch and a storage capacitor between the control input terminal and ground.

This switch is activated by continuous pulses φ2A, φ2
Driven by a pulse from the divider that closes into the gap between B.

? As a result, the capacitor is charged to a constant voltage that represents the difference between the charges on capacitors C2A and C2B during the interval between switching pulses and is not adversely affected by temporary instabilities in charge.

Another variation of the circuit of FIG. 1 is to provide a switch at the input terminal of the comparator C in the word sampling circuit.

A circuit for varying the threshold voltage of the comparator is connected to the switch.

When the output of the word counter switches to a state indicating detection of an input signal having a frequency within a predetermined band, the switch is actuated by the output voltage provided by the word counter.

The effect of operating the switch is to change the threshold voltage up to a certain value.

That is, when the charge on capacitors C3A and C3B decreases to 1/2 of the turn-on value, only the output terminal of the comparator
It is arranged so that the state returns from the "l1" state to the "It" state.

This prevents the output terminal of the comparator from switching between the n n and ll1'' states due to small variations in the voltages on capacitors C3A and C3B about the original threshold.

Hereinafter, features of this invention other than those described in the claims will be explained.

1. In the claimed electrical circuit arrangement, the frequency of the first sampling period is initially equal to twice said frequency within a predetermined band, but equal to twice the upper and lower frequencies of the predetermined band. can be varied over a band of upper and lower frequencies, and each first sampling period occurs at the point in time when the polarity of the input signal changes or when the frequency of the first sampling period changes to a value equal to twice the input signal frequency. An electric circuit device configured to spread around the area.

2. The electric circuit device according to item 1, wherein each first sampling period has a gap twice the time gap between successive 10th) sampling periods.

3. In the first or second term, the second sampling period also initially has a frequency equal to twice said frequency within the predetermined band, but with an upper part equal to twice the upper and lower frequencies of the predetermined band. and electrical circuit devices that can vary over lower frequencies.

4. 3. The electric circuit device according to claim 3, wherein each of the second sampling periods has a time width twice as long as the time gap between successive second sampling periods.

5. In paragraph 4, the electric circuit device wherein the second sampling period starts and ends within a half cycle time of the input signal when the frequency of the second sampling period changes to a value equal to twice the input signal frequency. .

6.

5. The electrical circuit arrangement according to claim 5, wherein each second sampling period begins at a time when the polarity of the input signal changes.

7. In each of the foregoing clauses, the first sampling means comprises integral storage means, such that during operation the first switching signal from the oscillating means causes the switching signal to be applied to the storage means during the period of this switching signal. an electrical circuit arrangement which is applied to an input terminal of the means and in which an input signal is provided to the storage means;

8. Electric circuit arrangement according to claim 7, wherein the storage means of the first sampling means includes capacitor means in which a charge representing the difference in frequency and phase between the switching signal and the input signal is stored.

9. An electric circuit device according to item 8, wherein the integral storage means includes a resistor and a capacitor to which input signals are applied alternately.

10. In the first or second term, the first sampling means is constituted by one resistor, two capacitors, and a switching means for alternately applying the input signal to each capacitor during operation, and each capacitor has a the amplifiers are connected to respective input terminals of dynamic amplifiers, the amplifiers generating control voltages applied to the oscillating means such that each first sampling period has a value centered at or near the point of change in polarity of the input signal; An electric circuit device in which the first switching signal frequency is changed until the electric charges of both capacitors become equal to each other.

11, paragraph 10, the output terminal of the differential amplifier is coupled to the oscillating means via a switch to which the switching signal is applied from the oscillating output means, whereby the switch is closed only during the first sampling period. an electrical circuit arrangement which is provided at the human input terminal to the capacitor means or to the oscillating means and provides the oscillating means with a control voltage which is unaffected by temporary instability of the charge in the capacitor.

12. In each of the foregoing paragraphs, the second sampling means includes an integral accumulation circuit and a switching means by which the input signal is applied to the accumulation means during operation, and the second switching signal from the oscillating means is transmitted during each second switching signal period. an electrical circuit arrangement applied to a switching input terminal of the switching means operative to supply an input signal to the storage means;

13. In paragraph 12, the integral accumulation means of the second sampling means calculates the magnitude of the human signal when the second sampling period becomes another frequency and phase relationship set by inscribing the input signal. Electrical circuit means including capacitor means in which a charge representing a charge is stored.

14. In item 13, the integral storage means includes a resistor and a second
An electric circuit device comprising first and second capacitors to which switching signals of 1 and 2 are alternately applied.

15. In any of clauses 3 to 6, the second sampling means comprises a resistor, two capacitors and a switching means for alternately applying the input signal to each capacitor during operation, each capacitor being connected to a comparator. is connected to each input terminal, and when the difference between the charges on both capacitors and therefore the voltage applied to the comparator exceeds a predetermined value and has a predetermined sign, the comparator outputs an output representing the detection of the input signal. An electrical circuit device configured to provide a signal.

16. In clause 15, the counter is connected to the output terminal of the comparator, and the output terminal of the counter is connected to the input terminal only if the output signal is held at the output terminal of the comparator for a predetermined number of sampling periods. An electrical circuit device that enters a predetermined state indicating the detection of.

17. In clause 16, another switching means is provided between the capacitor and the comparator, said further switching means being actuated by the output voltage from the counter, and when actuated, the output signal is switched from the capacitor to electrical circuit means for reducing the voltage to a predetermined magnitude that must be reduced.

18. In the claims, the frequency of the first sampling period is initially equal to twice said frequency in a given band, but within a range of upper and lower frequencies equal to twice the upper and lower frequencies of the given band. and when the frequency of the first sampling period is changed to a value equal to twice the input signal frequency, the first
The sampling period is equal to 1/3 cycle of the input signal and spans a time region centered with respect to the maximum value of the input signal, and the second sampling period has a time width equal to 1/6 cycle of the input signal. an electrical circuit device comprising: an electrical circuit device occupying a time domain between successive first sampling periods;

[Brief explanation of drawings]

1 is a block diagram of an electric circuit means according to the invention, and FIG. 2 shows an input signal synchronized in frequency and phase with respect to the frequency and phase of an oscillator in the circuit means of FIG. A switching signal is shown. Explanation of symbols, 1... Oscillation circuit, 3, 5...
...Sampling circuit, 7...Bias circuit,
A1...Differential amplifier, C...Comparator,
WC: Counter, VOO: Voltage controlled oscillator, D: Divider circuit, G: Gate circuit.

Claims (1)

[Claims] 1. An electric circuit device that receives an input signal that changes in alternating current and detects whether the frequency of the input signal is within a predetermined frequency range including a reference frequency, comprising: a control input terminal for receiving polarity change points of the input signal from positive to negative and from negative to positive when the input signal is substantially equal to the reference frequency; A first switching pulse train is sent through the first means, the time period including the positive and negative peaks of the input signal being a second sampling period. 2 switching pulse trains can be sent through the second output means, and if the control signal is provided indicating that the input signal is within the frequency range (ζ), oscillation means capable of varying the frequency of the second switching pulse train; a first input terminal receiving the input signal; and receiving the first switching pulse train during the first sampling period;
a first switching means for passing the human signal;
a first accumulating means for integrating and accumulating the input signal that has passed through the switching means; and as a result of monitoring the accumulation level of the first accumulating means, when the frequency of the input signal is within the frequency range, the frequency range is indicates what is within, and
A signal representing a phase difference between the input signal and the first sampling period is transmitted as the control signal, and otherwise a signal representing that the frequency of the input signal is outside the frequency range. a first sampling means having a means for sending the control signal as the control signal; a second input terminal receiving the input signal; and receiving the second switching pulse train, during the second sampling period;
a second switching means for passing the input signal;
a second accumulation means for integrating and accumulating the input signal that has passed through the switching means; and as a result of monitoring the accumulation level of the second accumulation means, when the amplitude of the input signal becomes higher than a predetermined level, the input signal and second sampling means having means for sending an output signal representing the detection of the electrical circuit.