JPS5836436B2 - Memory cell selection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory cell selection method, and an object of the present invention is to provide a memory cell selection method that can relatively simplify the circuit and shorten the refresh time. This is the purpose.

Generally, in a dynamic memory constructed using MIS (metal-insulator-semiconductor) IC technology, one memory cell is selected from a plurality of memory cells from a selection line in the row direction, and for this selected memory cell, Write and read data are input and output from data lines in the column direction.

And when using such dynamic memory 1
In order to retain the information stored in each memory cell, the memory cell is periodically refreshed.

In this case, a method is known in which by selecting each memory cell, the cells in the entire row are refreshed.

Generally, when inputting necessary information to a memory or extracting necessary information from the memory, only one memory cell in the selected row is refreshed.

Therefore, if the time from the end of one refresh operation to the start of the next refresh operation for one memory cell 1 becomes long, the information in the memory cell may disappear.

Therefore, memory cells 1 in all rows are
It is necessary to refresh frequently, and the refresh time cannot be ignored.

Therefore, it is desirable to be able to shorten the refresh cycle time as much as possible.

However, the above method uses n
This results in a disadvantage that the refresh cycle time is twice as long (n is the number of rows), and the refresh time becomes considerably longer due to the number of rows n1.

The present invention eliminates the above-mentioned drawbacks, and will be described below in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the memory cell selection method according to the present invention.

In the figure, 1 and 6 are lines 3, 8, 10 and 13 in the row direction.
This is an address signal input terminal for selecting.

The address signals applied to the terminals 1 and 6 are decoded by the decoder drive circuit 2.

As a result, a row selection signal is applied from the decoder drive circuit 2 to lines 3, 8, 10, 13, etc. in the row direction.

4, 9, 11, 14, 4', 9', 11', 14', etc. are memory cells, and their respective selection terminals are coupled to the corresponding lines 3, 8, 10, 13, and their respective data inputs. The output terminals are common data lines 5, 12, 5 in the column direction.
15 connected to ', 12', etc. are the lines 3 and 1 above.
0, and 16 is a wire for connecting line 8 and line 13.

20, 20' are first separation circuits, as shown in the figure.
Its terminals a and a' are connected to lines 5 and 5'l, respectively.
These terminals b and b' are connected to lines 1 2 and 1, respectively.
Terminals c and c65 are connected to data input/output terminals 22 and 22 through lines 21 and 21, respectively, and terminals d and d' are connected to data input/output terminals 22 and 22 through lines 19 and address buffer drive circuit 18, respectively. and is connected to the address signal input terminal 17.

This first separation circuit 20, 20' is connected to the lines 5, 5' and 12, 12' in response to the signals supplied to the terminals d, d' via the line 19, as will be clear from the following description. This is for coupling the lines 21, 21' to the alternative line 21, 21'.

That is, the first separation circuit 20.20' is substantially
It constitutes a selection circuit.

The first separation circuits 20, 20' are composed of MIS transistors Q and Q2 as shown in FIG. 2, for example.

Note that in FIG. 2, MIS transistors Q1 and Q2 are operated selectively by one signal supplied to terminal d.
2 has a well-known complementary MIS transistor structure.

23 is a second separation circuit, and address input terminal 25
．． Based on the address signals V and Wt applied to 26,
This is a circuit for selectively coupling the data input/output terminals 22 and 22' to the data input/output terminal 241.

That is, the second separation circuit 23 substantially constitutes a second selection circuit.

Now, memory cells 4, 9, 11, 14, 4', 9', 11
When writing data to each of ' and 14', write selection signals X and y are supplied from terminals 1 and 6, address signal 2 is supplied from terminal 171, and address signal is sent from terminals 25 and 26. All that is required is to supply V and W, and to supply write data from the terminal 24.

In this case data is transferred from one line 21 or 21' selected by the second separating circuit 23 to the first separating circuit 2.
One of either 0 or 20' is sent.

Further, the above address signal is transmitted to the address buffer drive circuit 1.
8, first separation circuits 20, 20 sequentially via line 19
', so lines 21, 21 above
' is line 5, 5' or line 1 2, 1 2'
If any one of these is connected, it will be one.

On the other hand, due to the above signal xy, lines 3, 10 or 8,
One of 13 is selected.

As described above, memory cells 4, 9, 11, 1 4, 4
Select one of ', 9', 11', 14',
You can put information into it or get information out of it.

Memory cells 4, 9, 11, 14, 4', 9', 1 1'
, 14', a refresh row selection signal is supplied from terminals 1 and 6, and memory cells 4 and 4 on two lines 3 and 10 in the row direction are refreshed.
', 11, 11' are refreshed once at the same time, and memory cells 9, 9' of two lines 8, 13 in the row direction are subsequently refreshed.
, 14, and 14' are refreshed simultaneously.

Note that the memory cell may be of a dynamic type and refreshed by a selection signal.

In addition, in this first embodiment, two lines in the row direction are connected, but the invention is not limited to this, and it is possible to connect three or more lines in the row direction by devising the first separation circuit. It's okay.

As described above, according to the memory cell selection method of the present invention, a plurality of lines in the row direction are connected, a predetermined first separation circuit is provided, and the first separation circuit performs writing.
When reading, only one of the lines in the row direction is selected, so multiple data will not be read out from the lines in the row direction at the time of the above, and in the case of refresh. Since the required signals are simultaneously sent to the plurality of lines in the row direction, the refresh time is shortened, and the first separation circuit only needs to be one for each column, and its input circuit is simple. Therefore, the addition of the first separation circuit does not complicate the overall circuit configuration, and the connection described above simplifies the decoder 2, so the overall circuit configuration is simple.

[Brief explanation of drawings]

FIG. 1 is a block system diagram of an embodiment in which the memory cell selection method according to the present invention can be implemented, and FIG. 2 is a specific circuit diagram of a separation circuit in the present embodiment. 1, 6, 17, 22, 22', 24, 25, 26...
Terminal, 2... Decoder (drive circuit), 3, 8, 10,
13...Line in the row direction, 4, 9, 11, 1 4,
4', 9', 11', 14'...Memory cell, 5, 12, 5', 12'-...Line in column direction, 15
, 16... Wire, 18... Address buffer drive circuit, 19, 2 1 , 2 1'... Line, 20
, 20', 23...separation circuit, Q1-Q6...MI
S transistor.

Claims (1)

[Claims] 1. First and second row-direction lines, a first memory cell with a selection terminal coupled to the first row-direction line, and a selection terminal coupled to the second row-direction line. a first column direction line to which the input/output terminals of the first memory cell are coupled; a second column direction line to which the input/output terminals of the second memory cell are coupled; a decoder circuit for selectively selecting the first and second row-direction lines, and selecting one of the first and second column-direction lines in response to an address signal different from the address signal applied to the decoder; a selection circuit, wherein one of the first and second memory cells is selected by the decoder circuit and the selection circuit. 2 The first and second memory cells are composed of dynamic memories, and the first and second row lines are n.
2. The memory cell selection method according to claim 1, wherein the first and second memory cells are refreshed every time the first and second memory cells are selected.