JPS5836435U - I/O device control circuit - Google Patents
I/O device control circuitInfo
- Publication number
- JPS5836435U JPS5836435U JP12788581U JP12788581U JPS5836435U JP S5836435 U JPS5836435 U JP S5836435U JP 12788581 U JP12788581 U JP 12788581U JP 12788581 U JP12788581 U JP 12788581U JP S5836435 U JPS5836435 U JP S5836435U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- flop
- input
- flip
- output device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の制御回路図、第２図は第１図の正常動作
タイムチャート、第３図は第１図の異常動作タイムチャ
ート、第４図は本考案の制御回路原理図、第５図は第４
図に関するタイムチャートである。
１・・・・・・セットリセットフリップフロップ、２゜
５・・・・・・立ち上がりトリガワンショットマルチ、
４・・・・・・Ｄタイプフリップフロップ、１０・・量
計算機、１１・・・・・・入出力装置、１２・・・・・
・制御回路、ｂ・・・・・・ビジー、Ｃ・・・・・・駆
動パルス、ｄ・・曲エンドシンク。Fig. 1 is a conventional control circuit diagram, Fig. 2 is a normal operation time chart of Fig. 1, Fig. 3 is an abnormal operation time chart of Fig. 1, Fig. 4 is a principle diagram of the control circuit of the present invention, and Fig. 5 is a diagram of the control circuit of the present invention. The figure is number 4
It is a time chart regarding the figure. 1...Set/reset flip-flop, 2゜5...Rising trigger one-shot multi,
4...D type flip-flop, 10...quantity calculator, 11...input/output device, 12...
- Control circuit, b... Busy, C... Drive pulse, d... Song end sync.
Claims (1)
ップを備え、パルスにより駆動される入出力装置を制御
する制御回路において、ビジー中に前記入出力装置から
入力するレディ信号の立ち上がりエツジでエンドシンク
フリツプフロツフヲセットする手段と、そのエンドシン
クフリップフロップの出力を前記入出力装置の駆動パル
スによりインヒビットする手段と、インヒビットされた
前記エンドシンクフリップフロップの出力によりワンシ
ョットマルチをトリガーする手段と、その出力パルスに
よりビジーフリップフロップをリセットする手段とから
なることを特徴とする入出力装置制御回路。In a control circuit that is equipped with a busy flip-flop that indicates that the control circuit is in operation, and that controls an input/output device driven by pulses, an end sync flip is activated at the rising edge of a ready signal input from the input/output device while the control circuit is busy. means for setting the end sync flip-flop; means for inhibiting the output of the end sync flip-flop by a drive pulse of the input/output device; and means for triggering the one-shot multi by the inhibited output of the end sync flip-flop; An input/output device control circuit comprising means for resetting a busy flip-flop by an output pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12788581U JPS5836435U (en) | 1981-08-31 | 1981-08-31 | I/O device control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12788581U JPS5836435U (en) | 1981-08-31 | 1981-08-31 | I/O device control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5836435U true JPS5836435U (en) | 1983-03-09 |
Family
ID=29921599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12788581U Pending JPS5836435U (en) | 1981-08-31 | 1981-08-31 | I/O device control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5836435U (en) |
-
1981
- 1981-08-31 JP JP12788581U patent/JPS5836435U/en active Pending
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