JPS5835950A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5835950A
JPS5835950A JP56134026A JP13402681A JPS5835950A JP S5835950 A JPS5835950 A JP S5835950A JP 56134026 A JP56134026 A JP 56134026A JP 13402681 A JP13402681 A JP 13402681A JP S5835950 A JPS5835950 A JP S5835950A
Authority
JP
Japan
Prior art keywords
roughness
film
lead frame
wire
plated film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56134026A
Other languages
Japanese (ja)
Other versions
JPS6257257B2 (en
Inventor
Masahiro Koizumi
小泉　正博
Hitoshi Onuki
仁 大貫
Tateo Tamamura
玉村　建雄
Tomio Iizuka
飯塚　富雄
Susumu Okikawa
進 沖川
Hiroshi Kato
弘 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56134026A priority Critical patent/JPS5835950A/en
Publication of JPS5835950A publication Critical patent/JPS5835950A/en
Publication of JPS6257257B2 publication Critical patent/JPS6257257B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48755—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01—Chemical elements
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To strengthen the junction between a lead frame and an Al wire, and to reduce secular degradation by forming an electric Ni plated film having not more than 0.5mum roughness onto the lead frame. CONSTITUTION:When an Al wire is joined onto an Ni plated film, difference is generated in shearing strength according to the difference of the roughness of the Ni plated film, and the more the surface is rough, the more a junction rate lowers. With the electrically plated Ni film, roughness is far smaller than a chemically plated film and approximately 0.1-0.3mum, and scatter is small. The rate of phosphorus and a brightener in the plated film is increased, and the roughness of the surface of the film is decreased and made 0.5mum or less. According to this constitution, the Al wire junction with a strong joined section is obtained while the secular degradation is also reduced, and the reliability of the device is improved.

Description

【発明の詳細な説明】 零発−は半導体装置に係り、特に、アルミニウムワイヤ
にて、半導体素子上の電極とり−ドフレームとを導電接
続し九半導体装置に関する０従来のＩＣ，ＬＳＩ等の半
導体装置にお妙る、半導体素子上の電極とリードフレー
ムとの接続は。DETAILED DESCRIPTION OF THE INVENTION The invention relates to a semiconductor device, in particular, to a semiconductor device such as a conventional IC, LSI, etc., in which an electrode on a semiconductor element is conductively connected to a lead frame using an aluminum wire. The connection between the electrodes on the semiconductor element and the lead frame depends on the equipment.

金１えはアルミニウム（合金）ワイヤボンディングによ
ってなされている。The gold plate is made by aluminum (alloy) wire bonding.

金ワイヤボンディングの場合には、リードフレームの表
面に勤めつき膜が設けられ、一方、アルミニウム（合金
）ワイヤボンディングの場合には、化学的にめっきした
Ｎ１めっき膜が、リードフレームの表面に設けられてい
る・ 金ワイヤと細めつき膜との導電接続は、性能の面では極
めて優れているが、ワイヤ及びリードフレームに金を用
いているため、コストが高いという欠点がある。In the case of gold wire bonding, a hard coating is provided on the surface of the lead frame, while in the case of aluminum (alloy) wire bonding, a chemically plated N1 plating film is provided on the surface of the lead frame. The conductive connection between the gold wire and the thinned membrane has excellent performance, but has the drawback of high cost because gold is used for the wire and lead frame.

一方、アルミニウムワイヤと、その表面に化学的にめっ
きし九Ｎ１めりき膜を施し九Ｆ・−Ｎ１合金のリードフ
レームとの接続は、 （１）リードフレームのＮｉｂつき膜のめつき速度が遅
いため畏時間を要することからコストが高いことと、（
２）　　Ｎｉめつき膜の表面が比較的あらいため、ボン
ディング時にアルミニウムワイヤと接合しにくいこと。On the other hand, when connecting an aluminum wire to a lead frame made of 9F/-N1 alloy with a 9N1 plating film chemically plated on its surface, (1) The plating speed of the Nib-coated film on the lead frame is slow. The cost is high because it takes a lot of time, and (
2) Since the surface of the Ni plating film is relatively rough, it is difficult to join it to the aluminum wire during bonding.

（３）　　また、接合したとしても、剥離し易いため、
喪好で信頼性のある接続が得られないこと、などという
欠点がある。(3) Also, even if bonded, it is easy to peel off, so
There are disadvantages such as the inability to obtain a reliable connection due to mourning conditions.

さらに又、アルミニウムワイヤによる半導体素子上の電
極とリードフレームとの接続には、直径３０μｍのアル
ミニウム細線が普通に使用されている。Furthermore, thin aluminum wires with a diameter of 30 μm are commonly used to connect electrodes on semiconductor elements and lead frames using aluminum wires.

このため、ボンディング後、プラスチックパッケージす
る時に、リードフレーム側のワイヤ切れや、接合部の剥
離を生ずるという問題がある。その上に、製品として稼
動中に室温以上の５ｔＬ−例えば１５０℃、２００℃な
どのＳ度に長時間加熱されるため接合部が劣化し、同様
にワイヤ切れ、筐たは剥離を生ずるという問題がある。Therefore, when plastic packaging is performed after bonding, there is a problem in that wires on the lead frame side may break or the joint may peel off. In addition, during operation of the product, it is heated for a long time to 5tL above room temperature - for example, 150℃, 200℃, S degree, etc., so the joint deteriorates, and the problem is that the wire breaks and the casing or peels off. There is.

そのため、アルミニウムワイヤとリードフレームのＮ１
めつき膜との接合部の強度を向上し、好適な接続１＊現
して信頼性の高い半導体装置を開発することは、極めて
重畳である。また、一方、半導体装置は低コストを指向
しているため、リードフレームのコスト低減も重畳であ
る。Therefore, N1 of aluminum wire and lead frame
It is extremely important to develop a highly reliable semiconductor device by improving the strength of the joint with the plating film and achieving a suitable connection1*. On the other hand, since semiconductor devices are aimed at low cost, the cost reduction of lead frames is also a superimposition.

し九がって、本発明の目的は、アル１ニウムワイヤを接
合されるＮｉめつき膜リードフレームのコストを像滅し
、さらに前記Ｎ１めつき膜リードフレームとアル１ニウ
ムワイヤとの容易かつ強固な接合を得ることのできる半
導体装置を提供するにあるＯ 前記目的を達成する丸め、不発゛明においては、リード
フレームの表面に形成されるＮ１めつき膜の表面あらさ
を０．５μｍ以下にし、アル１ニウムワイヤとの接合性
を教養している。Therefore, it is an object of the present invention to reduce the cost of a Ni-plated film lead frame to which aluminum wires are bonded, and to provide easy and strong bonding between the Ni-plated film lead frame and the aluminum wire. In order to achieve the above object, the surface roughness of the N1 plating film formed on the surface of the lead frame is set to 0.5 μm or less, and the aluminum plated film is We are well-educated in bondability with aluminum wire.

本発明は、つぎのような新規な事象の確認に基づい・て
なされたものである〇 （１）Ｆ・−Ｎｉ製リードフレームの表面へのＮ１めつ
き膜形成は、電気的な方法でも可能であること。この場
合のＮ１めつき膜の生成時間は、化学的方法に比べて１
１５に短縮されること。The present invention was made based on the confirmation of the following novel phenomena. (1) Formation of N1 plating film on the surface of F.-Ni lead frame can also be done by electrical method. To be. In this case, the generation time of the N1-plated film is 1
be shortened to 15.

これによって、リードフレームの製造能率を上げ、コス
トの低減をはかることができること０ （２）表１ｉ　Ｋ　Ｎｉめっき属を有するリードフレー
ムに対するアルミニウムワイヤの接合強度は、前記Ｎｉ
めつき膜の表面あらさが小さいはと大龜くなること。特
に、　Ｎ１めつき膜の表面あらさが０．５μｍ以下の場
合には、十分な接合強度が得られること。This makes it possible to increase lead frame manufacturing efficiency and reduce costs.0 (2) Table 1i The bonding strength of the aluminum wire to the lead frame with K Ni plating
The surface roughness of the plating film becomes small. In particular, if the surface roughness of the N1 plated film is 0.5 μm or less, sufficient bonding strength should be obtained.

（３）　　リードフレーム表面のＮｉめつき膜のあらさ
は、電気的にめっきすることにより、小さくできること
。(3) The roughness of the Ni plating film on the lead frame surface can be reduced by electroplating.

以下に、本発明の詳細な説明する。The present invention will be explained in detail below.

まず初めに、電気的にＮ１めつき膜を表面にめっきし九
Ｆｅ−Ｎｉリードフレームと、化学的にＮ１めつき膜を
表面にめっきし九Ｆａ　−Ｎｉリードフレームの表面の
あらさを測定したＯ この場合の表面あらさの一１定方法は、Ｎ１めつき膜を
２０，０００倍に拡大し、ボンディング時のアルミニウ
ムワイヤのつぶれ幅にはぼ會わせた５０μｍ間を１サン
プル区間とし、その区間内での凹凸の最大値を表面あら
さの値とした。同様の測定を３０ナンプル区間について
行なった。第１図にその測定結果の分布範囲を示す。First, we measured the surface roughness of a 9Fe-Ni lead frame whose surface was electrically plated with an N1 plating film and a 9Fa-Ni lead frame whose surface was chemically plated with an N1 plating film. In this case, the method for determining the surface roughness is to magnify the N1 plating film 20,000 times, set a 50 μm interval that is blurred by the collapse width of the aluminum wire during bonding, and set it within that interval. The maximum value of the unevenness was taken as the value of the surface roughness. Similar measurements were conducted for 30 sample sections. Figure 1 shows the distribution range of the measurement results.

化学的ＫＮｉめっきしたリードフレームのあらさは、同
図ＣＫ示すように、０．５〜０．８μｍと大きい。一方
、電気的にめっきし九Ｎｉめつき膜は、同図ＫＫ示すよ
うに、０．１〜０．３μｍと非常に小さかった。また、
電気的にＮ１めつきを施こしたリードフレームは化学的
にめっきしたものに比べ、あらさにばらつきが少ないこ
とが確認された。The roughness of the chemically KNi-plated lead frame is as large as 0.5 to 0.8 μm, as shown in CK in the same figure. On the other hand, the electrically plated Ni-plated film was very small, 0.1 to 0.3 μm, as shown by KK in the same figure. Also,
It was confirmed that electrically N1 plated lead frames had less variation in roughness than chemically plated lead frames.

第２図は、直径３０μｍのアルミニウムワイヤを、あら
さの異なるＮ１め′）１１膜に、そのつぶれ幅を同一に
してボンディングした後の、接合部のせん耐強度を測定
した結果である。FIG. 2 shows the results of measuring the shear strength of the bonded portion after bonding aluminum wires with a diameter of 30 μm to N1 11 films of different roughness with the same collapse width.

これから、Ｎｌめつき膜のあらさが０．５μｍ以下の範
囲では、せん耐強度は２３．９のはソ一定値を示すが、
ａ、５μｍ以上のあらさになると、せん耐強度が急激に
減少することが知られる。From this, it can be seen that in the range where the roughness of the Nl-plated film is 0.5 μm or less, the shear resistance strength is a constant value of 23.9, but
It is known that when the roughness becomes 5 μm or more, the shear resistance strength decreases rapidly.

第２１１の測定結果から、アルミニウムワイヤボンディ
ングにおいて、Ｎ１めつき膜との強固な接合強度が得ら
れるＮｉめりき膜のあらさＦｉ、０．５μｍ以下が適し
ていることが確認された。From the 211th measurement result, it was confirmed that a roughness Fi of 0.5 μm or less of the Ni plating film is suitable for obtaining strong bonding strength with the N1 plating film in aluminum wire bonding.

ｆ／ｓ３図に、Ｎ１めつき膜のあらさと、アルミニウム
ワイヤボンディング時のアルミニウムワイヤのＮ１めつ
電膜への接合率との関係を示す。The f/s3 diagram shows the relationship between the roughness of the N1 plated film and the bonding rate of the aluminum wire to the N1 plated film during aluminum wire bonding.

ことでいう接合とは、ボンディング後のアルきニウムワ
イヤが、はぼ０のカで引剥がされない状態をさしている
。Bonding here refers to a state in which the aluminum wire after bonding is not peeled off with almost zero force.

との測定結果から、Ｎｉめつき膜表面のあらさが０、５
　μｍ以下では、接合率ＦｉＬＯＯ１を示すが、０．５
μｍ以上のあら窃のＮ１めつき膜でＦｉ接合率が低下す
ることが確認された。すなわち、例えば０６μｍのあら
さのＮｉめっき膜に対する接合率は８０チ、０．８μｍ
のあらさのＮｉめりき膜に対する接合率は４０％という
ように、Ｎｉめっき膜の表面があらくなるほど、接合率
は低下する＠ 第２図に関して前述したようにアルミニウムワイヤボン
ディングにおいてＮ１めっき膜のあらさの違いによシせ
ん耐強度に差が認められた。これはアル１＝クムワイヤ
とＮ１めっき膜の接合部の面積に関係していると考えら
れる。この場合、ワイヤのつぶれ幅は同一にしているの
で、見掛けの接合ｌｉ＋積は同じであるが、真に接合し
ている面積に逮いがあると考えられる・ このことを確認するために、あらさ０．２，０．５及び
０．６μｍのＮ１めつき膜に、つぶれ幅を一定にしてア
ルミニウムワイずをボンディングしたときの、接合部の
真の接合面積を、見掛けの接合面積との比で示したのが
第４図である。From the measurement results, the roughness of the Ni-plated film surface is 0.5.
Below μm, the junction ratio FiLOO1 is shown, but 0.5
It was confirmed that the Fi junction rate decreased in the N1-plated film with a roughness of μm or more. That is, for example, the bonding rate for a Ni plating film with a roughness of 0.6 μm is 80 inches, 0.8 μm.
The bonding rate for the roughness of the Ni plating film is 40%, and as the surface of the Ni plating film becomes rougher, the bonding rate decreases. Differences in shear strength were observed depending on the difference. This is considered to be related to the area of the joint between the Al1=cum wire and the N1 plating film. In this case, since the wire collapse width is the same, the apparent joint li + product is the same, but it is thought that there is a difference in the true joint area. To confirm this, we When aluminum width is bonded to N1 plating films of 0.2, 0.5 and 0.6 μm with a constant collapse width, the true bonding area of the bonded portion is calculated as a ratio to the apparent bonding area. This is shown in Figure 4.

０．２及び０．５μｍあらさの場合の、見掛けの接合面
積に対する真の接合面積の比は、いずれも０．８〜１．
０を示し、真の接合面積が大きいことが認められた。し
かし、あらさが０．６μｍのＮｉめつき膜の場合Ｕ　Ｏ
，５〜０．８を示し、真の接合面積が小さいことが認め
られた。In the case of 0.2 and 0.5 μm roughness, the ratio of the true bonding area to the apparent bonding area is 0.8 to 1.
0, and it was recognized that the true bonding area was large. However, in the case of a Ni-plated film with a roughness of 0.6 μm, U O
, 5 to 0.8, and it was recognized that the true bonding area was small.

リードフレームの表面は、シリコンペレットをハンダ付
けする時に、１５０〜２５０℃で、数分間大気中で加熱
されるため酸化される。そのため、酸化され九Ｎｉめつ
き膜とアルにラムワイヤボンディングした場合の接合部
のせん耐強度を検討した。When soldering silicon pellets, the surface of the lead frame is oxidized because it is heated in the air at 150 to 250° C. for several minutes. Therefore, we investigated the shear strength of the joint when ram wire bonding was performed on the oxidized nine-Ni plated film and Al.

第５図社、あらさの異なるＮｉめっ！１膜リードフレー
ムｔ％２５０℃の大気中で１時間加熱した後、その表面
にアルミニウムワイヤをボンディングして、接合部のせ
ん耐強度を求めた結果である。Figure 5: Nime with different roughness! These are the results of determining the shear strength of the joint by bonding an aluminum wire to the surface of a single-film lead frame after heating it in the atmosphere at 250° C. for 1 hour.

この結果から、Ｎ１めつき膜のあらさが０．５μｍ以下
では、せん耐強度が２３９のｑｙ一定値を示すが、１５
μｍ以上のあらさになると急激に低下し、α６μｍのあ
らさでは、わずか５１１Ｋｔで低下し九ことがわかる。From this result, when the roughness of the N1 plated film is 0.5 μm or less, the shear resistance shows a constant qy value of 239, but when the roughness of the N1 plated film is 0.5 μm or less,
It can be seen that when the roughness becomes more than μm, it decreases rapidly, and when the roughness is α6 μm, it decreases at only 511Kt.

このことから、熱酸化し九Ｎｉめつき膜でも、ワイヤボ
ンディングにおいてあらさがＱ、５μｍ以下であれば、
強固な接合部をもったワイヤボンディングが得られるこ
とが確認された。From this, even if the thermally oxidized 9Ni-plated film has a roughness of Q, 5 μm or less in wire bonding,
It was confirmed that wire bonding with strong joints could be obtained.

半導体装置は、製品として律動中に、室温以上のｓｆに
長時間加熱され、アルきニウムワイヤとの接合部が劣化
し剥離し易くなる。A semiconductor device is heated to SF above room temperature for a long time while it is being operated as a product, and the bonded portion with the aluminum wire deteriorates and becomes easily peeled off.

そこで、接合部の経時劣化をあらさ０．２．α５及び０
１μｍのＮｉめつき膜について、試験温度２００℃で検
討した結果を、第６図に示す。同図において、黒丸、白
丸、四角の６印は、それぞれＮ１めつき膜のあらさが０
．２μｍ、（Ｌ５μｍ、０６μｍの場合の測定値を示し
ている。Therefore, the deterioration of the joint over time should be reduced to 0.2. α5 and 0
FIG. 6 shows the results of examining a 1 μm Ni-plated film at a test temperature of 200°C. In the same figure, the six black circles, white circles, and square marks indicate that the roughness of the N1 plated film is 0.
．． Measured values are shown for 2 μm, (L5 μm, 06 μm).

第６図の一線（イ）で示すように、Ｎｉめつき膜のあら
さが＆２及び０．５μｍの接合部の劣化は、１０００時
間後でも生じない。しかし、同図の曲線（ロ）で示すよ
うに、０．６μｍのあらさの場合は、５００時間で、せ
ん耐強度が１３ｐに低下し、以下時間の経過と共に減少
した。As shown by the line (A) in FIG. 6, no deterioration occurs in the joint portions where the roughness of the Ni-plated film is &2 and 0.5 μm even after 1000 hours. However, as shown by the curve (b) in the same figure, in the case of a roughness of 0.6 μm, the shear strength decreased to 13p after 500 hours, and then decreased with the passage of time.

このことから、接合部の経時劣化についても、Ｎ１めつ
き膜のあらさをＱ、５μｍ以下にした方が良いことが確
認された。From this, it was confirmed that it is better to reduce the roughness of the N1 plated film to Q, 5 μm or less with respect to aging deterioration of the joint portion.

以上の各測定結果から明らかなように、アルミニウムワ
イヤを１表面にＮｉめつき膜を有するリードフレームに
ボンディングする場合は、Ｎ１めつき膜の表面あらさを
０．５μｍ以下にする会費がある。As is clear from the above measurement results, when bonding an aluminum wire to a lead frame having a Ni plating film on one surface, there is a fee to make the surface roughness of the N1 plating film 0.5 μm or less.

この場合、Ｎ１めつき膜の表面あらさけ、前記膜中に含
まれる燐や光沢剤の割合が多いほど、小さくで龜ること
が知られている。In this case, it is known that the surface roughness of the N1 plating film becomes smaller and faster as the ratio of phosphorus and brightener contained in the film increases.

第７図は、本発明の半導体装置の一実施例の断面図であ
る。図において、１はアルミニウム（合金）ボンディン
グワイヤ、２はリードフレーム７の表面に形成されたＮ
１めつき膜である。前記Ｎ１めつ電膜は、本実施例では
、電気メッキによって形成され、その表面あらさはＱ、
５μｍ以下になるように制御されている。FIG. 7 is a sectional view of one embodiment of the semiconductor device of the present invention. In the figure, 1 is an aluminum (alloy) bonding wire, 2 is an N bonding wire formed on the surface of a lead frame 7.
It is a single plating film. In this example, the N1 eyelid film is formed by electroplating, and its surface roughness is Q,
It is controlled to be 5 μm or less.

３Ｖｉ半導体ベレット、５はアルミニウム電極、６は半
導体ペレット３をリードフレーム７上に固着する九めの
はんだ層であり、４はアル１ニウムワイｆ１．半導体ペ
レツ）　３　、　Ｎｉめりきｌ［２ｔ−有するリードフ
レーム７等を一体的に被覆保護するモールド拳レジンで
ある。3Vi semiconductor pellet, 5 is an aluminum electrode, 6 is a ninth solder layer that fixes the semiconductor pellet 3 on the lead frame 7, 4 is an aluminum wire f1. It is a molded resin that integrally covers and protects the lead frame 7 and the like having semiconductor pellets) 3 and Ni-plated [2t].

この発明によれば、Ｎｌめつき膜２のあらさが０５５ｍ
以下に調整されているので、アルミニウムワイヤ１とＮ
ＬめつＩＩ［２およびリードフレーム７との接合が強固
くでき、又経年変化等による劣化も極めて小さくして、
十分に高い信頼性を得ることができる。According to this invention, the roughness of the Nl plating film 2 is 055 m
Since it is adjusted as follows, aluminum wire 1 and N
The bond between L Metsu II [2 and the lead frame 7 can be made strong, and deterioration due to aging etc. can be minimized,
Sufficiently high reliability can be obtained.

なお、本発明がトランジスタ、サイリスタ等のあらゆる
半導体装置や集積化半導体装置に適用できることは、容
品に通解されるであろう。It should be noted that it will be understood from the packaging that the present invention is applicable to all semiconductor devices and integrated semiconductor devices such as transistors and thyristors.

【図面の簡単な説明】 第１１１は電気的並びに化学的にめっきし九Ｎｉめつき
膜のあらさを測定した結果を示す図、第２図はＮ１めつ
き膜のあらさと、前記Ｎｉめつき膜に接合され九アルミ
ニウムワイヤのせん断強度との関係を示す図、第３図Ｆ
ｉＮｉめっき膜のあらさと前記Ｎ１めつき膜に対するア
ルミニウムワイヤの接合率との関係を示す閣、第４図は
Ｎｔめつき膜のあらさと前記Ｎ１めつｉ！膜に対するア
ルミニウムワイヤの接合面積との関係を示す図％第５図
は熱酸化し州ｌめっき膜のあらさと前記Ｎｉめつ自模に
接合されたアルミニウムワイヤの接合部のせん断強度と
の関係を示す図、Ｗ２Ｃ図はアルミニウムワイヤをボン
ディングした後の、Ｎｉめつき膜のあらさと接合部の経
時劣化との関係を示す図、第７図は本発明の半導体装置
の一実施例の断面図である。 １・・・アルミニウム（合金）ボンディングワイｆ。 ２・・・Ｎｌめつき膜、　　３・・・半導体ペレット、
　４・・・モールド、・レジン、　　７・・・ＩＪ　−
）”フレーム。 代理人弁理士　平　木　道　人 第１図 角２図 Ｎ１めフＶ頃りδうで（ＡＪｍ） 第３１！］ ’ＩＡｔ、　　図 Ｎ１かり曖Ｉ）がｙ　’！　（ＡＩｍ）第　５図 Ｎ１め、＝＊＊のｘＪ７ａ　　（ＡＪｎ）４７１１（ｈ
） ｖＪ７　口[Brief explanation of the drawings] Fig. 111 shows the results of measuring the roughness of the Ni-plated film electrically and chemically plated, and Fig. 2 shows the roughness of the N1-plated film and the Ni-plated film. Figure 3F shows the relationship between the shear strength of nine aluminum wires bonded to
Figure 4 shows the relationship between the roughness of the iNi plating film and the bonding rate of the aluminum wire to the N1 plating film. Figure 5 shows the relationship between the bonding area of the aluminum wire to the film and the roughness of the thermally oxidized plated film and the shear strength of the bonded portion of the aluminum wire bonded to the Ni film. The W2C diagram is a diagram showing the relationship between the roughness of the Ni plating film and the aging deterioration of the bonded portion after bonding aluminum wires, and FIG. 7 is a cross-sectional view of one embodiment of the semiconductor device of the present invention. be. 1... Aluminum (alloy) bonding wire f. 2... Nl plating film, 3... semiconductor pellet,
4...Mold, Resin, 7...IJ-
)"Frame. Agent Patent Attorney Michihito Hiraki 1st figure angle 2 figure N1 mefu V round δ arm (AJm) 31st! Figure 5 N1, =** xJ7a (AJn) 4711 (h
) vJ7 mouth

Claims (2)

【特許請求の範囲】[Claims] （１）　　半導体チップをリードフレーム上に固着し、
かつ半導体チップ素子上の電極とり−ドフレームとをア
ル１＝ウムワイヤにて肇絖した半導体装置において、上
記リードフレームはＮ１めつき膜でおおわれており、鋺
記Ｎ１めつき膜は、その表面あらさがＱ、Ｓμｍ以下で
あることを特徴とする半導体装置。(1) Fix the semiconductor chip on the lead frame,
In a semiconductor device in which an electrode lead frame on a semiconductor chip element is covered with aluminum wire, the lead frame is covered with an N1 plating film, and the N1 plating film has a surface roughness. A semiconductor device characterized in that Q, Sμm or less. （２）　　Ｎｉめつき膜は、電気的めっき膜であること
を特徴とする特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the Ni plating film is an electrically plated film.
JP56134026A 1981-08-28 1981-08-28 Semiconductor device Granted JPS5835950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56134026A JPS5835950A (en) 1981-08-28 1981-08-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56134026A JPS5835950A (en) 1981-08-28 1981-08-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5835950A true JPS5835950A (en) 1983-03-02
JPS6257257B2 JPS6257257B2 (en) 1987-11-30

Family

ID=15118634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56134026A Granted JPS5835950A (en) 1981-08-28 1981-08-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5835950A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6412563A (en) * 1987-07-07 1989-01-17 Sumitomo Metal Mining Co Nickel plating of lead frame
US5277356A (en) * 1992-06-17 1994-01-11 Rohm Co., Ltd. Wire bonding method
JP2011146477A (en) * 2010-01-13 2011-07-28 Shinko Electric Ind Co Ltd Wiring board, manufacturing method thereof, and semiconductor package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6412563A (en) * 1987-07-07 1989-01-17 Sumitomo Metal Mining Co Nickel plating of lead frame
US5277356A (en) * 1992-06-17 1994-01-11 Rohm Co., Ltd. Wire bonding method
JP2011146477A (en) * 2010-01-13 2011-07-28 Shinko Electric Ind Co Ltd Wiring board, manufacturing method thereof, and semiconductor package
US8673744B2 (en) 2010-01-13 2014-03-18 Shinko Electric Industries Co., Ltd. Wiring substrate, manufacturing method thereof, and semiconductor package

Also Published As

Publication number Publication date
JPS6257257B2 (en) 1987-11-30

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