JPS5835476A - Testing method for semiconductor ic - Google Patents

Abstract

PURPOSE:To simplify the test of a semiconductor IC by a method wherein an integrated circuit to be tested and a standard sample are tested simultaneously based on the same test pattern and the quality of the circuit is decided according to the result of the test. CONSTITUTION:When the data on a test of some item are delivered from a test pattern memory 1, they are inputted in input/output pin cards 7 and 8 through the intermediary of a timing selector 4, subjected to analog conversion therein and given to an integrated circuit 9 to be tested and a standard sample 10. The circuit 9 and the sample 10 are tested simultaneously, and the results of the test are digitized by the cards 7 and 8 and then compared by a comparator 11. A quality decision signal is delivered from the comparator 11, while the result of the comparison is stored in a memory means through a mother bus. When completion signals are inputted in a trigger means 12 from the cards 7 and 8, the means 12 triggers the selector 4. At this time, the data on a test of the following item has already been inputted in the selector 4 from the memory 1, and thus the subsequent test is conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing semiconductor integrated circuits. Functional testing of semiconductor integrated circuits has been conventionally performed. In other words, write test patterns that cover multiple test items in the test turn memory (as well as record the test results that would be obtained if the integrated circuit under test was tested according to the above test pattern). A pattern (hereinafter referred to as a standard pattern) is stored in the standard pattern memory.The integrated circuit under test is tested according to the test pattern output from the test pattern memory, and in synchronization with this. The test result is compared with a standard pattern stored in the standard pattern memory, and based on the comparison result, it is determined whether the integrated circuit under test is defective or not.

However, the conventional testing method described above has the disadvantage that the standard pattern must be stored in memory in advance, which requires time and effort to operate the program.

The present invention has been made in view of these points, and its feature is that a standard sample having the same configuration as one integrated circuit under test is used in place of the standard pattern memory.

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

The drawing is a block diagram showing an example of an apparatus for carrying out the test method according to the invention. In the figure, reference numeral 1 denotes a test pattern memory that stores test patterns having a plurality of test items, and the stored data is transmitted through the typewriter interface 2, the mother bus, and the test pattern menu interface 3. The input is from a paper tape reader (not shown) connected to a typewriter interface.

Reference numeral 4 indicates a timing selector for timing-processing the output signal of the memory 1, and the output signal of the selector 4 is applied to the input/output pin cards T and 8 in the integrated circuit under test unit 5 and the standard sample unit 6, respectively. The input/output pin card 7 converts the test and data output from the timing selector 4 into an analog signal and inputs it to the integrated circuit under test 9, and converts the test result of the circuit 9 into a digital signal. On the other hand, the input/output pin card 8 has the same function as the pin card 7 for the standard sample/pull 10. The standard sample has exactly the same function as the integrated circuit under test 9. It is a semiconductor integrated circuit having a configuration that has been tested in advance and determined to be a good product.

A comparator 11 compares the test results converted into digital signals by the input/output pin cards 7 and 8.

The test method according to the present invention is carried out as follows using the above-mentioned apparatus. That is, when the test data of the item to be stored is output from the memory 1, the data is inputted to the input/output pin cards 7 and 8 via the timing selector 4, where it is converted into an analog signal, and then
Each person is given the integrated circuit under test 8 and the standard sample 10. However, the integrated circuit under test 8 and 41j
1 Quasi-samples 10 are simultaneously tested according to the above data 2 and the test results are converted into digital signals by the pin cards 1 and 8 and then sent to the comparator 11.
is input. The ratio softener 11 compares the test results, and if the comparison results are the same, outputs a judgment signal of "good", and if not, outputs a judgment signal of "defective".

The results of this comparison are input to the test result storage means via the mother bus. When the test for the above-mentioned item is completed, a completion signal is output from the input/output pin cards 7 and 8, and these trigger means 12 for said timing selector 4;
Two inputs are entered. However, when the means 12 triggers the timing selector 4, the tasting data of the next item is inputted to the color line selector 4 from the pattern memory 1. Data is input via timing selector 4 to the human output bin cards T and 8. As a result, a test is performed on the test drive data for the integrated circuit under test 9 and the standard sample 10, and the test results are compared by the comparator 11 in the same manner as described above.

In this way, when all the tests for the test numbers programmed in the test turn memory 1 (turn O) are completed, the overall quality of the integrated circuit under test is determined based on the comparison result in the above comparison #11. Then, a new integrated circuit under test is tested in comparison with the standard sample 10 in the same manner as described in 1 above.

As described above, the semiconductor integrated circuit testing method according to the present invention involves simultaneously testing the integrated circuit under test and a standard sample (passing product) having the same configuration as the circuit, according to the same test pattern, and comparing the test results. Since the above-mentioned integrated circuit under test is determined to be good or bad by comparing the 411 [This test can be performed more easily and inexpensively, and is also advantageous in terms of hardware.

BRIEF DESCRIPTION OF THE DRAWINGS The drawing is a block diagram showing an example of an apparatus for implementing a semiconductor integrated circuit testing method according to the present invention. 1...Test pattern memory 2...
Typewriter/Interface 3/Paper pattern memory ◆Interface 4...Timing-
Selector T, 8... Human output pin card 9... Integrated circuit under test 10... Standard sample 11... Comparator 12... Trigger means. (7317J Agent: Patent Attorney Noriyuki Sae (1 person)

Claims (1)

[Claims] A standard sample having the same configuration as the integrated circuit under test and the circuit is simultaneously tested according to a test pattern that corresponds to a plurality of test items, and the integrated circuit under test and the standard sample obtained for the above valley test item are obtained. The test results were compared one by one, and from the comparison results, the quality of the above-mentioned integrated circuit under test was determined.
A method for testing a semiconductor integrated circuit, characterized in that it determines whether it is defective.