JPS5833607B2 - Head dirt detection circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a head dirt detection circuit.

In magnetic tape devices, during read/write operations on the tape, oxides generated by the tape itself and external substances such as dust tend to collect on the surface of the magnetic head.

This dust collection action tends to contaminate the head and lowers the read/write voltage of the head, causing reading and writing errors.

An automatic head cleaning device has been proposed as one method to solve this problem.

This head cleaning device removes dirt from the head by cleaning the head intermittently.

Conventional automatic head cleaning systems operate by moving a special tape relative to the head or by moving the head relative to a cleaner wiper.

In a manual head cleaning device, the head is cleaned using an abrasive tape or a brush.

The number of times these head cleaning devices (VC) clean the head is once every few minutes to several tens of minutes for automatic ones, or once every few hours in some cases, and for eight hours for manual ones. This is done every time the business starts, such as once every year.

In this conventional head cleaning method, the head is cleaned even though the head is not dirty, and the head is rubbed recklessly, causing damage to the head.

Do not clean the head even though it is dirty, or forget to clean the head.

Disadvantages include using a special head cleaning tape more than necessary, and stains that cannot be removed by an automatic head cleaning device alone.

In order to eliminate such defects, the head should be cleaned when it becomes dirty.

However, no clear means had been thought of in the past regarding how to detect dirt on the head or how much of a corner it should be before it should be cleaned.

In particular, the degree of contamination is difficult to accurately determine, as it is related to the amount of work involved in running the tape, the degree of contamination of the tape itself, and the degree of contamination of the room in which it is used.

This invention was made as a result of various experiments and research on the generation of head dirt and read voltage, focusing on the head read voltage due to head dirt, and its purpose is to provide a head dirt detection circuit. That's true.

An example of the configuration of the present invention to achieve this object is a system that includes a read signal level determination circuit, an internal block (gap) detection circuit, an abnormal block determination circuit, and a head dirt determination circuit, and detects head dirt. If the read signal of the head is higher than a predetermined signal level (for example, 0.8Vp-p), the read level determination circuit is positive in terms of the read signal level.
This circuit generates a first signal as a normal read signal, and generates a second signal as an abnormal read signal when the signal is lower than a predetermined signal level in terms of the read signal level.

The block (gap) detection circuit detects a signal corresponding to a block or IRG from the head read signal,
This is a circuit that generates detection signals corresponding to blocks.

The above-mentioned abnormal block determination circuit detects two or more of the first signals (
For example, the number of second signals between the number of detected signals (for example, 6) is counted, and when this count value reaches a predetermined number (for example, 32) or more, the block corresponding to the previous detection signal is regarded as an abnormal reading block. This is a circuit that makes a judgment and generates an abnormal reading block signal.

The head dirt determination circuit counts the number of abnormal read blocks by counting the abnormal read block determination signal, and determines that this count value is a predetermined number (for example, 12).
This circuit determines that the head is dirty when the above occurs and generates a head dirt determination signal.

In addition to the circuit described above, a circuit is further provided for determining the block corresponding to the detection signal as a normal read block when the count value of the abnormal block determining circuit is less than a predetermined number, and generating a determination signal for the normally read block. The judgment signal is sent to the previous head dirt judgment circuit, and the head dirt judgment circuit counts the number of judgment signals for the abnormal reading block between a predetermined number of consecutive judgment signals (for example, two) for the normal reading block. However, by determining that the head is dirty when this count value reaches a predetermined number and generating a head dirt determination signal, it is possible to perform dirt detection in a more appropriate dirt state. Become.

Next, specific embodiments of the present invention will be described with reference to the drawings, and specific contents of the invention will be clarified.

FIG. 1 is a block diagram of a head dirt detection circuit according to an embodiment of the present invention, and FIG. 3 is a diagram for explaining the relationship between head dirt status and read voltage.
It is a graph in which the horizontal axis represents the number of output signals of the normal/abnormal read signal determination circuit when the head read signal is sampled every 16 bits of the rad read voltage (p-p).

Similarly, this graph shows a portion from a state slightly before the head becomes contaminated to the point where the head begins to become contaminated.

In the graph, in part a, the graph is intermittent (read voltage) is 0.8 Vp-p or less.

This phenomenon occurs because dust or the like temporarily attaches to the head and then immediately separates from the head.

Part b is a graph in which a certain amount of dust, tape oxide, etc. has adhered to the head.

In the state of part b, when the head deposits reach a certain level of the placement plate, some of the deposits are moved away from the head by the movement of the tape, etc., and the read voltage of the head temporarily increases.

This state is indicated by 0 copies.

Furthermore, dust, oxides, etc. adhere to the head, and as the amount of adhered substances increases, the read voltage drops from the C state to 0.8 Vp-1) or less, and this state continues for a certain amount of time.

This state is the state of section d. The graph in Figure 3 is a typical graph; in some cases, the b part and the 0 part do not exist, and there is a transition from the normal read voltage state to the d part state, and after the d part state, It may temporarily be in the 0 part state and then be in the d part state again.

Further, the state of part b and part 0 may be repeated several times.

When examining the head in the d section of this graph, it is found that a considerable amount of dust, oxides, etc. have adhered to the head.

Based on this fact, we have invented a configuration example as shown in FIG. 1.

In FIG. 1, the signal from the Mihead readout circuit 1 is supplied to the readout signal level determination circuit 2, and here, the readout voltage is a signal of 0.8V (p-p) or more, but 0.8V (p-p) or more.
Determine whether the signal is less than 8 V (p − p ),
If it is 0.8V (p p) or more, the first signal corresponding to the read signal is generated as a normal read signal, and 0.
．． If it is less than 8V (p-p), a third signal corresponding to the read signal is generated as an abnormal read signal.

In this case, the first signal and the second signal may be made to correspond 1:1 to the head read signal, but they may also be sampled at an appropriate cycle and made to correspond n:1.

Differential amplifier and Schmitt trigger are used to judge the signal level.
It may be possible to perform this at a voltage level using a circuit or the like, or it may be performed at a current level.

The signal from the readout circuit 1 of the head is further applied to a block detection circuit 3.

The block detection circuit 3 generates a block detection signal when detecting a preamble or the like in the head read signal.

The block detection circuit 3 may detect a postamble signal or IRG (inter, recording, gap) and make it correspond to a block.

The detection signal of the block detection circuit 3 and the first and second signals of the previous read signal level determination circuit 2 are sent to the next normal/abnormal block determination circuit 4.

The normal/abnormal block determination circuit 4 has two internal counters, a first and a second counter, and counts the number of first signals and second signals.

The second counter that counts the second signal is cleared by the signal from the block detection circuit 3, and is also cleared when the first counter that counts the first signal counts a predetermined number.

This determination circuit 4 generates a determination signal as an abnormal reading block when the count value of the second counter exceeds a predetermined number, and the count value of the second counter in the block corresponding to the detection signal is less than the predetermined number. When , a determination signal indicating a normal read block is generated.

Here, the determination signal as the abnormal reading block can also be used as the n-th reverse output of the second counter.

The determination signal as an abnormal read block and the determination signal as a normal read block are supplied to the head dirt determination circuit 5, where the number of abnormal blocks or the number of abnormal blocks occurring between normal blocks is counted by a third counter. be done.

When the count value of this counter is greater than or equal to a predetermined number,
Head dirt determination circuit 5 generates a head dirt determination signal at terminal 6.

FIG. 2 shows a concrete circuit development of the embodiment of the present invention shown in FIG.

The read signal level determination circuit 2 includes a differential amplifier 21, a differentiation circuit connected to this amplifier, a variable power supply, and an inverter 2.
2, a counter 23, and AND circuits 24 and 25.

The differential amplifier 21 receives a readout signal at one input from the readout circuit 1 via a differentiating circuit, and this readout signal is applied to the other input at a variable constant voltage level (0.8V (p-p
) generates an output signal when it is at a higher voltage level.

This output signal is supplied to an AND circuit 24 via an inverter circuit 22, and directly to an AND circuit 25.

The counter 23 is a hexadecimal binary counter and generates an output pulse for sampling, for example, every 16 head read signals from the read circuit 1.

Note that the counter can be set variably.

This pulse output is then applied to AND circuits 24, 25, which sample the output of the differential amplifier 21 in response to the read signal.

What should be noted here is that when the button is pressed when there is no read signal from the read circuit 1 (i.e., where no data is written on the tape), this sampling pulse is not generated and the first and second signals are No judgment is made.

As a result, for each output of the counter 23, the AND circuit 25 generates a signal (first signal) corresponding to o, 5V (p-p, 1 or more read signals), and the AND circuit 24 generates a signal (first signal) corresponding to one or more read signals. , a signal (second signal) corresponding to a read signal of less than 0.8V (p-p) is generated.

Therefore, the first signal corresponds to a normal read signal of o, 5V (p p) or more, and the second signal is 0
．． This corresponds to an abnormal read signal of less than 8V (p-p).

Note that the counter 23 is not necessarily required as part of the read level determination circuit 2.

When generating either the first or second signal in response to the readout signal, the output of the readout circuit 1 may be directly supplied to the AND circuits 24 and 25.

In this case, it is preferable to increase the count value of the second counter 42, which will be described below.

The normal/abnormal block determining circuit 4 includes first and second counters 41 and 42, an OR circuit 43, a delay circuit 44, a flip-flop 45, and AND circuits 46 and 47.

The first counter 41 is a quaternary counter that counts the first signal from the AND circuit 25 as a normal read signal, and when it counts four, the output clears the second counter 42 via the OR circuit 43. .

The second counter 42 is a 32-decimal counter and the AND circuit 24
The second signal from the second signal is counted as an abnormal read signal, and when 32 signals are counted, an output signal is generated and the flip-flop 45 is set with this signal.

The first counter and the 20th counter are each cleared by a detection signal generated when the block detection circuit 3 receives a readout pattern for block detection, for example, a preamble, from the readout circuit 1 of the head.

In this manner, the number of abnormal read signals between four successive normal read signals corresponding to blocks is counted, and when the number of abnormal read signals reaches 32, a signal indicating an abnormal block is generated.

In this case, once the second counter counts 32, it is set to O.

Therefore, this output is supplied to a flip-flop 45 and stored.

In this case, if the maximum count value of the second counter is larger than the number of normal and abnormal read signals of one block,
It is sufficient to simply take out the output from the stage of a predetermined base number, and there is no need to store it in the flip-flop 45.

The flip-flop 45 is reset by the output of the block detection circuit 3 delayed by the delay circuit 44.

The Q output signal of the flip-flop 45 and the detection signal of the block detection circuit 3 are supplied to an AND circuit 47, and the Q output signal of the flip-flop 45 and the detection signal of the block detection circuit 3 are supplied to an AND circuit 46.

Here, if the flip-flop 45 is set between the previous block detection signal and the block detection signal read this time, the determination signal as an abnormally read block will be output in synchronization with the read block detection signal. If the flip-flop 45 is reset, a determination signal as a normal read block is sent to the 40th counter 52 in synchronization with the read block detection signal.

After this judgment signal is sent out, the flip-flop 45
It is set by the detection signal of the block detection circuit 3 delayed by the delay circuit 44.

At this time, the AND condition of the AND circuit 46 does not hold.

In this way, it is determined whether each block has been read out normally or not, based on the level of the readout signal.

Similarly, here, the first counter 41 is taken as an example of a quaternary counter, but this first counter 41 is deleted, the output of the AND circuit 25 is directly added to the OR circuit 43, and the 20th
The counter 42 may be cleared, and the second counter may count the number of abnormal read signals applied between two normal read signals.

The count number of the second counter is not limited to 32 either.

The head dirt determination circuit 5 includes a third counter 51, a fourth counter 52, an OR circuit 53, and a delay circuit 54.

The third counter 51 is an octal counter, and the AND circuit 4
Receives a judgment signal from 7 as an abnormal reading block,
The number of these signals is counted, and when eight signals are counted, a head dirt determination signal is sent to the terminal 6.

Further, this determination signal is applied to the OR circuit 53 via the delay circuit 54.

The fourth counter 52 is a binary counter and the AND circuit 46
It receives a determination signal as a normal read block from , counts the number of signals, and sends the output to the OR circuit 53 when it counts two.

Therefore, the head dirt judgment circuit 5 sends a head dirt judgment signal to the terminal 6 when the third counter 51 counts eight abnormal reading signals without including two or more judgment signals of normal reading blocks. .

The 30th counter 51 is cleared via the OR circuit 53 after a certain period of time after sending out the head dirt determination signal, and is also cleared by the output of the fourth counter 53.

The head dirt determination signal sent to the terminal 6 is supplied to a head cleaning device, an alarm device, or a corresponding circuit as sense information.

As a result, the head will be automatically cleaned by a head cleaning device, the head will be cleaned manually based on an alarm from an alarm device, or the software will provide a warning to the operator or statistical information.

The 40th counter 52 of the head dirt determination circuit 5 may be deleted, or may be limited to a binary system, such as a quaternary system, an octal system, or the like.

The fourth counter 52 can be set as a counter of various decimal numbers or deleted depending on the work situation and the dirt status of the head, so that it can be adapted to the dirt status of the head and dirt can be determined.

Sampling counter 23, first counter 4
The first and fourth counters 52 can be provided or deleted as appropriate depending on the level of contamination of the heads of magnetic tapes, magnetic disks, etc., differences in the number of read blocks due to differences in devices, and differences in the number of read bits. be.

Since the embodiment of this invention uses a counter, the first
By changing the count values of the second, third, and fourth counters, it is possible to realize a head dirt detection circuit that is compatible with various situations.

In the embodiment, if the fourth counter 52 is deleted, neither the AND circuit 46 nor the delay circuit 44 is necessary.

In this case, the third counter 5 of the head dirt determination circuit 5
1 simply counts only the number of abnormal read blocks.

In this case, as mentioned above, it is particularly effective to eliminate the flip-flop 45.

Note that the count number of the third counter 51 is not limited to eight either.

The head dirt detection circuit of the present invention may be connected to a readout circuit of a head corresponding to any track, but a particularly effective readout circuit is a readout circuit of a head corresponding to the second track counting from the outer track. Two head dirt detection circuits may be provided corresponding to the head reading circuits of the two upper and lower tracks, and a head dirt determination signal may be outputted via an OR circuit.

As detailed above, the present invention can provide a circuit that can detect dirt on a magnetic head, and by employing this circuit, it is not necessary to clean the head more than necessary, and damage to the head can be reduced. At the same time, it prevents the use of unnecessary leaning tape and reduces the burden on the operator.
It is possible to prevent read/write failures due to head dirt.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a head dirt detection circuit which is an embodiment of the present invention, FIG. 2 is a specific circuit configuration diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of the head dirt detection circuit. FIG. 3 is a diagram illustrating the relationship with the read voltage of the head. 1 is a head readout circuit, 2 is a readout signal level determination circuit, 3 is a block detection circuit, 4 is a normal/abnormal block determination circuit, 5 is a head dirt determination circuit, 6 is an output terminal,
21 is a differential amplifier, 23 41 42 51
2 TS 52
is a counter, 24 25 46 47 is an AND circuit, 4
3 and 53 are OR circuits.

Claims (1)

[Claims] 1. A first output signal is generated when the head read signal is higher than a predetermined signal level, and a second output signal is generated when the read signal of the head is lower than the predetermined signal level. a detection circuit that generates a detection signal corresponding to a block or a gap from a readout signal of the head; and a detection circuit that receives the first output signal, the second output signal, and the detection signal; The number of second signals divided between a predetermined number of output signals is counted, and when this count value reaches a predetermined number, the block corresponding to the detection signal is read and determined to be an abnormal block. ,
An abnormal block determination circuit that generates a determination signal; and a head that counts the number of determination signals, determines that the head is dirty when the count value reaches a predetermined number, and generates a head dirt determination signal. A head dirt detection circuit comprising a dirt determination circuit. 2. When the count value of the abnormal block determination circuit is less than a predetermined number, the block corresponding to the detection signal is determined as a normal read block, and a circuit is further provided that generates a determination signal corresponding to the normal read block, and this determination signal is sent to the head. The head dirt determination circuit counts the number of determination signals corresponding to abnormal read blocks between a predetermined number of successive determination signals corresponding to normal read blocks, and determines whether this count value is a predetermined value. 2. The head dirt detection circuit according to claim 1, wherein the head dirt detection circuit determines that the head is dirty when a number of the head dirt is detected, and generates a head dirt determination signal.