JPS583342A - Flag synchronizing system - Google Patents

Abstract

PURPOSE:To prevent the missing of data and to improve the reliability with a frequency drift of a base band signal, by discriminating the base band signal surely and performing flag synchronism. CONSTITUTION:The input of a base band signal BBS from an A/D conversion section 2 is discriminated with an internal input/output circuit IO1 of an input/ output processing section 3, data is obtained with a sampling pulse from a programmable timer module 5, demodulation is performed at each synchronizing signal clock from the module 5 and the result of discrimination is obtained. Next, the sum of the result of discrimination is obtained and a BBS signal value is inputted to a flag detecting section 4 with a synchronizing signal clock via a bus 7. If the synchronizing error is greater than a half period at the detecting section 4, the clock is split and the correcting operation corresponding to the BBS of the clock is performed, the sure flag synchornism is taken and the data missing due to frequency drift can be prevented for the BBS signal. A microcomputer is used for the processing section 3 and the detection section 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rounding flag synchronization method in which a baseband signal value is determined from sampling data, a synchronization error is extracted, and flag synchronization is performed in a modulation/demodulation device using a digital signal processing format. It is something.

For example, when demodulating a P8K (frequency shift keying) signal by digital signal escape, each demodulated data is usually sampled m times (m>2), and the m times of tenbling is performed. One predetermined sampling value of the data is adopted as the demodulation result.

However, the baseband signal obtained by demodulating the FSK signal using a demodulation path using a phase-locked loop circuit (so-called PLL), etc., suffers from a frequency drift due to jitter in one of the demodulation circuits. Data loss may occur in the demodulation result.

In other words, when the frequency drift of the baseband signal is larger than the specified value and the predetermined sampling position to be adopted as the demodulation result is close to the change point of the baseband signal, the loss of one data is particularly likely to occur. .

This will be explained according to the timing f-) of an example of baseband signal sampling shown in Fig. Jl1.

This example shows the case where m = x 4 as described above, and the baseband signal BB8 (for example, data...101...
The period T of #) is shorter than specified, and the data determination position DP of the sampling pulse SPP to be adopted as each data value of the baseband signal BB8 is the data "
Since it is not included in the period of 0#, the sampling pulse SP
The sampling data by P, the data of the data @O'' part in the data 8PD, are not extracted, resulting in the data being missing.

The above applies not only to the case of F8KI, but in general.
This is always the case for baseband signals that have a frequency rIi number drift.

Therefore, if there is a frequency drift in the sampling data of the baseband signal that is close to the change point of the baseband signal, errors like the above Q are likely to occur, so the data period of the baseband signal is It is said that the sampling result near the center should be used as the baseband signal value.

On the other hand, the modulator/demodulator AT (the so-called DCE before the modem) needs to send a rounded synchronization signal clock that is read by the DTE along with the obtained transmission result to the data terminal (so-called DTE). The clock must be synchronized with the baseband signal resulting from demodulation, and DCEs typically do this using edge synchronization or flag synchronization.

Figure M2 is a time chart when data loss occurs in an example of the conventional flag synchronization method, and is
This is the case where m = flea.

Baseband signal BBS (for example, data "...1"
011...") is the sampling pulse S PPK,
Therefore, the sampling data 8P
D is for each data of baseband signal BB8, pulse data 11'' of Hl for @11#, and 10
``5m pulse data @IO# has been obtained for K.

The clock CLK has the same period as the baseband signal BB8 (To') and has a pulse ratio of 50%. At the falling edge of the pulse, the clock CLK gives the demodulation result DMD data rewriting signal, and after a predetermined number of seconds (To'), the pulse ratio is 50%. In the diagram, the sampling pulse position of the third pulse (that is, the center position of one cycle) is the data determination position DPO, DPI, DP2 . DP3
It is set so that

Note that the rising edge of this pulse provides timing when the DTE compensates for the demodulation result DMD.

In this case, the synchronization signal CLK has a synchronization error Tp with respect to the baseband signal BB8, which must be corrected.

Therefore, the data @0# of the baseband signal BB8 becomes a changing point in relation to the data "1#" before and after it, and as is well known, edge synchronization (flag synchronization) occurs here. must be done.

That is, the demodulation result D at the data determination position DPI, DP2
After determining the data 11'' and 10# of the first part of the MD, the rise of the synchronization signal clock CLK must be delayed by the synchronization error Tp from point A to Bat.

In this case, the synchronization error T? Since is larger than 1/2 period,
Data following data 10” of baseband signal BB8 @
l# is dropped, and the next data ""1' is the demodulation result D
The MD data becomes 11''.

Note that when the synchronization signal clock CLK is applied once, the synchronization I@-difference T
Since it was corrected to be delayed by p, the demodulation result DMD
The duration of the data @0# is extended to a full length by adding the above synchronization error TP to the original period.2 In this way, the conventional method does not cause data loss in the rounding that synchronizes the flag. If the data cannot be obtained, this will cause problems with the reliability of the received data.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a 72G synchronization method that can reliably determine baseband signal values and perform flag synchronization.

The 4I feature of the present invention is to determine the baseband signal value for each period of the synchronization signal clock from all the sampling values for that period, and extract the synchronization error, and if this is larger than the half period, the By dividing the error into a predetermined number of subsequent cycles and performing synchronization, the nine-flag synchronization method enables synchronization using flags without causing data loss.

The principle of flag detection will be described in detail below with reference to the time chart of the flag detection raw salt according to the present invention shown in FIG.

First, it is assumed that sampling is performed m times for each period of the baseband signal BB8, the modulation rate of the baseband signal is f-, and the rate of the sampling pulse 8PP is fly.
Then, fly-rnf@...(1
).

Furthermore, with respect to an arbitrary point in time of the synchronization signal clock CLK as a reference, the demodulation determination result for each synchronization signal clock CLK in the n-th period from there is calculated using 84(11)(
1-1 to m), and if ``0'' of sampling data 8PD in that period is Δ(rl), then Δ(n)xm-(8t(n)+-+8m(n))
...(2), which is the synchronization signal clock C
This shows where within one cycle of LK there is an etch (rising edge, falling edge) of the demodulation result DMD of the baseband 1δ BBS.

Preferably, if the baseband signal value for the nth period of the synchronization signal clock CLK is d (n), then it is defined as -.

That is, when ``0'' occupies the majority of m@ sampling data SPD for each cycle, 10# is adopted as the baseband signal value de), and @
If 1" is the predominant value, I would like to adopt 11" as the baseband signal value d(n).

The flag detection method will be explained below, but the above formula (
In the definitions 3a) to (3C), there is a possibility that a data error may occur in the demodulation result DMD.

That is, for example, if the baseband signal BB8 is as shown in (1) in FIG. 3, and the sampling data 8PD for it is shown in the same figure, then
If d (n −1) = 1, j(n) = 4 to dF) = 0. From Δ(n+1)=5 to d(n
+1)=0 occurs repeatedly for each flag period TFic.

The present invention attempts to perform accurate 1iK flag detection in consideration of this point, and assumes that the following conditions are satisfied.

b(1/fs-1/(fm+Δfa))<
<Cm1a]-x>・tap ,,, (4) That is, jfs/fs<1/(b・m/((m/4 E −1)
-1) (5) Here, Δf- is the maximum frequency drift width of the baseband signal BB8, b is the number of bits of the flag signal, and m≧8. In addition, [ ] means marriage with the gakusu symbol.

Equation (5) means that for one flag,
This means that the drift length of the jIilrIL number drift must be smaller than the sampling period 1/flPo((m/4)-1> times).

If this condition is satisfied, the flag can be detected as follows. That is, (1) d (n-1)
=o, Δ(n)+m/z, d(n)---...
=d (1+5)=1, O<j(n+5)km
/2 is a flag.

(If) d (n −1) −〇, d(n)=−
・=d (n-1-5)=1. Δ(n-f-5) ”0
If d(n+6)=0, then it is a hook.

(iii) Δ(”-1) field 0.Δ(n)=-...-
i (n + 41, 0, and Δ(fil5)≦[
:3ffl/4], it is a flag.

θV) Cases other than the above (1) to (fil) are not flags.

First, regarding flag detection, the case that is unrelated to the above equation (3C) is the above detection condition <1), (it), and the -
As an example, the baseband signal BB8 has a waveform (d
), (+) There are cases as shown in (+) (The illustration of the Sangli puffer data SPD for these is omitted. The same applies to waveforms (b) and (C).)

That is, in the case of waveform (d), d(n-1)-o
, i (11-1)-s, d(n)=-=d (n
+s)-1, Δ(11+5)-3, and in the case of waveform e), d(i-1)〉Q, Δ(n-1)==x8.
Δ(n)=1, d(n)=,・=(i (n+5
) =1, Δ(n+5)−0,d(1m+6)=
0. j (In+6)=σ, and the above detection condition (i
), (II) may be satisfied and detected as a flag.

Next, considering the case related to the above formula (3C), in this case, there is a possibility that the data m is as described above, but
Regular flags, e.g. “01111” specified in CCITT (International Telegraph and Telephone Consultative Committee) Recommendation T30
A case will be explained in which 8 bits of 110'' are sent.

In this case, Δ(El-1)! qO,a(n)−Δ(1'
l+1)−...=Δ(n+4)=0 is detected,
It is assumed that the relationship expressed by the above formula (3c) exists.

In this case, the following relationship generally holds true.

b(t /l■-1/(fs+jf1<k/fat
...If (6), then J(fl)ri0,
J (n+1) b@Q, 1Δ(n)−4(
1+I) I≦k ,,, (7) Here, $≦
It is b-2.

That is, 1Δ(El-1)−Δ(fi+5N≦[m/
4]-1, holds, and d (It-z
)=o, i (n-1)=m/l, d(n-13-
1, Δ(1m) = ・=Δ(In+4>=O, then 1Δ(rl-1)-Δ(n+May≦(m/4)-x, (m/4)+1≦j (11+5)≦('In/4)-1
This will be detected as the p1 flag.

9, Δ(n-x)! qm/z, J (b) =...J
(n + 4) - 0 (also in case of D, j (n - 1) > m
/2, d (n −1) −0, d(n)z・=
= d (n-)-4) = 1, then the round line Δ(1m
The same applies when +5)≦(3m/4).

Furthermore, when Δ(In+5)>[8m/4), the increase due to frequency drift is m/2-(ffl-C3m/4), )=(3m
/4)-ffl/2≧(m/4)-1! D, Cm/4)-1, but the formula (
4) From the condition of t or (5), the maximum shrinkage width is [m/
4) It becomes smaller than -1, which is contradictory.

Therefore, even if i (nt)>m/z, it will be reliably detected if a regular flag is sent.

9, and even in the case of Δ(n-1)<m/2, d (
n-z)=o, d(nt)=1, d(n)
=...=d(In+4)-1, so J(In+
5)>(3m/4), l, 6, d (n+5)
-0〇〈Δ(1+4)＜m/2, the above detection condition (1
), the flag is detected by Δ(In+5)≦(3
m/4], the flag is detected according to the detection condition (II).

-Finally, even if there is a risk of detecting something that is not a flag as a flag, the condition of formula (3c) above should be used for determination.
When "011111G" with 7 pits was sent, Δ(1-1))0. Δ(n)=...=ノ(n
If +4)=o, the equation (4) is based on ω), and Δ(11+5)≧m−Cm/4)+1=(3m/4)+
1, it does not meet the detection condition (lit) and the same (i
v) It is not determined to be 7 lags due to K. As this Oka,
Waveform (b) in FIG. 3 is used, Δ(n −1)=8. j(
n+5)=7. ” Also, as a fun nine flag, “0011111
When 8 bits of 0” are sent, o Δ
An example of the possibility that (n+5)<m/l is the waveform (C) in Figure 3. In this case, d(n-1)=0,
ti(n)=-=d(n+s)-1, but j
(n)=xx m/2, so the detection condition (
1) and is not determined to be 7 blowfish by f, fiiill (IV).

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 shows an implementation 111 of the flag synchronization method according to the present invention.
Figure S is a block diagram of the main parts of the system, and Figure S is its time chart, Figure 6 line, and its flowchart.

Here, 1 is a digital/analog converter CD/A) that converts the baseband signal BB8 into an analog modulated signal and sends it to the line LINE, and 2 is a baseband signal that receives the analog modulated wave from the line LINIC. The analog/digital converter (A/D) that performs BBSK conversion, a, is
An input/output processing unit that determines the data (baseband signal value) of the baseband signal BBS, extracts synchronization errors, and performs predetermined processing using a digital signal processing method; 4 is a 7-lag verification unit that also uses a digital signal processing method; These two are, for example, CPUI and CPU, respectively.
2 (central processing circuit), ROMI.

ROM2 (read only memory), RAMI.

RAM2 (random access memory), IOI.

+02 (internal input/output circuit), etc. 1 uses a microcomputer, 5 is a PTM (programmable timer module) that generates various tie ink pulses,
6 is a foreign output unit (10), 7 is a path for data and address, and 8 is an interface path for the DTg.

First, the operation of data judgment and synchronization error extraction will be explained.

The input/output processing section 3 converts the analog/digital conversion section 2 to the IOI from the baseband No. 1 BBS (for example, '...
・101...”) is inputted or not.
Block 10) in figure (a), if it is input,
Sampling data 8PD is obtained by sample #P supplied from PTM5, and demodulated for each synchronization signal clock CLK supplied from PTM5, and the determination result 8i(n) is obtained (block 11).

Next, the sum of the judgment results 5t(11) is calculated (block 12), and the required predetermined number m (the number of samplings for each period of the baseband signal <, in the JIE s diagram, Ifl
:l+10) and judge whether the sum is 9 or not (
Same as previous block 13).

When this is completed, the above sum and m/2 are added to the north wall (block 14), and the baseband signal value d (n) is set to a predetermined value (block 15).
, 16.17).

Also, subtract the sum in block 13 from the above m, and use this as the interval of "0" of the sampling data 8PD, and block 18), blocks 15, 16
．． In step 17, the obtained value is output together with d(n) to the flag verification unit 4 via path 7 (block 19), and the above operation is repeated every cycle.

Note that, as shown in the figure, the synchronization signal clock CLK has a synchronization difference Tp with respect to the baseband signal BB8, so this is also detected and sent to the flag verification section 4.

On the other hand, in order to correct the synchronization error TP which is larger than half a cycle, the flag verification section 4 sequentially divides the subsequent pulses of the synchronization signal clock CLK into two pulses, τ1. T
Since it is reduced by 2, even if the synchronization error TP is larger than half a period, the next @1 of data 10# of baseband signal BB8
# is missing8. A normal demodulation result DMD is obtained without being dropped and sent to D'l'E.

Note that the synchronization signal clock CLK, data determination position DPO
Other effects such as ~pP3 are exactly the same as those explained in FIG. 2.

Next, the synchronization operation and flag detection operation in the flag verification section 4 will be explained in more detail.

Bit displays for synchronization correction (display 1), (display 2), and (display 3) are provided according to each process of error correction operation.

In other words, (display 1) shows that when the synchronization error is larger than half a period, for example, when the synchronization error is divided into two times and corrected, the synchronization signal clock CLK is changed to [Δ(r
(Display 2) indicates whether or not the next cycle is shortened by l)/2) under the above-mentioned detection condition (1).
, (displays whether or not flag detection has been performed by old) (Display 3) indicates whether or not the same detection condition (Iil) is satisfied.

Hereinafter, data d(n) is generated at the nth period in FIG.

Δ(n) has been input! The following description assumes that flag detection is performed for the (1m+1)th cycle and a synchronous operation is performed.

First, (display 1) is 11# to judge whether or not to get married.
If block 2G) in Figure 3) is "1", the synchronization signal clock CLK is set to Δ(fi-1)-(Δ(n-1)/2).
(block 21), immediately read the data d (n) and Δ(n) if it is not @1",
When the flag detection conditions (1) and (if) described above are satisfied,
(Display 2) is set (block 22).

Next, it is determined whether (display 3) is 11# (block 23), and if it is "1", it is further determined whether the data is Δ(n)≦Cam/4). If not, check (Display 3).
Clear.

Accordingly, with the judgment result of block 23 above (display 3)
In addition to the case where is not I''1'', it is necessary to judge whether (display 2) is @1# or anzu (block 26), when it is '''1#, and the judgment result in block 24 is negative. Sometimes, it is determined whether or not the depth pW'(n)≧-/2 (block 27).

If the judgment condition is satisfied, the synchronization signal clock C
Shrink by LKtm-Δ(n) (block 28 in the same way)
.

When the determination result is negative, the synchronization signal clock CLK
After shrinking by [Δm/2] (previous block), (display 1) is set (previous block 30).

9. If the judgment result of block 26 is negative, then Δ(n-5)'Ice, Δ(1-4)=...=
When Δ(n)=0, (display 3) is set (block 31).

Upon completion of the operations of the blocks 28, 30, and 31, data d(n+1), Δ(
1m+1), and the operation of this cycle is ended (block 32 in the same example).

In this way, seven lags are detected every cycle, and the synchronization of the synchronization signal clock CLK is corrected.

Note that the above synchronization correction is performed in two cycles, but due to design reasons, this is done in three cycles.
It is clear that this can be done in divisions over more than one period.

As explained above in detail 11, according to the present invention, it is possible to reliably determine the baseband signal value and perform flag synchronization, so data is not lost due to frequency drift of the baseband signal, etc. , a remarkable effect can be obtained in improving the reliability of the flag synchronization method.

[Brief explanation of the drawing]

! Figure s1 is a time chart of an example of baseband signal sampling, Figure 2 is a time chart of a case where data loss occurs in the conventional 7-lag synchronization method, and Figure 3 is a flag detection principle according to the present invention. FIG. 4 is a block diagram of the main part of an embodiment of the flag synchronization method according to the present invention, FIG. 5 is a time chart thereof, and FIG. 6 is a 70-cheat diagram. 1... Digital/analog conversion section, 2... Analog/digital conversion section, 3... Input/output processing 1111.4
...Flag verification department, 5...Programmable tie! Module, 6... External input/output section, 7... Path, 8.
...Inter (1 other person J Kaya 4 mouths!! P50

Claims (1)

[Claims] 1. In a flag synchronization method for a modulation/demodulation device using a digital signal processing format, a baseband signal value for each cycle is determined from all sampling values in each cycle of a synchronization signal clock, and the synchronization - The turtle extracts the difference, and if it is larger than the corresponding cycle, the turtle divides the error into a predetermined number of subsequent cycles and synchronizes, thereby avoiding data loss. A flag synchronization method is characterized in that it allows the following operations to be performed. 2. A 72-gram synchronization system according to claim 15, in which the input/output processing section and the flag verification section of the modulation/demodulation device are configured using a microcomputer.