JPS583319B2 - read-only memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read only memory (hereinafter referred to as ROM), and in particular to an MIS type FET (Meta1-Ins FET).
ulator-Semiconductor type Field
The present invention relates to a ROM constituted by a field effect transistor (hereinafter referred to as FET) such as a d-effect-transistor.

In general, ROMs composed of FETs are often used in practice.

Figure 1 shows a commonly used ratioless ROM.
FIG. 2 is a block diagram for explaining.

Note that this ROM and its peripheral circuits are built into a semiconductor integrated circuit device (hereinafter referred to as an IC device).

In the figure, 1 is a ROM, which is composed of a precharge circuit 2, a memory circuit 3, and a column selection circuit 4 connected by conductive regions L1 to Ln of a plurality of semiconductors having a predetermined conductivity type arranged in parallel in a semiconductor substrate. It is configured.

Further, 5 is an address decoder, and row selection lines R1 to R
n are connected, and these row selection lines R1 to Rn and conductive region L1
~Ln form a matrix in the memory circuit 3 section.

Further, OUT is an output terminal connected to the column selection circuit 4.

In the ratioless ROM shown in FIG. 1, a precharge circuit 2 applies an output voltage to each of conductive regions L1 to Ln arranged in parallel in a memory circuit 3, and pre-charges each conductive region to a constant voltage. It works like a charge.

Further, the address decoder 5 has a decoding function, performs decoding based on the row designation input signals D1 to Dn, and outputs a decoded output to one of the row selection lines R1 to Rn.

Therefore, for example, when three row designation input signals D1 to D3 are manually input to the address decoder 5, 23-8 kinds of outputs are obtained as decoded outputs, and eight row selection lines R1 to R8 are obtained.
You can get different outputs.

The decode output derived from any of the row selection lines R1 to R8 is applied to the memory circuit 3.

This memory circuit 3 is configured in advance in a matrix form formed by row selection lines R1 to Rn and conductive regions L1 to Ln.
By configuring the circuit using ET or the like, desired information set by a program is stored.

Further, the column selection circuit 4 is applied with column selection input signals A1 to An, and selects a plurality of conductive regions L based on this signal.
It has the function of selecting a pair of conductive regions adjacent to each other from 1 to Ln, and connecting one of the pair of conductive regions to an output terminal and the other to a reference potential point such as a ground potential.

That is, in this ratioless ROM, after precharging the conductive regions L1 to Ln by the precharge circuit 2, the decode output from the address decoder 5 to the row selection lines R1 to Rn by the row designation input signals D1 to Dn and the column designation are performed. Based on input signals A1 to An, information preprogrammed in the memory circuit 3 by FETs etc. is transferred to the column selection circuit 4.
The output terminal OUT is connected to the output terminal OUT.

The operation will be explained using a specific circuit of the ratioless ROM shown in the block diagram of FIG.

FIG. 2 is a specific circuit diagram showing an example of a conventional ROM.

In the figure, the same or corresponding parts as in FIG. 1 are given the same reference numerals.

Note that this conventional circuit shows a ROM in which eight columns B1 to B8 are formed by nine conductive regions L1 to L.

Furthermore, all of the conventional circuits are shown using P-channel FETs.

In the conventional circuit shown in this FIG. It is composed of FETs (QPI) to (QP9).

A clock signal φ is applied to the gate electrode of each of these FETs (Q.P1) to (Q.P9), and in response to this clock signal, the conductive regions L1 to L are connected to the power supply voltage VDD. It has the role of charging.

Next, the memory circuit 3 is a P-channel type FET (QMI
) to (QMn), each of which is connected between a pair of adjacent conductive regions among the conductive regions L1 to Ln at preprogrammed positions so as to store desired information. .

Decode outputs decoded by the address decoder 5 based on the row designation input signals D1 to Dn are applied to the respective gate electrodes of these FETs (QMI) to (QMn) via row selection lines R1 to Rn. There is.

In this memory circuit 3, a preprogrammed FE
It has the role of connecting or separating adjacent conductive regions, respectively, depending on the positions of T(QMI) to (QMn) and the decode output based on the row designation input signals D1 to Dn applied to their gate electrodes. There is.

Furthermore, the column selection circuit 4 is a P-channel type FET (Q8
1) to (QS2o), and are driven by six column designation input signals A1 to 80.

Signal A1 is applied to the gate electrodes of FETs (Q81) to (Qs4), signal A2 is applied to those of Q85 to Qss, Qs,
~Qs,1 has signal A3, Q81L~Q815
A signal A4 is applied to those of Q816 to Qsts, A is applied to those of Qszo and Q82G, and a signal A6 is applied to those of Q82G.

Also, FET (Q81), (Q812) and (Qsta
) are connected in series between the conductive region L1 and the reference potential terminal 7 to which the reference potential ■SS is applied, and the FET (Q8
2) and (QS13) are the conductive region L2 and the output terminal oU
Between T, FET (Qss) and (Qs1o)
is a FET (Q) between the conductive region L3 and the terminal T.
84) and (Qs9) are the conductive region L4 and the output terminal OU
FET (QSIO) M and (Qsty
) between the conductive region L5 and the terminal 7, the FET (
Q85) and (QSII) are FETs (Qsa) and (QS
20) is the FE between the conductive region L7 and the terminal 7.
T(Qs7) and (Q814) are FET(Q8s)t(Q8
15) and (Qsts) are connected in series between the conductive region L9 and the terminal 7, respectively.

That is, every other conductive region Lt, El3, L5, L7t, and L9 among the nine conductive regions L1 to L are each FE
The remaining conductive regions L2jL4jL6 and L8 are connected to the reference potential terminal 7 through the series connection body of the FET.
It is connected to the output terminal OUT via a series connection body.

The column selection circuit 4 selects a pair of adjacent FETs, one of which is connected to the reference potential terminal 7 and the other to the output terminal OUT, by turning on a predetermined FET in accordance with the column designation input signals A1 to A6. It has the role of selecting a conductive region.

The operation of the conventional circuit shown in FIG. 2 constructed in this way will be explained.

In this conventional ROM, by first applying a clock signal, the FET (
QPI) ~ (QP9) are made conductive, and conductive regions L, ~
Power supply potential VDD is applied to L9.

Thereafter, by cutting off the clock signal DA, the conductive regions L1 to L9 are precharged to the power supply potential DD.

Next, a pair of conductive regions adjacent to each other are selected by the column selection circuit 4, and one predetermined column is selected.

For example, from among the column designation input signals A1 to A6, the signal A1,
When A4 and A5 are low potential level signals (hereinafter referred to as L level signals), FET (QSI) to (QS4)
and (Qs12) to (Qs18) become conductive, the conductive region L1 becomes the reference potential terminal 7, and L2 becomes the output terminal OUT.
Conductive regions L1 and L2 adjacent to each other and connected to each other are selected.

In other words, column B1 is selected.

Subsequently, in this state, in the memory circuit 3, if a decoded output is derived from the address decoder 5 to the row selection line R1 based on the row designation input signals D1 to Dn, the FET (QM1) forming the memory circuit 3 becomes conductive, and the pair of conductive regions L1 and L selected by the column selection circuit 4
2 is connected.

Therefore, the FET(QS12)t(Qs2), which is interposed between the output terminal OUT of this ROM and the reference potential terminal 7,
(QM1), (Qs1), (QS12) and (Q8.6
) are all conductive, and the output terminal OUT has the reference potential VSS.
will be read out.

In addition, in this state, in the memory circuit 3, the FET to which the decoded output is applied from the address decoder 5 is connected to the column B1.
For example, when a decoded output is derived from the address decoder 5 to the row selection line R2, the pair of conductive regions L1 and L2 selected by the column selection circuit 4 are separated.

Therefore, the output terminal oUT and the reference potential terminal 7 are separated, and the precharged power supply potential VDD is read out to the output terminal OUT.

Similarly, in the column selection circuit 4, the column designation input signals A1 to A6 are set to A1 and A2, A3 and A4, and A5 and A6.
By dividing the FETs into three groups of two and making three signals from each group L level signals, a predetermined FET is turned on, and one is connected to the output terminal OUT and the other is connected to the reference potential terminal 1. A pair of mutually connected conductive regions adjacent to each other is selected.

That is, only one column is selected from columns B0 to B8.

Next, in this state, there is an FET connected between the pair of conductive regions selected by the column selection circuit 4 in the memory circuit 3;
Moreover, the power supply potential VDD or the reference potential V8S is read out to the output terminal OUT depending on whether the decoded output from the address decoder 5 based on the row designation input signals D0 to Dn is led out to this FET.

As described above, in the ROM shown in FIG. 2, after the conductive regions L1 to L9 are precharged by the precharge circuit 2, the row selection lines R1 to Rn are input from the address decoder 5 by the row designation input signals D1 to Dn. The memory circuit 3
The information programmed in advance by the FET is delivered to the output terminal OU.

By the way, the conventional circuit shown in FIG. 2 is an example of a ROM, and has 8N bits, which is the product of 8 columns and N row selection lines R0 to Rn. ing.

However, ROMs are generally configured so that information of several hundred to several thousand bits can be read out.

Therefore, based on the conventional circuit configuration shown in FIG.
When the number of bits of OM is increased, and the number of columns is increased, that is, the number of conductive regions is increased, the number of FETs forming the column selection circuit 4 increases, and a potential is derived to the output terminal OUT. As a result, the number of FETs to be passed through increases inevitably, which limits the discharge rate and makes high-speed operation impossible.

Further, in the address decoder 5, a row designation input signal D
When the number of row selection lines R1 to Dn is increased, the number of row selection lines R1 to Rn from the address decoder 5 increases, and accordingly, the number of FETs forming the memory circuit 3 also increases. ~The capacitance for Ln increases, and the output terminal OUT
The speed at which the potential is derived will decrease.

Therefore, in order to operate the ROM at high speed, the column selection circuit 4
In order to improve the mutual conductance gm of the FETs constituting the FETs, it has become necessary to apply a large voltage as the column designation input signals A1 to An.

However, when a large voltage is applied as the column designation input signals A1 to An, a disadvantage arises in that the power supply voltage margin is impaired.

Therefore, in order to realize a ROM that can operate at low voltage and at high speed, it is necessary to increase the mutual conductance gm of the FET constituting the column selection circuit 4 so as to avoid the above-mentioned drawbacks.

Therefore, based on the relationship of formula [1] below, the column selection circuit 4
It has been considered to increase the mutual conductance gm by increasing the channel width of the FET constituting the FET.

However, in equation [1], μ is the electron mobility, W is the channel width, l is the channel length, εox is the dielectric constant of the gate oxide film, tox is the thickness of the gate oxide film, VG is the gate applied voltage, th is a threshold voltage.

However, when the channel width W of the FET constituting the column selection circuit 4 is increased, the ROM of FIG. 2 shown in FIG.
As is clear from the pattern diagram of a part of the circuit, the distance between adjacent FETs in the column selection circuit 4 becomes narrower, and the distance between adjacent conductive regions also becomes narrower, which causes punch-through. Sometimes I put it away.

In order to prevent this, if the interval between adjacent FETs in the column selection circuit 4 is increased, the pattern size is increased, which is a disadvantage.

In addition, in the pattern diagram shown in FIG. 3, the conductive region L
1 to L3 are diffusion regions formed by diffusion of impurities into the semiconductor substrate, and row selection lines R1 and R2 and column designation input signal lines A1jA2 are gate electrodes formed of electrode metal such as aluminum. and wiring.

Further, in FIG. 3, the same or corresponding parts as in FIG. 2 are given the same reference numerals.

Further, FIG. 4 is a specific circuit diagram showing another example of the conventional ROM.

In the figure, the same or corresponding parts as in FIG. 2 are given the same reference numerals.

Note that also in this conventional circuit, the nine conductive regions L1 to
L9 shows a ROM having eight columns B1 to B8, and further shows a case in which a P-Nayannel type FET is used.

The conventional circuit shown in FIG. 4 is similar to the ROM shown in FIG.
This is a modification of the configuration of the column selection circuit 4 shown in FIG.

That is, the column selection circuit 4 in the ROM shown in FIG.
It is a circuit configuration composed of 24 P-channel type FETs, each connected between adjacent conductive regions, the conductive region L1 is connected to the output terminal OUT, and the conductive region L is connected to the reference potential terminal 7, respectively. 6 column designation input signals A1
~A6 drives each FET.

Specifically, the column designation input signal A1 is applied to the gate electrode of each of the FETs (QS4]) to (Q844), and the column designation input signal A1 is applied to the gate electrode of each of the FETs (QS4]
45) to (QS48), the signal A2 is connected to the FET (
QS49) to (Q852) have signal A3, and FE
For those of T(Q853) to (Qsse), signal A4 is
Signal A5 is used for FETs (QS57) to (Qseo).
However, the signal A6 is added to each of the FETs (Q861) to (QS64).

In addition, FET (QS45) t (QS49) and (Qse
t) is the FET (Q
S46) t(QS50) and (Qsi7) are L2 and L3
Between L3 and L4, FET (QS47) t (Q853) and (QS58)
Q848), (QS54) and (QS62) are L4 and L
5, FET(QS41)t(Qsss)
and (QS63) is the FET between L5 and L6.
(QS42)t(QS56) and (QS59) are FETs (QS43)t(QS51) between L6 and L7.
) and (Qseo) are FE between L7 and L8.
T(Qs44), (QS52) and (Qsa+) are L,
and L, are connected in parallel.

This column selection circuit 4 turns off predetermined FETs in response to column designation input signals A, ~A6, so that two adjacent FETs, one of which is connected to the reference potential terminal 7 and the other to the output terminal OUT, are connected to each other. This is a circuit that selects a pair of conductive regions.

The operation of the conventional circuit shown in FIG. 4 in which the column selection circuit 4 is constructed in this manner will be explained.

In this conventional ROM, as in the ROM shown in FIG.
conduction, the conduction region L1 to LSK power supply potential VDD
is given.

Thereafter, by cutting off the clock signal D, the conductive regions L1 to L8 are precharged to the power supply potential VDD.

Note that the conductive region L9 is connected in advance to the reference potential terminal 7, and has the reference potential VSS.

Next, a pair of conductive regions adjacent to each other are selected by the column selection circuit 4, and one predetermined column is selected.

That is, column designation input signals A1 to A6 are converted into signals A1 and A2, A
The FETs are divided into three groups of two each, ie, FET 3 and A4, and A5 and A6, and three signals, one from each group, are selectively set to an L level signal, thereby turning off a predetermined FET.

For example, when signals A1, A4, and A are L level signals, FET'(Qs41) to (QS44) and (QS
53} to (Qsao) become conductive, and conductive region L2
~L, and the reference potential terminal 7 are connected.

Also, the FET (QS45) t(QS
49) and (QS61) are in the off state, the conductive region L1 connected to the output terminal OUT and the reference potential terminal T
This means that the conductive region L2 connected to the conductive region L2 is selected.

In other words, column B1 has been selected.

Subsequently, in this state, in the memory circuit 3, when a decode output is derived from the address decoder 5 to the row selection line R1 based on the row designation input signals D1 to Dn, the FET (QMI) constituting the memory circuit 3 becomes conductive, and the pair of conductive regions L1 and L2 selected by the column selection circuit 4 are connected.

Therefore, the output terminal OUT of this ROM is connected to the reference potential terminal 7, and the power supply potential V of the conductive region L1
DD is discharged to the reference potential VSS, and the reference potential VSS is read out to the output terminal oUT.

Further, in a state where the pair of conductive regions L1 and L2 are selected, if there is no FET in the column B1 to which the decoded output from the address decoder 5 is applied in the memory circuit 3, for example, Selection line R2
When the decoded output is being derived, the pair of conductive regions L1 and L2 selected by the column selection circuit 4 are separated.

Therefore, the output terminal OUT and the reference potential terminal 7 are separated, and the precharged power supply potential VDD is read out to the output terminal OUT.

Similarly, in the column selection circuit 4, three signals, one from each of the three sets of column designation input signals A1 to A80, are set to L level signals, thereby selecting the FETs connected in parallel in a predetermined column. It is turned off and one of the pair of conductive regions forming this predetermined column is connected to the output terminal OUT and the other to the reference potential terminal 1.

Then, with this pair of conductive regions selected,
FE connected between a pair of conductive regions of ζ in the memory circuit 3
The power supply potential VDD or the reference potential VSS is read out to the output terminal OUT depending on whether the decoded output from the address decoder 5 based on the row designation input signals D1 to Dn is output to this FET.

As described above, in the ROM shown in FIG. 4, after the conductive regions L1 to L8 are precharged by the precharge circuit 2, the column selection circuit 4 based on the column designation input signals A1 to A6
The operation of selecting a pair of conductive regions by the operation of and connecting one conductive region side to the output terminal OUT and the other conductive region side to the reference potential terminal 7 with the column formed by the pair of conductive regions as a boundary. By deriving the decode output from the address decoder 5 to the row selection lines R1 to Rn based on the row designation input signals D1 to Dn, the information programmed in advance by the FET in the memory circuit 3 is transferred to the output terminal OU.
It is derived to T.

By the way, when the number of bits of the ROM is increased based on the conventional circuit configuration shown in FIG. 4, similar to the conventional circuit shown in FIG. As is clear from the pattern diagram of a partial circuit of the ROM in FIG. 4 shown in FIG. Since the channel width W of the FET constituting the column selection circuit 4 can be increased and the mutual conductance gm of the FET can be increased, the ROM can operate at a low voltage.

In addition, in the pattern diagram shown in FIG.
1 to L3 are diffusion regions formed by diffusion of impurities into the semiconductor substrate, and row selection lines R, R2 and column designation input signal lines Al and A2 are formed of electrode metal such as aluminum. These are the gate electrode and wiring.

Further, in FIG. 5, the same or corresponding parts as in FIG. 4 are given the same reference numerals.

However, in the ROM shown in FIG. 4, with a column sandwiched between a pair of conductive regions selected by the column selection circuit 4 as a boundary, one conductive region side is the output terminal QUT, and the other conductive region side is the reference. Since they are connected to the potential terminals 1, when the selected pair of conductive regions are connected in the memory circuit 3, after the power supply potential VDD precharged to all the conductive regions L1 to L8 is discharged. Output terminal oU
The reference potential VSS will be derived at T.

Therefore, based on the conventional circuit configuration shown in FIG.
When the number of bits of OM increases, the number of FETs connected between adjacent conductive regions increases in the memory circuit 3 and column selection circuit 4, and the capacitance associated with the conductive regions L1 to L increases. Furthermore, the discharge time became longer, resulting in the inconvenience of not being able to operate at high speed.

Furthermore, if the power supply potential VDD is increased to prevent this, there will be a drawback that the power supply voltage margin will be impaired.

This invention was made in view of the drawbacks shown in the conventional circuits of ROMs shown in Figs. It is an object of the present invention to provide a ROM that can operate at low voltage and high speed without increasing the size of the memory.

The present invention will be explained in detail below based on the drawings.

FIG. 6 is a circuit diagram showing an embodiment of the ROM according to the present invention.

In the figure, the same or corresponding parts as in FIG. 2 are given the same reference numerals.

This embodiment circuit is constructed using P-channel FETs, and eight columns B1 are formed by nine conductive regions L1 to L.
- The ROM in which B8 was formed is shown.

The embodiment circuit shown in FIG.
, a memory circuit 3, a column selection circuit 4, and an address decoder 5, and is an improved version of the column selection circuit 4.

Therefore, the prechege circuit 2 and the memory circuit 3 have the same circuit configuration as the conventional circuit shown in FIG. 2 or FIG. 4.

That is, in the precharge circuit 2, the clock signal D is applied to each gate electrode, and the power supply terminal 6 and the nine conductive regions L are connected to each other.
It is composed of nine P-channel type FETs (Qps) to (QP9) connected between 1 to L, respectively.

The memory circuit 3 also includes P-channel type FETs (P-channel FETs) connected between adjacent conductive regions at preprogrammed positions so that desired information can be stored.
QMI) to (QMn), and the decoded outputs decoded by the address decoder 5 based on the row designation input signals D1 to Dn are sent to the gate electrodes of these FETs via the row selection lines R1 to Rn. is being applied.

The column selection circuit 4 in the ROM shown in FIG.
- A second transistor group 9 consisting of seven P-channel type FBTs connected in series between every other conductive region from L9 and the output terminal OUT or the reference potential terminal 7.

Specifically, the first transistor group 8 has a gate electrode F to which one signal A1 of a pair of signals AI and A2 selected from column designation input signals A1 to A6 is applied.
ET (QS71) to (QS74) and FETs (QS?5) to (QS?5) to which the other signal A2 is applied to their gate electrodes.
878).

These FETs (QS71) to (Q878) are located in column B1.
~B8, the FETs to which one signal A1 is applied and the FETs to which the other signal A2 is applied are arranged in an alternating pattern.

That is, FET (QS71) is connected between conductive regions L2 and L3, (QS?2) is connected between L4 and L, and (QS?3) is connected between conductive regions L2 and L3.
is between L8 and L7, (Q874) is between L8 and L9, (Q875) is between L1 and L2, (Qs?e
) is connected between L3 and L4, (Qs7y) is connected between L and L6, and (Qs7g) is connected between L7 and L8.

In addition, the second transistor group 9 includes seven FETs (Q88
1) to (Q887), whose gate electrodes include FBTs (Q871) to (Q878) constituting the first transistor group 8 from among the column designation input signals A1 to A6.
A pair of signals A1, A selected to be applied to the gate electrodes of
Signals A3 to A6 except for 2 are applied.

That is, the signal A3 is applied to the gate electrodes of FETs (Q8st) and (Q8s2), the signal A4 is applied to those of FETs (Q88s) and (Q884), and the signal A is applied to that of (Qssg).
Signal A6 is applied to each of Qs86) and (QS87).

In these FETs (Q8at) to (Q8B?),
FETs (Qs83) and (Qssa) are connected between conductive region L1 and reference potential terminal 7, FET (QS85) is connected between conductive region L4 and terminal 7, and FBT (Q882) and (Qssa) are connected between conductive region L1 and terminal 7.
887) are connected in series between the conductive region L and the terminal 7, respectively, and the FET (Q884) is connected between the conductive region L3 and the output terminal O.
The FBT (Qs81) is connected between the conductive region L7 and the output terminal 0υT.

The operation of the implementation circuit having the column selection circuit 4 having such a configuration will be explained.

In this embodiment circuit, first, as in the conventional circuit, the FETs (Qpt) to (QP) constituting the precharge circuit 2 are made conductive by applying the clock signal φ.
A power supply potential is applied to conductive regions L1 to L9.

Thereafter, by cutting off clock signal 2, conductive regions L1-L9 are precharged to power supply potential VDD.

Next, a pair of conductive regions adjacent to each other are selected by the column selection circuit 4, and one predetermined column is selected.

That is, column designation input signals A1 to A6 are converted into signals A1, A2, A
A predetermined FE from the first transistor group 8 is divided into three sets of two transistors, A4 and A5, and three sets of two, A5 and A6, and three signals, one from each set, are selectively set to L level signals.
T is turned off, and a predetermined FET from the second transistor group 9 is turned on.

For example, when signals A1, A4, and A6 are L level signals, FBT(Q871) to (Q874)t(Qsa3)
t(QS84) and (Qsaa) are turned on, the conductive region L1 is connected to the reference potential terminal 7, and the conductive regions L2 and L3 are connected to the reference potential terminal 7.
are respectively connected to the output terminal OUT.

In other words, column B1 is selected.

Subsequently, in this state, in the memory circuit 3, if a decode output is derived from the address decoder 5 to the row selection line R1 based on the row designation input signals D1 to Dn, the FET (QM1) constituting the memory circuit 3 turns on,
A pair of conductive regions L1 and L selected by the column selection circuit 4
2 is connected.

Therefore, in the pair of conductive regions L1 and L2 of this ROM, the FETs (QS84), (QS71)-(QMI), which are interposed between the output terminal OUT and the reference potential terminal 7,
(Q883) and (Q8sa) are all conductive, and the power supply potential VDD of conductive regions L1, L2, and L3 is set to the reference potential v8.
8, and the reference potential 88 continues to be output from the output terminal OUT.

In addition, in a state where the pair of conductive regions L1 and L2 are selected, if there is no FET in column B1 to which the decoded output is applied from the address decoder 5 in the memory circuit 3, for example, if the address decoder 5 sends the row selection line When the decoded output is derived from R2, the pair of conductive regions L1 and L2 selected by column selection circuit 4 are separated.

Therefore, the output terminal OUT and the reference potential terminal 7 are separated, and the precharged power supply potential VDD is read out to the output terminal OUT.

That is, when the column selection circuit 4 is configured as shown in FIG. 6, in order to select column B1, column designation input signals A1,
A4 and uA Saki L level signal, FET (Q.884)
It is necessary to make at least t(Q8?t)t(Qs83) and (Qs86) conductive.

In addition, in order to select column B2, the signals A2, A4 and A6'PL level signals are used, and FBT(Q884)t(Q
875), (Q8s3) and (Q886) must be made conductive.

Furthermore, in order to select column B3, signals A, A4 and A are set to L level signals, and FETs (Qs8,), (Qs8,
s72) and (Qa84) must be made conductive.

Similarly, in the column selection circuit 4, three signals, one from each of the three sets of column designating human input signals A1 to A6, are set to L level signals, thereby responding to the signal A or A2. FETs (Q871) to (Q878) of the first transistor group 8 connected between mutually adjacent conductive regions
A predetermined FET is turned off from among the FETs, and the signal A3
~In response to 80, every other conductive area L1tL3t
FET of the second transistor group 9 connected between L52L7 and L9 and the output terminal OUT or reference potential point 7
Turn on a predetermined FBT from among (Q881) to (Q887), and connect one of the pair of conductive regions constituting the selected column to the output terminal OUT and the other to the reference potential terminal 7. This will select only one column.

After that, when this predetermined column is selected and the pair of conductive regions are selected, the memory circuit 3 includes an FET connected between the pair of conductive regions, and the row designation input signal D
The power supply potential VDD or the reference potential VSS is read out to the output terminal OUT depending on whether the decoded output from the address decoder 5 based on 1 to Dn is derived to this FBT.

As described above, in the ROM shown in FIG. 6, after the conductive regions L, ~L, are precharged by the precharge circuit 2, the first transistor group 8 is activated based on the column designation input signals A, ~A6. The column selection circuit 4 selects a pair of conductive regions by turning off a predetermined FET in the second transistor group 9 and turning on a predetermined FET in the second transistor group 9, and selects one of the pair of conductive regions. and the other to the reference potential terminal 7, respectively, and the row designation input signal D.
1 to Dn from the address decoder 5 and the row selection line R1.
By deriving the decode output to Rn, information programmed in advance in the memory circuit 3 by the FET is derived to the output terminal OUT.

When the column selection circuit 4 is constructed as in the embodiment circuit shown in FIG. 6, the pattern as shown in FIG. F that configures the column selection circuit 4 without increasing the size.
Since the channel width W of the ET can be increased and the mutual conductance (gm) of the FET can be increased, there is an effect that the ROM can be operated at a low voltage.

As for the first transistor group 8, since the FET is connected between each conductive region, this is possible without increasing the pattern size, similar to the conventional circuit shown in FIG.
The channel width W of the FET can be increased.

Regarding the second transistor group 9, FETs (Q
881) to (QS87), the distance between adjacent FETs on the pattern, e.g.
Since the gap between (Qsa3) and (Q884) can be increased, the channel width W of the FET can be increased without the disadvantages such as punch-through shown in the conventional circuit of FIG.

Furthermore, FBTs (Q871) to (
By increasing the channel width W of Q878) and (Qss1) to (Qs87), low voltage operation becomes possible, and furthermore, the FET can be short-channeled, and the pattern size can be reduced.

Note that in the pattern diagram shown in FIG.
1 to L5 are impurity diffusion regions into the semiconductor substrate, column designation input signal lines A1 to A4 are gate electrodes and wiring formed of electrode metal, and the same or equivalent parts as in FIG. 6 are given the same reference numerals. did.

Furthermore, if the column selection circuit 4 is configured as shown in FIG.
The selected pair of conductive regions receive row designation input signals D1 to Dn.
When connected to each other in the memory circuit 3 based on
After the power supply potential VDD precharged to at most three conductive regions is discharged, the reference potential VDD is applied to the output terminal OUT.
Since SS is read out, higher speed operation is possible compared to the conventional circuit shown in FIG.

That is, for example, column B1 is selected by column selection circuit 4,
When the FET (QMI) is in a conductive state in the memory circuit 3, the conductive region L1 is connected to the reference potential terminal 7, and the conductive region L1 is connected to the reference potential terminal 7.
2 is connected to the output terminal OUT via the FET (QS71) and the conductive region L3, so at most the conductive regions L1 to
It is only necessary to apply the precharged power supply potential vDD to L3, and the reference potential VS is immediately applied to the output terminal oUT.
S will be read out.

As described above, the ROM according to this embodiment can operate at low voltage and high speed without increasing the pattern size when integrated into an IC. The number of FBTs to be used can be reduced.

In the example circuit shown in FIG. 6, eight columns B1 to B6 are formed by nine conductive regions L1 to L.
Although OM is shown, the present invention is not limited to this, and can be applied to cases where the number of bits is further increased.

Furthermore, when the embodiment circuit shown in FIG.
When P1) to (QP9) are configured with FETs having a conductivity type different from other FBTs, the effectiveness as a ROM can be further improved.

Generally, when FETs of different conductivity types are formed on the same pattern, the FBTs of different conductivity types are separated by a guard diffusion region.

When connecting FETs having different conductivity types, contacts are formed on each FBT, and the contacts are connected by electrode wiring extending beyond the card diffusion region.

At this time, since the pattern size of the contact needs to be larger than the width of the diffusion region, the distance between adjacent conductive regions cannot be made smaller than the distance between the contacts.

For this reason, when the number of bits of a ROM with a CMOS configuration is increased, the pattern size is disadvantageously increased.

That is, in the conventional circuit shown in FIG. 2, FBT (QPI) to (QP9) constituting the precharge circuit 2 are
When a channel type FET or other PET is used as a P channel type FBT, the precharge circuit 2 shown in FIG.
As is clear from the partial pattern diagram of the memory circuit 3, the pattern size of this ROM is determined by the spacing between the contacts.

In FIG. 8a, the same or corresponding parts as in FIG. 2 are given the same reference numerals.

Furthermore, in the figure, PDt to PDa are N-channel type FETs (QPI) = (QP
3) N-type drain regions, Ps1 to Ps3 are each FET (
Qp1) to (QP3) are N-type source regions.

Also, CNt to CN3 are FETs (Qpt) to (QP3)
Contacts CPI-cP3 formed in the N-type source regions Ps1 to P83 are contacts provided to the P-type conductive regions L1 to L3, respectively.

GD is a guard diffusion region, and N-channel FETs (Qpt) to (QP5) forming the precharge circuit 2
and a P-type conductive region L1 in which a P-channel FET is formed.
~L3, these are formed to be separated from each other.

Further, CA1-CA3 are wiring metals made of aluminum or the like, and contacts C'-CN3 and CP1-C
P3 is connected across the guard diffusion region GD.

As mentioned above, in the conventional ROM with CMOS configuration,
N-channel FET (
N-type source regions P8, ~PS9 of QPI) ~ (QP9)
and the P-type conductive regions L1 to L, are connected by a contact C.
Wiring metal CA via N1-CN9 and CP1-CP9
Since it is necessary to connect by t~CA9, this ROM
The pattern size is determined by the spacing between adjacent contacts, resulting in an enlarged pattern size.

However, in the embodiment circuit shown in FIG. 6, every other conductive region Ll, L3 among the conductive regions L1 to L,
Since jL5, L7, and L are connected to the output terminal OUT or the reference potential terminal 7, it is necessary to precharge only every other conductive region with the precharge circuit 2 in advance.

Therefore, there is no need to precharge the conductive regions L2, L4, L6, and L8, so FETs (QP2) and (QP4) are used to precharge these conductive regions.
, (QP6) and (QP8) are no longer necessary.

Therefore, the FET (QP
1) ~ (QP9) are N-channel FETs, other FETs
Even if the ET is a P-channel FET, one contact can be formed for two P-type conductive regions, as is clear from the partial pattern diagram of the precharge circuit 2 and memory circuit 3 shown in FIG. 8b. Therefore, it is possible to prevent the pattern size of the ROM from increasing, and furthermore, because of the CMOS configuration, low voltage operation is possible.

In the diagram of FIG. 8b, the same or equivalent parts as in FIGS. 6 and 8a are given the same reference numerals.

As described above, the ROM according to the present invention has a plurality of conductive regions,
It consists of a precharge circuit, a memory circuit, and a column selection circuit, and the column selection circuit is arranged between each of a plurality of conductive regions adjacent to each other, and is selected from among a plurality of column designation input signals and is complementary to each other. a first transistor group consisting of a multi-junction FBT, one of which is applied to the control electrode of every other one between the conductive regions, and the other is applied to the control electrode of the remaining ones; The signals are connected in series between the first column and the common output terminal or the reference potential point by means of respective predetermined conditions, and the signals other than the selected pair of signals among the plurality of column-specified human input signals are controlled differently. a second transistor group consisting of a plurality of FETs applied to the electrodes, and in response to the selected pair of the plurality of column designating input signals, a predetermined FET in the first transistor group is turned off, and a predetermined FET in the second transistor group is turned on in response to a signal other than the selected pair of signals, so that the output terminal and the reference potential point are turned on. A pair of adjacent conductive regions electrically connected to each other are selected, and stored information is read out according to the operation of a memory circuit driven by a row designation input signal between the selected pair of conductive regions. Therefore, when converting this ROM into an IC, the channel width of the FET can be increased without increasing the pattern size, making it possible to operate at low voltage.Moreover, the discharge path when reading out stored information is shortened, resulting in high-speed operation. It has the effect of allowing you to move.

[Brief explanation of the drawing]

Fig. 1 is a block diagram for explaining a ratioless ROM that is commonly used, Fig. 2 is a specific circuit diagram showing an example of a conventional ROM, Fig. 3, and a partial circuit pattern of the ROM shown in Fig. 2. 4 is a specific circuit diagram showing another example of the conventional ROM, FIG. 5 is a pattern diagram of a partial circuit of the ROM shown in FIG. 4, and FIG. 6 is an embodiment of the ROM according to the present invention. 7 is a pattern diagram of a part of the column selection circuit of the ROM in FIG. 6, and FIG. 8 is a circuit diagram showing the R
8A and 8B are partial pattern diagrams of a precharge circuit and a memory circuit of the OM; FIG. 8A is a pattern diagram of a conventional circuit, and FIG. 8B is a pattern diagram of an embodiment circuit. In the figures, the same or corresponding parts are denoted by the same reference numerals. 1... ROM, 2... pre-charge circuit, 3...
Memory circuit, 4... Column selection circuit, 5... Address decoder, 6... Power supply, 7... Reference potential point, 8...
First transistor group, 9...Second transistor group, QP1 to Qp9...2 FETs, QM1 to QMn.
...3 FETs, Q871QS78...8 FETs.
Qss1~Q887...9 FETs, L1~L,...
・Conductive region, D1~Dn...Row designation input signal, A1~
A6... Column designation input signal, O... Output terminal, VDD
...Power supply potential, X...Clock signal.

Claims (1)

[Scope of Claims] 1. A plurality of conductive regions arranged in parallel with each other on a semiconductor substrate, connected between a power source and the conductive regions, and configured to select a desired one of the plurality of conductive regions in response to a clock signal. A precharge circuit consisting of a plurality of field effect transistors for precharging to a power supply potential; A memory circuit comprising a plurality of field effect transistors in which row specifying input signals are applied to respective different control electrodes, a pair of conductive regions adjacent to each other is selected from among the plurality of conductive regions, and the selected pair of conductive regions are selected from the plurality of conductive regions. and a column selection circuit consisting of a plurality of field effect transistors arranged in a predetermined manner to connect the output terminal and the reference potential point, and to which a plurality of column designation input signals are applied to respective different control electrodes. , in a read-only memory that reads out information set in advance based on the plurality of row designation input signals and column designation input signals to the output terminal, the column selection circuit is arranged adjacent to each other in each of the plurality of conductive regions. A pair of signals selected from among the plurality of column specifying input signals and having a mutually complementary relationship are arranged between the conductive regions, one of which is applied to every other control electrode between the conductive regions, and the other is applied to the remaining control electrodes. A first transistor group consisting of a plurality of field effect transistors applied to the control electrode of the device is connected in series in a predetermined manner between every other one of the plurality of conductive regions and the output terminal or the reference potential point. a second transistor group consisting of a plurality of field effect transistors connected to each other, and signals other than the selected pair of signals among the plurality of column designating input signals are applied to different control electrodes, respectively; A predetermined field effect transistor in the first group of transistors is turned off in response to the selected pair of the plurality of column specifying input signals, and a pair of mutually adjacent conductive regions electrically connected to the output terminal and the reference potential point, respectively, by turning on a predetermined field effect transistor in the second group of transistors in response to the signal to be removed; A read-only memory characterized in that the memory information is read between the selected pair of conductive regions according to the operation of a memory circuit driven by the row designation input signal. 2. The read-only memory according to claim 1, characterized in that the field effect transistors constituting the precharge circuit, the memory circuit, and the column selection circuit are of the same conductivity type.・Only memory. 3. In the read-only memory according to claim 1, the plurality of field effect transistors constituting the precharge circuit are of the first conductivity type, and the other field effect transistors are of the second conductivity type. A read-only memory characterized by.