JPH0457297A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To speedily select a word line without damaging the degree of integration by turning on a second transistor (Tr) when exceeding a second threshold voltage, and connecting the word line through a first Tr to a power source as the result. CONSTITUTION:At time t0, the word line selected by the H drive of an X decoder 4 starts rising. When the potential of the most distant part of the word line exceeds a threshold voltage Vth' of a Tr31 at time tV, the Tr 31 is changed from OFF to ON. Since the resistance value of a resistor 33 is enough higher than the ON resistance of the Tr 31, the gate potential of a Tr 32 is made L. Since the Tr 32 is turned on as the result, it is connected to a power supply word line 2 and the H drive of an auxiliary drive circuit 10' is operated. By the H drive of the circuit 10', the rising potential change of the most distant part of the word line is made sharp.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention has memory cells connected to first and second power supplies, arranged in a matrix, and connected to word lines in units of rows, and a row decoder. The present invention relates to a semiconductor memory device in which a row of memory cells is selected by setting the selected word line to a first power supply potential and setting the unselected word line to a second power supply potential.

[Conventional technology]

FIG. 4 is a circuit configuration diagram showing the configuration of a mask ROM, which is one of the semiconductor memory devices in which memory cells are arranged in a matrix.

As shown in the figure, memory transistors 1 are arranged in a matrix, their gates are commonly connected to a word line 2 in each row, and their drains are commonly connected to a bit line 3 in each column. .

Word line 2 is connected to X decoder 4 and bit line 3 is connected to Y decoder 4.
It is connected to the decoder 5.

Based on an external input signal (not shown), the X decoder 4 drives one selected word line 2 among the plurality of word lines 2 to the H level and drives the other unselected word lines 2 to the L level. X
The above driving by the decoder 4 is carried out by a drive circuit inside the X decoder 4.

Then, the Y decoder 5 selects one bit line 3 from among the plurality of bit lines 3 based on an external input signal (not shown), and selects a memory transistor 1 at the intersection of the selected bit line 3 and the selected wire F line 2. Read the memory contents of.

By the way, as the capacity of memory increases, the length of the word line 2 tends to increase, and as a result, the word line 2 has a resistance component that cannot be ignored in proportion to its length. Therefore, the resistance value rO of the word line 2 up to the memory transistor 1 located closest to the X decoder 4 and the
There is a difference between the resistance value rE of the word line 2 and the memory transistor 1 located farthest from the word line 2.

As a result, as shown in FIG. 5, when the word line 2 rises to the H level, the word line 2 (hereinafter abbreviated as the nearest word line) under the gate of the memory transistor 1 located closest to the X decoder 4. ) changes in potential, compared to O,
Memory transistor 1 located farthest from decoder 4
The potential change LE of the word line 2 below the gate (hereinafter abbreviated as the farthest part of the word line) becomes gradual, and the rise time as a whole becomes slow. The same thing can be said when the word line falls to the L level. This delay in rise and fall times has the problem of slowing down the access time of the mask ROM.

In order to improve the above problem, an auxiliary drive circuit 10 that assists the rise and fall operations of the word line as shown in FIG. 6 is connected to the end of the word line 2 on the side to which the X decoder 4 is not connected. . The auxiliary drive circuit 10 includes a PMOS) transistor 21 and an NMOS) transistor 2.
An inverter 11 consisting of 2 and whose input is connected to the end of the word line 2, and an inverter I2 consisting of a PMOS transistor 23 and an NMOS transistor 24 are connected in series, and the output of the inverter I2 is fed back to the input of the inverter 11. There is. Note that r indicates the resistance value of the entire word line 2.

The function of the auxiliary drive circuit 10 will be explained below with reference to FIG. If the auxiliary drive circuit 10 is not present when the word line is selected, when the farthest part of the word line rises at time to, it finally reaches the H level at time tE. However, if the auxiliary drive circuit 10 is present, the potential change LE
' As shown in FIG.
Accordingly, inverter I2 changes from L to H.
to be reversed. As a result, H by the auxiliary drive circuit 10
The drive operates, and the potential change at the farthest part of the word line becomes rapid, and finally reaches the H level at time tH, which is faster than time tE.

On the other hand, even when the selected word line becomes unselected, when the farthest part of the word line falls and its potential falls below the threshold voltage vth of the inverter 11, the inverter 11 is inverted from L to H, and as a result, the inverter 2 is inverted from H to L, the auxiliary drive circuit 10 operates, and the potential change at the farthest part of the word line becomes rapid, and finally the L
The time to reach the level will be faster than before.

However, the main cause of the delay in the access time of the mask ROM is the delay in the rise time for charging the word line to the H level, and basically it is sufficient if the rise time can be shortened.

In this way, by speeding up the rise and fall times of the furthest part of the word line, which takes the longest time to rise and fall, by the auxiliary drive circuit 10, R
This realizes faster OM access times. Note that the threshold voltage vth of the inverter 11 is the same as that of the inverters II and I.
The intermediate value (■ o
It is desirable to set C to o/2).

Further, the auxiliary drive circuit 10, as shown in FIG.
It can also be provided at the center of the word line 2. Note that in the figure, r/2 indicates the resistance value for half the length of the word line 2.

[Problem to be solved by the invention]

However, in order to configure the auxiliary drive circuit 10, it is necessary to form at least four transistors, and providing such an auxiliary drive circuit 10 for each word line impairs the degree of integration and increases the capacity of the memory. The problem was that it was a major hindrance, and its practicality was poor.

This invention has been made to solve the above-mentioned problems, and provides a semiconductor memory device that can quickly select a word line without impairing the degree of integration even if the word line has a resistance component. The purpose is to obtain.

[Means to solve the problem]

A semiconductor memory device according to the present invention has memory cells connected to first and second power supplies, arranged in a matrix, and connected to word lines in units of rows, and has memory cells connected to word lines selected by a row decoder. A memory cell row is selected by setting the word line to a first power supply potential and setting the unselected word line to a second power supply potential, and includes an auxiliary drive circuit connected to the word line. This auxiliary drive circuit has one electrode connected to the first power supply, the other electrode connected to the word line, and a control electrode with a first threshold voltage that is an intermediate potential between the first and second power supply potentials. The first transistor turns on when a potential on the second power supply potential side is applied.
a first transistor having a conductivity type of
is connected to a power supply, a control electrode is connected to the word line, and a potential on the side of the first power supply potential is applied to the control electrode from a second threshold voltage that is an intermediate potential between the first and second power supply potentials. a second transistor of a second conductivity type that turns on when the transistor is turned on, one end of which is connected to the first power source, and the other end of which is connected to the other electrode of the second transistor and the control electrode of the first transistor; , and a resistor whose resistance value is sufficiently larger than the on-resistance of the second transistor.

[action,]

In this invention, when the potential of the selected word line changes from the second power supply potential to the first power supply potential when selecting a row of memory cells, when the potential exceeds the second threshold voltage, the second transistor is turned on. However, a potential divided by the resistor and the on-resistance of the second transistor is applied to the control electrode of the first transistor.

At this time, the resistance value of the resistor is sufficiently larger than the on-resistance of the second transistor, and the potential applied to the control electrode of the first transistor is closer to the second power supply potential than the first threshold voltage. Transistor 1 turns on. As a result, the word line is connected to the first power supply via the first transistor and thereby driven to the first power supply potential.

〔Example〕

FIG. 1 is a circuit diagram showing the vicinity of a word line of a mask ROM which is an embodiment of the present invention. As shown in the figure, the auxiliary drive circuit 10' is connected to the end of the word line 2 to which the X decoder 4 is not connected. The auxiliary drive circuit 10' includes NMOS) transistors 31. PM
It is composed of an OS transistor 32 and a resistor 33, and the resistor 33 and NMOS transistor 31 are connected in series between the power supply and ground. The resistance value of the resistor 33 is set to be sufficiently larger than the on-resistance of the NMOS transistor 31, and N
The gate of MOS transistor 31 is connected to the end of word line 2. Also, PMO5 is connected between the power supply and word line 2.
) A transistor 32 is inserted, and the gate of this PMOS transistor 32 is connected to a resistor 33 and an NMOS transistor 31.
connected between the drain and the drain of the Note that r is word line 2
Shows the overall resistance value. Further, the overall structure of the mask ROM is similar to the conventional example shown in FIG.

FIG. 2 is a graph showing the word line selection operation of the mask ROM having the auxiliary drive circuit 10 shown in FIG. In the same figure, LO represents the potential change at the nearest part of the word line, LE represents the potential change at the farthest part of the word line without the auxiliary drive circuit 10', and LE2 represents the potential change at the farthest part of the word line without the auxiliary drive circuit 10'.
′ shows the potential change at the farthest part of the word line. As shown in FIG. 2, at time to, the word line selected by the H drive of the X decoder 4 (the nearest word line, the farthest word line) starts to rise. and,
When the potential at the farthest part of the word line exceeds the threshold voltage v th' of the NMOS transistor 31 at time tV, the NMOS transistor 31 changes from off to on. At this time, since the resistance value of the resistor 33 is sufficiently higher than the on-resistance of the NMOS transistor 31, the power supply V is applied. PM obtained by dividing C by the resistor 31 and the on-resistance of the NMOS transistor 31
The gate potential of OS transistor 32 is led to approximately L level. As a result, the PMO5I-transistor 32 is turned on, and the power is connected to the word line 2 via the PMOS transistor 32, so that the auxiliary drive circuit 1
H drive drive by 0' works. Due to this H drive drive by the auxiliary drive circuit 10', the rise potential change at the farthest part of the word line becomes rapid, and it finally reaches the H level at time tH', and the H drive drive by the auxiliary drive circuit 10' It becomes faster than the H level arrival time tE when it does not work. Moreover, NMOS transistor 3
1 can be set lower than the threshold voltage vth of the CMOS inverter.
Compared to the conventional auxiliary drive circuit 10 (see FIGS. 6 and 7) configured by connecting OS inverters in series, the rise time of the word line to the H level can be shortened.

On the other hand, even when the selected word line becomes unselected, when the farthest part of the word line falls and its potential falls below the threshold value v th' of the NMOS transistor, the NMOS transistor 31 changes from on to off, and the PMOS transistor 32 turns off. The gate potential is led to H level and PMO3I-transistor 32
turns off. As a result, the word line 2 is grounded via the NMOS transistor 31, so the auxiliary drive circuit 1
0', the drive is activated, the falling potential changes rapidly, and the time at which the voltage finally reaches the L level becomes faster than before.

FIG. 3 is a plan view showing the layout pattern of the auxiliary drive circuit 10'. Note that in the figure, the mouth indicates a contact. As shown in the figure, a resistor 33 made of polysilicon is formed along the width direction of the power supply wiring 40, and one end thereof is connected to the end of the power supply wiring 40 via a contact, and the other end is connected to the end of the power supply wiring 40 through a contact. It is connected to the ρ wiring 42 and to the polysilicon gate 41 of the PMOS transistor 32 through it.

PMO5) The source of the transistor 32 is connected to the end of the power supply wiring 40 through a contact, and the train is connected to the Aρ wiring 43 through a contact. And this A
The No. 11 wiring 43 is connected to the word line 2 which also serves as the polysilicon gate of the NMOS l-transistor 31 via a contact. The drain of the NMOS transistor 31 is connected to the AI wiring 42 via a contact, and the source is connected to a source line 43 made of polysilicon (leading to the ground level).

This layout realizes the auxiliary drive circuit 10'. Note that the resistor 33 shown in FIG. 3 is formed along the width of the power supply wiring 40, and the resistor 33 shown in FIG.
Although it is formed without substantially impairing the degree of integration of M, this is based on the premise that the width of the power supply wiring 40 is sufficiently wide. However, in recent years, it has become common practice to place wide power supply wiring around the ζ memory cell in order to protect the chip from the effects of stress when the memory chip is sealed in a package. There is no problem with the above.

In this way, two transistors and one resistor constitute the auxiliary drive circuit 10'. Since the resistor is not an active element and does not need to be formed separately, the region for forming one resistor can be smaller than the region for forming two transistors. Therefore, the auxiliary drive circuit can be configured more compactly than in the past, and the degree of integration is improved accordingly.

In this embodiment, a mask ROM is used as an example, but if it is a semiconductor memory device that needs to select a word line that has a substantial resistance component at high speed without impairing the degree of integration, an EPROM or an E2FROM may be used. , SRAM, DRA
The present invention can also be applied to other semiconductor memory devices such as M. Further, the auxiliary drive circuit 10' is connected to the word line 2
It can also be provided in the center instead of at the end.

〔Effect of the invention〕

As described above, according to the present invention, when the potential of the selected word line changes from the second power supply potential to the first power supply potential, the second transistor is turned on when it exceeds the second threshold voltage. Accordingly, the first transistor is turned on and connected to the first power supply via the second transistor, thereby driving the word line to the first power supply potential.

By driving the auxiliary drive circuit by turning on the first transistor, the word line can be selected quickly even if the word line has some resistance component. Furthermore, since the auxiliary drive circuit can be formed using two transistors and one resistor, the degree of integration is also improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing the periphery of a word line of a mask ROM which is an embodiment of the present invention, FIG. 2 is a graph for explaining the operation of the auxiliary drive circuit shown in FIG. 1, and FIG. 1
4 is a circuit configuration diagram showing the overall configuration of a conventional mask ROM, FIG. 5 is a graph showing potential changes of selected word lines, and FIG. 7 and 7 are circuit diagrams showing an auxiliary drive circuit formed within the mask ROM. In the figure, 2 is a word line, 3 is an NMOS transistor, 32 is a PMOS transistor, and 33 is a resistor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1

Claims (1)

[Claims] (1) It has memory cells connected to first and second power supplies, arranged in a matrix and connected to word lines in row units, and sets the word line selected by a row decoder to the first power supply potential. a semiconductor memory device that selects a row of memory cells by setting the unselected word line to a second power supply potential, further comprising an auxiliary drive circuit connected to the word line, the auxiliary drive circuit One electrode is connected to the first power source, the other electrode is connected to the word line, and the control electrode is lowered from a first threshold voltage, which is an intermediate potential between the first and second power source potentials, to the second power source. a first transistor of a first conductivity type that turns on when a potential on the power supply potential side is applied; one electrode is connected to the second power supply; a control electrode is connected to the word line; a second transistor of a second conductivity type that turns on when a potential closer to the first power supply potential than a second threshold voltage, which is an intermediate potential between the first and second power supply potentials; 1, the other end is connected to the other electrode of the second transistor and the control electrode of the first transistor, and the resistance value is sufficiently larger than the on-resistance of the second transistor. A semiconductor memory device characterized in that: