JPH07182869A - Data writing method for semiconductor memory and semiconductor memory - Google Patents

Abstract

PURPOSE:To exactly operate a flashlight by applying a specified voltage to plural memory elements. CONSTITUTION:A contactor is formed in a P type well forming driver transistors NT1, NT2 and transfer transistors NT3, NT4 of an N channel MOS transistor constituting a memory cell. Then, an input voltage Vin higher than a source voltage Vss is applied to the P type well which is the back gate of the N channel MOS transistor, and respective transistors are operated as a bipolar transistor, and the flashlight is operated. Thus, since no necessity providing the N channel MOS transistor for the flashlight exists, the flashlight is realized without increasing a chip area. Further, since no N channel MOS transistor for the flashlight is formed, no load exists in the read of the data, and high speed operation is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data writing method for a semiconductor memory device and a semiconductor memory device, and more particularly to a random access memory (RAM).

In recent years, RAMs have been highly integrated and speeded up. In addition, a flash write function is required to write the same data to all or some of the memory cells of the RAM at the same time. Therefore, it is desired to realize the flashlight function without increasing the number of circuits.

[0003]

2. Description of the Related Art FIG. 16 is a block circuit diagram showing a structure of a general static random access memory (SRAM).

The SRAM includes a memory cell array (memory cell matrix) 101, an X (row) decoder and word driver 102, a bit driver 103, and a Y (column).
It includes a decoder 104, input circuits 105 and 106, a write amplifier 107, a sense amplifier 108, and an output circuit 109.

The memory cell array 101 is composed of memory cells arranged two-dimensionally, and each memory cell stores 1-bit data. The address Add from the outside is
X and Y decoders 102, 10 via input circuit 105
Sent to 4. Then, the X decoder 102 selects one word line WL, and the Y decoder 104 selects the pair of bit lines BL and the inverted bit line bar BL, whereby the word line WL and the bit line pair BL,
The memory cell at the intersection of the bars BL is determined. The determined memory cell is the target of the read operation and the write operation.

Input data Din from the outside is sent to the write amplifier 107 via the input circuit 106 when the write enable signal bar WE is L active. The input data Din is the bit line pair BL, selected from the write amplifier 107 via the bit driver 103.
It is sent to bar BL. At this time, the selected word line W
L is driven by the word driver 102. Therefore, the input data Din sent to the bit line pair BL and bar BL is written to the memory cell at the intersection of the selected word line WL and the bit line pair BL and bar BL.

On the other hand, the data read from a predetermined memory cell is output from the bit line pair BL, BL via the bit driver 103 and the sense amplifier 108 to the output circuit 1.
Sent to 09. The output circuit 109 is controlled by the control signal from the input circuit 106 and outputs the data read from the memory cell to the outside as output data Dout.

The chip select signal bar CS can be used to enable or disable the entire SRAM. Further, by the clear signal CLR, the data stored in a part of the SRAM memory cells can be simultaneously rewritten to a certain value (for example, “0”). This memory cell is shown in FIG.

FIG. 17 shows a high resistance load type memory cell,
In the memory cell C, a flip-flop circuit is formed by connecting the gate terminals of the driver transistors 110 and 111 of N-channel MOS transistors to the drain terminals of the other driver transistors 111 and 110.

High resistances R11 and R12 are connected as loads to the drain terminals of the driver transistors 110 and 111, respectively. The high resistance R11 and the driver transistor 110 are connected to the high potential side power source Vcc and the low potential side power source Vcc.
It is connected between ss. The high resistance R12 and the driver transistor 111 are connected to the high potential side power source Vcc and the low potential side power source Vcc.
It is connected between ss. In addition, the driver transistor 11
The transfer transistor 11 is connected between the drain terminal of 0 and the bit line BL, and between the drain terminal of the driver transistor 111 and the inverted bit line BL.
2, 113 are connected. The gate terminals of the transfer transistors 112 and 113 are connected to the word line WL.

N-channel MOS transistors 114, 1 for flash write are provided on each bit line pair BL, bar BL.
15 are respectively connected. The drain terminals of the N-channel MOS transistors 114 and 115 are bit line pair B.
It is connected to L and bar BL, and the source terminal is the low potential side power supply V
connected to ss. N-channel MOS transistor 1
A flash write signal FL is input to the gate terminal of 14, and an inverted flash write signal bar FL is input to the gate terminal of the N-channel MOS transistor 115.

That is, as shown in FIG. 16, the input circuit 10
6 receives the clear signal CLR, the clear signal C
The flash light signal FL and the bar FL are generated based on LR. Then, the input circuit 106 outputs the generated flash write signals FL and FL to the memory cell array 101.
Output to.

The flash write signal FL, FL input to the memory cell array 101 sets one of the bit line pair BL, BL to the power supply voltage Vss. At this time, the selected word line WL is driven by the word driver 102 in the same manner as the above-described data writing.
Therefore, the state (for example, "0") of the bit line pair BL and bar BL is written in all the memory cells connected to the selected word line WL.

[0014]

However, in the above method, the N-channel MOS transistor 11 for flash write is provided for each bit line pair BL, bar BL.
Since 4,115 must be provided, there is a problem that the chip area of the SRAM increases. In addition, an N-channel MOS transistor 114 for flashlight,
Reference numeral 115 denotes driver transistors 110 and 111 and transfer transistor 1 for performing flash writing.
Since it is formed to be larger than 12, 113, there is a problem that it becomes a load when reading the data stored in the memory cell C.

The present invention has been made to solve the above problems, and an object thereof is to make it possible to suppress an increase in the chip area of a circuit for a flashlight and to increase the flashlight. An object of the present invention is to provide a data writing method for a semiconductor memory device and a semiconductor memory device that can be surely performed.

[0016]

In order to achieve the above object, the present invention provides a semiconductor memory device in which the semiconductor memory element comprises a memory element having a MOS structure, wherein the back gates of a plurality of predetermined memory elements have the MOS structure. Each memory element is rewritten to have the same content by applying a voltage to operate the memory element as a bipolar parasitic transistor having a lateral structure.

[0017]

In the semiconductor memory device in which the semiconductor memory element is a memory element having a MOS structure, a voltage is applied to the back gates of a plurality of predetermined memory elements. Based on this voltage, the storage element of each MOS structure becomes a bipolar parasitic transistor of a lateral structure. That is, the back gate serves as the base, the drain serves as the collector, and the source serves as the emitter. This bipolar parasitic transistor is turned on and the contents of the memory element are rewritten. Therefore, the flashlight is surely performed.

[0018]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a high resistance load type memory cell. The memory cell C is composed of driver transistors NT1 and NT2 which are N channel MOS transistors and transfer transistors NT3 and NT4 and high resistances R1 and R2. The gate terminals of the driver transistors NT1 and NT2 are connected to the other driver transistor NT.
2, a flip-flop circuit is formed by connecting to the drain terminal of NT1.

High resistances R1 and R2 are connected as loads to the drain terminals of the driver transistors NT1 and NT2, respectively. The high resistance R1 and the driver transistor NT1 are connected between the high potential side power source Vcc and the low potential side power source Vss. The high resistance R2 and the driver transistor NT2 are connected between the high potential side power source Vcc and the low potential side power source Vss. Transfer transistors NT3 and NT are provided between the drain terminal of the driver transistor NT1 and the bit line BL, and between the drain terminal of the driver transistor NT2 and the inverted bit line bar BL, respectively.
4 is connected. Each transfer transistor NT
The gate terminals of 3 and NT4 are connected to the word line WL.

In this embodiment, the memory cell C is formed asymmetrically. That is, the high resistance R1 is formed so that its resistance value is larger than that of the high resistance R2. The input voltage Vin is applied to the substrates of the driver transistors NT1 and NT2 and the transfer transistors NT3 and NT4, that is, the back gate, through an external terminal (not shown).

FIG. 3 is a sectional view of the memory cell C formed on the semiconductor substrate, and schematically shows the structure and arrangement of the memory cell C for convenience of explanation. Then, for the sake of clarity, the N-channel MOS transistors NT1 to NT4 of the memory cell C are shown in a line.

The semiconductor substrate 11 is an N-type semiconductor substrate, and the P-type well 12 formed on the semiconductor substrate 11.
An N-type drain region 13 and a source region 14 are formed in the. A gate layer 15 is formed on the channel between the drain region 13 and the source region 14 via an insulating layer. Then, the drain region 13 and the source region 1
4 and the gate layer 15 make the driver transistor N
T1 is formed. Similarly, the N-type drain region 16 and the source region 17 formed in the P-type well 12 and the gate layer 18 formed on the channel between the drain region 16 and the source region 17 via the insulating layer are used. The driver transistor NT2 is formed.

An N type drain region 19 and a source region 20 are formed in the P type well 12. A gate layer 21 is formed on the channel between the drain region 19 and the source region 20 via an insulating layer. Then, the drain region 19, the source region 20, and the gate layer 21
Thus, the transfer transistor NT3 is formed. Similarly, the N type drain region 22 and the source region 23 formed in the P type well 12 and the drain region 2 are formed.
The transfer transistor NT4 is formed by the gate layer 24 formed on the channel between the source region 23 and the source region 23 via the insulating layer.

The contactor 2 is provided in each of the drain regions 13, 16, 19, 22 and the source regions 14, 17, 20, 23.
5 are formed, and the transistors NT1 to NT4 are connected via the contactor 25. That is, the drain region 13 of the driver transistor NT1 is connected to the gate layer 18 of the driver transistor NT2 and the drain region 19 of the transfer transistor NT3, and
It is connected to the high potential side power source Vcc through the high resistance R1.

Gate layer 1 of driver transistor NT1
Reference numeral 5 is connected to the drain region 16 of the driver transistor NT2 and the driver region 22 of the transfer transistor NT4, and is also connected to the high potential side power source Vcc via the high resistance R2. The source region 14 of the driver transistor NT1 is connected to the low-potential-side power supply Vss together with the source region 17 of the driver transistor NT2.

Transfer transistors NT3 and NT4
Of the gate layers 21 and 24 are connected to the word line WL. Source region 20 of transfer transistor NT3
Is connected to the bit line BL, and the source region 24 of the transfer transistor NT4 is connected to the inverted bit line bar BL.

Further, the contactor 2 is directly attached to the P-type well 12.
6 is formed, and the input voltage Vin corresponding to the operation of the SRAM is input through the contactor 26. That is, when performing a normal operation of writing or reading data in the SRAM, the input voltage Vin is applied to the P-type well 12.
Is applied as the power supply voltage Vss. At this time, the driver transistors NT1 and NT2 and the transfer transistors NT3 and NT4 operate as normal N-channel MOS transistors.

On the other hand, when performing flash write, the input voltage Vin higher than the power supply voltage Vss is applied to the P-type well 12.
Is applied. Then, the driver transistor NT1 operates as a lateral NPN bipolar transistor BT1 having the drain region 13 as a collector, the P-type well 12 as a back gate as a base, and the source region 14 as an emitter.

Similarly, the driver transistor NT2 operates as a lateral NPN bipolar transistor BT2 having a drain region 16 as a collector, a P-type well 12 as a back gate as a base, and a source region 17 as an emitter.

Further, the transfer transistor NT3 operates as a lateral NPN bipolar transistor BT3 having a drain region 19 as a collector, a P-type well 12 as a back gate as a base, and a source region 20 as an emitter. Similarly, the transfer transistor NT4 operates as a lateral NPN bipolar transistor BT3 in which the drain region 22 is the collector, the back gate is the P-type well 12 is the base, and the source region 23 is the emitter.

That is, when the input voltage Vin higher than the power supply voltage Vss is input to the N-channel MOS transistors NT1 to NT4 of FIG. 1, the voltage of the P-type well 12 in which the N-channel MOS transistors NT1 to NT4 are formed, that is, , The back gate voltage rises. Then, the driver transistor NT1 of each N-channel MOS transistor
NT2 and transfer transistors NT3 and NT4
Are the bipolar transistors BT1 to BT1 as shown in FIG.
It operates in an equivalent to BT4.

Next, the operation of the memory cell C will be described. Now, it is assumed that the data “1” is stored in the memory cell C. At this time, the voltage of the node A is H level and the voltage of the node B is L level.

When the input voltage Vin input from the external terminal is the power supply voltage Vss, the driver transistors NT1 and NT
2 and the transfer transistors NT3 and NT4 directly operate as N-channel MOS transistors. Then, data write and read operations are performed based on the bit line pair BL, bar BL and word line WL.

On the other hand, when the input voltage Vin higher than the power supply voltage Vss is input from the external terminal, the voltage of the P-type well 12, that is, the back gate voltage is increased to increase the driver transistors NT1 and NT2 and the transfer transistor NT3. NT4 is a bipolar transistor BT1 to BT
4 will work. Then, a current flows through the bipolar transistor BT1 and the voltage at the node A drops. At this time, the value of the high resistance R1 is formed larger than the value of the high resistance R2. Therefore, the voltage of the node A is lower than the voltage of the node B.

Then, when the input voltage Vin becomes the power supply voltage Vss, the bipolar transistors BT1 to BT4, which have operated as bipolar transistors, have their original N-channel MO.
Driver transistors NT1 and N that are S transistors
It operates as T2 and transfer transistors NT3 and NT4. At this time, since the voltage of the node A is lower than the voltage of the node B, the driver transistor NT
2 is turned off and the driver transistor NT1 is turned on. As a result, the data stored in the memory cell C becomes "0".

On the other hand, if "0" data is stored in memory cell C, the voltage of node A is at L level and the voltage of node B is at H level. When the input voltage Vin higher than the power supply voltage Vss is input from the external terminal, the voltage of the P-type well 12, that is, the back gate voltage rises, and the driver transistors NT1 and NT2 and the transfer transistors NT3 and NT4 are bipolar transistors BT1. ~ It operates as BT4. At this time, the value of the high resistance R1 is formed larger than the value of the high resistance R2, so that the voltage of the node A becomes lower than the voltage of the node B.

Then, when the input voltage Vin becomes the power supply voltage Vss, the bipolar transistors BT1 to BT4, which have operated as bipolar transistors, have their original N-channel MO.
Driver transistors NT1 and N that are S transistors
It operates as T2 and transfer transistors NT3 and NT4. At this time, since the voltage of the node A is lower than the voltage of the node B, the driver transistor NT
2 is turned off and the driver transistor NT1 is turned on. As a result, the data stored in the memory cell C becomes "0".

As described above, in this embodiment, the memory cell C
The contactor 26 is formed in the P-type well 12 in which the driver transistors NT1 and NT2 and the transfer transistors NT3 and NT4 of the N-channel MOS transistors constituting the above are formed. Then, the input voltage Vin higher than the power supply voltage Vss is applied via the contactor 26 to the P-type well 1 which is the back gate of the N-channel MOS transistor.
2, and each N-channel MOS transistor is operated as a bipolar transistor to perform flash writing. As a result, since it is not necessary to provide the N-channel MOS transistors 114 and 115 for flash writing, it is possible to realize the flash writing while suppressing an increase in chip area. Further, since the flash write N-channel MOS transistors 114 and 115 are not formed, there is no load for reading data, and the operation can be performed at high speed.

Further, in this embodiment, the flash write can be performed only by applying a voltage higher than the power supply voltage Vss to the P-type well 12 forming the memory cell C.
The flash write of the memory cell C can be performed without selecting the word line WL, and can be performed at a higher speed than the conventional flash write. (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS.

For convenience of explanation, the same components as those shown in FIGS. 1 to 3 are designated by the same reference numerals, and the description thereof will be partially omitted. 4 and 7 are circuit diagrams showing the memory cell C. The bit line pair BL, bar BL and the P-type well 12, which is a back gate, are connected via P-channel MOS transistors 31, 32. In addition, as shown in FIG. 7, the bit line pair BL and bar BL are P-channel MOS transistor 3
It is connected to the high potential side power source Vcc via 3, 34.
The P-channel MOS transistors 33 and 34 are transistors for precharging, and their gate terminals are connected to the low-potential-side power source Vss and are always controlled to be turned on. The bit line pair BL, bar BL is a bit driver 10
When not selected by 3, electric charges are stored in the capacitance through the P-channel MOS transistors 33 and 34.

FIG. 6 is a partial sectional view of the SRAM, showing the P-channel MOS transistor 33 for precharging and the memory cell C. For convenience of explanation, the structure and arrangement of the P-channel MOS transistor 33 and the memory cell C are shown. It is shown schematically. The P-channel MOS transistor 34 has the same drain terminal as the connection destination from the bit line BL to the inverted bit line bar BL, and its configuration is the same as that of the P-channel MOS transistor 33. Therefore, the description thereof is omitted. To do.

The source region 3 is formed on the N-type semiconductor substrate 11.
5 and the drain region 36 are formed. A gate layer 37 is formed on the channel between the source region 35 and the drain region 36 via an insulating layer. The source region 35, the drain region 36, and the gate layer 37 form the P-channel MOS transistor 33. The contactor 25 is formed in the source region 35 and the drain region 36, the source region 35 and the high-potential-side power supply Vcc are connected through the contactor 25, the drain region 36 and the bit line BL are connected, and the gate layer 37 is low. It is connected to the potential side power source Vss.

An N-type channel is formed between the drain region 36 of the P-channel MOS transistor 33 and the P-type well 12 which is the back gate of the memory cell C, and a gate layer is formed on the channel via an insulating layer. 38 is formed. The flash write signal FL is input to the gate layer 38. And the drain region 3
6, the gate layer 38 and the P-type well 12 form the P-channel MOS transistor 31.

Similarly, the P-channel MOS transistor 34
A gate layer is formed on the channel between the source region of the P type well and the P-type well 12 via an insulating layer.
The drain region of the channel MOS transistor 34 and P
The mold well 12 constitutes the P-channel MOS transistor 32.

A flash write signal FL is input to the gate terminal of the P channel MOS transistor 31, and an inverted flash write signal bar FL is input to the gate terminal of the P channel MOS transistor 32. The flash write signal FL and the bar FL are input from the input circuit 106.

In this embodiment, the memory cell C is formed symmetrically. That is, the high resistance R1 and the high resistance R2 are formed to have the same resistance value. FIG. 8 is a partial circuit diagram of the input circuit 106 and shows a flash write signal generation circuit. The flash write signal generation circuit is composed of CMOS inverter circuits 41 to 46 and NAND circuits 47 and 48, respectively. An external terminal 49 is connected to the input side of the inverter circuit 41,
The input data Din is input. The output side of the inverter circuit 41 is NA through the inverter circuit 42.
It is connected to the ND circuit 47 and directly to the NAND circuit 48.

An external terminal 50 is connected to the input side of the inverter circuit 43 so that the clear signal CLR is input. The output side of the inverter circuit 43 is connected to the NAND circuits 47 and 48 via the inverter circuit 44. The output side of the inverter circuit 43 is connected to the N-channel MOS transistor 5 via the inverter circuits 52 and 53.
4 is connected.

The N-channel MOS transistor 54 is connected between the P-type well 12 which is the back gate of the memory cell C and the low potential side power source Vss. Inverter circuit 5
Reference numerals 2 and 53 adjust the fan-out with respect to the input clear signal CLR, and the ON / OFF control of the N-channel MOS transistor 54 can be performed by the adjusted clear signal. That is, the N-channel MOS transistor 54 connects or separates the P-type well 12 which is the back gate of the memory cell C and the low-potential-side power supply Vss based on the input clear signal CLR.

An external terminal 51 is connected to the input side of the inverter circuit 45 so that the chip select signal bar CS is input. The output side of the inverter circuit 45 is connected to the NAND circuits 47 and 48 via the inverter circuit 46.

The NAND circuit 47 inputs the input data Din, the clear signal CLR and the chip select signal CS. The input data Din is data input to the SRAM, and the clear signal CLR is a signal for controlling the SRAM. Also, chip select signal bar C
S is a signal for switching the operating state of the SRAM between a standby state (standby) and an active state (active), and performs data read and write operations in the active state (active). And NAND
The circuit 47 outputs the flash write signal FL when the SRAM is in the standby state (standby).

Similarly, the NAND circuit 48 receives the input data Din inverted by the inverter circuit 41 and the clear signal C.
Input LR and chip select signal bar CS. Then, the NAND circuit circuit 48 outputs S based on the input signal.
The inverted flash light signal bar FL is output when the RAM is in a standby state (standby).

In this embodiment, the flashlight is S
It is set to be performed when the operating state of the RAM is the standby state (standby). That is, in the active state (active), the flash light signal FL, the bar FL
Both become H level. Therefore, the bit line pair BL,
The bar BL and the P-type well 12 which is the back gate of the memory cell are not short-circuited. Also, in the active state,
The N-channel MOS transistor 54 is controlled to be turned on, and the P-type well 12 of the memory cell C and the low-potential-side power supply Vss
And are connected.

On the other hand, in the standby state, the flash write signals FL and FL become H level or L level based on the input signal, and the P type well 12 which is the back gate of the bit line pair BL and bar BL and the memory cell C. Short and. In addition, the N-channel MOS transistor 54
Is controlled to be off, and the P-type well 12 of the memory cell C is separated from the low potential side power source Vss.

Next, the operation of the SRAM configured as described above will be described. Now, assuming that the data of "1" is stored in the memory cell C as in the above embodiment,
The voltage of the node A is H level, and the voltage of the node B is L
It is a level. Further, in the bit line pair BL and bar BL, charge is stored in the capacitor by a transistor for precharging.

NAND of flash write signal generation circuit
The circuits 47 and 48 generate and output flash write signals FL and FL based on the input data Din, the clear signal CLR, and the chip select signal bar CS. At this time,
When the input data Din is at H level, the generated flash write signal FL becomes L level and the inverted flash write signal bar FL becomes H level.

On the other hand, when the input data Din is at L level, the generated flash write signal FL becomes H level and the inverted flash write signal bar FL becomes L level. The flash write signals FL and FL are input to the gate terminals of the P channel MOS transistors 31 and 32, respectively. P-channel MOS transistor 3
When the flashlight signal FL and the bar FL are input to the terminals 1 and 32, on / off control is performed based on the signals. The N-channel MOS transistor 54 is on / off controlled based on the input clear signal CLR.

First, the case where the flash write signal FL is at the L level and the inverted flash write signal bar FL is at the H level will be described. The P-channel MOS transistor 31 to which the flash write signal FL has been input is turned on. On the other hand, the P-channel MOS transistor 32 to which the inverted flash write signal bar FL is input is turned off.
At this time, the N-channel MOS transistor 54 is turned off, and the back gate and the low potential side power source Vss are separated from each other.
Then, the charge of the capacitance of the bit line BL is changed to the P channel MOS.
Transistors NT1 to NT via the transistor 31
It will flow into the back gate of No. 4.

As a result, as shown in FIG. 5, the back gate voltage rises above the power supply voltage Vss, and the driver transistors NT1 and NT2 and the transfer transistor NT are transferred.
3 and NT4 operate as bipolar transistors BT1 to BT4 based on the P-type well 12 which is a back gate.

At this time, the charge of the capacitance of the bit line BL is P
The electric charge of the capacitance of the inverted bit line bar BL, which flows into the mold well 12, is retained as it is. As a result, the voltage of the node A becomes lower than the voltage of the node B.

When the charge of the capacitance of the bit line BL decreases,
The P channel MOS transistor 31 is turned off. Also, the N-channel MOS transistor 54 is turned on,
The back gate of the memory cell C and the low potential side power source Vss are connected. Then, the respective bipolar transistors BT1 to BT4 which have operated as the bipolar transistors are the driver transistors NT1 and NT2 and the transfer transistors NT3 which are the original N-channel MOS transistors.
It will operate as NT4. At this time, node A
Is lower than the voltage of the node B, the driver transistor NT2 is turned off and the driver transistor NT
1 turns on. As a result, the data stored in the memory cell C becomes "0".

Next, the case where the flash write signal FL is at H level and the inverted flash write signal bar FL is at L level will be described. The P-channel MOS transistor 31 to which the flash write signal FL has been input is turned off. On the other hand, the P-channel MOS transistor 32 to which the inverted flash write signal bar FL is input is turned on.
At this time, the N-channel MOS transistor 54 is turned off, and the back gate and the low potential side power source Vss are separated from each other.
Then, the charge of the capacitance of the inverted bit line bar BL is transferred to each transistor NT via the P-channel MOS transistor 32.
1 to NT4 will flow into the back gate.

As a result, as shown in FIG. 5, the back gate voltage rises above the power supply voltage Vss, and the driver transistors NT1 and NT2 and the transfer transistor NT are transferred.
3 and NT4 operate as bipolar transistors BT1 to BT4 based on the P-type well 12 which is a back gate.

At this time, the electric charge of the capacitance of the inverted bit line bar BL flows into the P-type well 12, and the electric charge of the capacitance of the bit line BL is retained as it is. Therefore, the voltage of the node B is kept lower than the voltage of the node A.

When the charge of the capacitance of the inverted bit line bar BL is lowered, the P channel MOS transistor 32 is turned off. Further, the N-channel MOS transistor 54 is turned on, and the back gate of the memory cell C and the low-potential-side power supply Vss
And connect. Then, the respective bipolar transistors BT1 to BT4 which have operated as the bipolar transistors are the driver transistors NT1 and NT2 which are the original N-channel MOS transistors and the transfer transistor N.
It operates as T3 and NT4. At this time, since the voltage of the node A is higher than the voltage of the node B, the driver transistor NT2 is turned on and the driver transistor NT1 is turned off. As a result, the data stored in the memory cell C becomes "1".

On the other hand, if "0" data is stored in memory cell C, the voltage of node A is at L level and the voltage of node B is at H level. Then, the P-channel MOS transistors 31 and 32 are on / off controlled based on the flash write signals FL and FL. The N-channel MOS transistor 54 is on / off controlled based on the input clear signal CLR.

First, the case where the flash write signal FL is at the L level and the inverted flash write signal bar FL is at the H level will be described. The P-channel MOS transistor 31 to which the flash write signal FL has been input is turned on. On the other hand, the P-channel MOS transistor 32 to which the inverted flash write signal bar FL is input is turned off.
At this time, the N-channel MOS transistor 54 is turned off, and the back gate and the low potential side power source Vss are separated from each other.
Then, the charge of the capacitance of the bit line BL is changed to the P channel MOS.
Transistors NT1 to NT via the transistor 31
It will flow into the back gate of No. 4.

As a result, as shown in FIG. 5, the back gate voltage rises above the power supply voltage Vss, and the driver transistors NT1 and NT2 and the transfer transistor NT are transferred.
3 and NT4 operate as bipolar transistors BT1 to BT4 based on the P-type well 12 which is a back gate.

At this time, the charge of the capacitance of the bit line BL is P
The electric charge of the capacitance of the inverted bit line bar BL, which flows into the mold well 12, is retained as it is. Therefore, the voltage of the node A is kept lower than the voltage of the node B.

When the charge of the capacitance of the bit line BL decreases,
The P channel MOS transistor 31 is turned off. Also, the N-channel MOS transistor 54 is turned on,
The back gate of the memory cell C and the low potential side power source Vss are connected. Then, the respective bipolar transistors BT1 to BT4 which have operated as the bipolar transistors are the driver transistors NT1 and NT2 and the transfer transistors NT3 which are the original N-channel MOS transistors.
It will operate as NT4. At this time, node A
Is lower than the voltage of the node B, the driver transistor NT2 is turned off and the driver transistor NT
1 turns on. As a result, the data stored in the memory cell C becomes "0".

Next, the case where the flash write signal FL is at H level and the inverted flash write signal bar FL is at L level will be described. The P-channel MOS transistor 31 to which the flash write signal FL has been input is turned off. On the other hand, the P-channel MOS transistor 32 to which the inverted flash write signal bar FL is input is turned on.
At this time, the N-channel MOS transistor 54 is turned off, and the back gate and the low potential side power source Vss are separated from each other.
Then, the charge of the capacitance of the inverted bit line bar BL is transferred to each transistor NT via the P-channel MOS transistor 32.
1 to NT4 will flow into the back gate. As a result, as shown in FIG. 5, the voltage of the back gate rises above the power supply voltage Vss, and the driver transistors NT1, NT
2 and the transfer transistors NT3 and NT4 operate as bipolar transistors BT1 to BT4 based on the P-type well 12 which is a back gate.

At this time, the charge of the capacitance of the inverted bit line bar BL flows into the P-type well 12, and the charge of the capacitance of the bit line BL is retained as it is. Therefore, the voltage of the node B becomes lower than the voltage of the node A.

When the charge on the capacitance of the inverted bit line bar BL decreases, the P-channel MOS transistor 32 turns off. Further, the N-channel MOS transistor 54 is turned on, and the back gate of the memory cell C and the low-potential-side power supply Vss
And connect. Then, the respective bipolar transistors BT1 to BT4 which have operated as the bipolar transistors are the driver transistors NT1 and NT2 which are the original N-channel MOS transistors and the transfer transistor N.
It operates as T3 and NT4. At this time, since the voltage of the node A is higher than the voltage of the node B, the driver transistor NT2 is turned on and the driver transistor NT1 is turned off. As a result, the data stored in the memory cell C becomes "1".

As described above, in the semiconductor memory device of this embodiment, it is formed on the channel between the P-type well 12 which is the back gate of the memory cell C and the drain region 36 of the P-channel MOS transistor 33 for precharging. The gate layer 38 was formed. The flash signal FL is input to the gate layer 38, and the drain region 36 and the gate layers 38 and P
The type well 12 is operated as a P-channel MOS transistor 31, and the bit line pair BL, bar BL and the P-type well 12 are short-circuited. Then, the driver transistors NT1 and NT2 and the transfer transistor NT
3, NT4 is a bipolar transistor B having a lateral structure
The flashlight is operated by operating as T1 to BT4.

As a result, the flash write can be performed by forming the gate layer 38 and operating it as the P-channel MOS transistors 31 and 32, so that the flash write can be realized while suppressing the increase of the chip area. Further, since the conventional N-channel MOS transistors 114 and 115 for flash write are not formed,
There is no load for reading data, and high speed operation is possible.

The levels of the flash write signals FL and FL can be switched according to the state of the input data Din, and the flash write signals FL and FL can be switched.
Since the flash write is performed based on
The flash write can be performed by selecting "0" or "1" of the data to be stored in.

The present invention is not limited to the above-described embodiments. For example, in the second embodiment, on the channel between the drain region 36 of the P-channel MOS transistor 33 for precharging and the P-type well 12. On the gate layer 3
8 is formed, and the bit line pair BL, bar BL and the P-type well 12 which is the back gate are short-circuited by the P-channel MOS transistor 31 (32) composed of the drain region 36, the P-type well 12 and the gate layer 38. However, the P-channel MOS transistor 31 (3
2) may be provided, that is, the source region and the drain region may be formed separately from the drain 36 and the P-type well 12. In this case, the SRAM becomes larger than the second embodiment by the amount of the drain region and the source region. However, the N-channel MOS transistors 31 and 32 are connected to the P-type well 12, which is a back gate, and the bit line pair BL, B.
Since only L needs to be short-circuited, the element can be small and can be made smaller than the conventional flash write transistors 114 and 115 of the SRAM. Therefore, the SRAM can be formed smaller than before,
Moreover, there is no load when reading data.

In addition, as shown in FIG.
The S transistors 61 and 62 may be provided to short-circuit the bit line pair BL, bar BL and the P-type well 12. At this time, the N-channel MOS transistor 61,
At the gate terminal of 62, a flash write signal FLFL2 and a bar FL2 via an inverter circuit shown by a dotted line in FIG.
Be sure to enter. Also, as shown in FIG.
It is also possible to form and implement the PNP type bipolar transistors 63 and 64 that connect the well 12 to the bit line pair BL and bar BL.

Further, as shown in FIG. 11, NPN bipolar transistors 65 and 66 may be used to short-circuit the back gate and the bit line pair BL and bar BL for flash writing. At this time, the NPN bipolar transistors 65 and 66 are P for precharge.
It is formed by inputting the flash write signal FL and the bar FL to the back gates of the channel MOS transistors 33 and 34.

That is, as shown in FIG. 12, the P-type buried layer 7
1 to form the N-type well 72 which is the back gate of the P-channel MOS transistor 33 and the N-type semiconductor substrate 11.
And separate. The contactor 73 is formed directly on the N-type well 72 which is a back gate. And the contactor 73
When the flash write signal FL2 is input to the P-channel MOS transistor 33 through the inverter circuit shown by the dotted line in FIG. 8, the drain region 36 of the P-channel MOS transistor 33 is the collector, the N-type well 72 which is the back gate is the base, and the P-type well 12 is the emitter. It operates as a PNP type bipolar transistor 65 which is a parasitic bipolar transistor having a lateral structure. Further, the PNP type bipolar transistor 66 has the same structure and operates as a parasitic bipolar transistor having a lateral structure by the flash write signal bar FL2 via the inverter circuit.

The P-type well 12 which is the back gate of the memory cell C is formed by the bipolar transistors 65 and 66.
The bit line pair BL and bar BL can be short-circuited to rewrite the memory of the memory cell C.

That is, a P-channel MOS for precharging
Flash write can be performed by directly forming the contactor 73 on the N-type well 72 which is the back gate of the transistors 33 and 34 and operating as the PNP-type lateral parasitic bipolar transistors PNP-type bipolar transistors 65 and 66. it can. As a result, since it is not necessary to provide the conventional N-channel MOS transistors 114 and 115 for flash writing, it is possible to perform flash writing while suppressing an increase in chip area. Further, since the flash write N-channel MOS transistors 114 and 115 are not formed, there is no load for reading data, and the operation can be performed at high speed.

Further, a P-channel MOS for precharging
The transistors 33 and 34 are connected to the high potential side power source Vcc via the P channel MOS transistor 74 as shown in FIG.
It is connected to the. P-channel MOS transistor 74
The flash write signals FL and FL are input to the gate terminal of the flash memory via the NAND circuit 75. That is, the P-channel MOS transistor 74 has the flash write signal F
By the L and bar FL, the bit line pair BL and bar BL and the high-potential side power source Vcc are separated from each other during flash writing. As a result, in addition to the effect of the above-described embodiment, the parasitic effect of the P-channel MOS transistors 33 and 34 for precharging can be eliminated, and the flash write can be efficiently performed.

Alternatively, only one of the P-channel MOS transistors 31 and 32 shown in FIG. 4 may be provided and implemented. At this time, the data stored in the memory cell C by the flash write is "0" or "1" depending on which of the bit line pair BL and bar BL is shorted to the P-type well 12. Become.

Further, in the first embodiment, the high resistance R1 is formed to have a larger resistance value than the high resistance R2 to form the memory cell C in an asymmetric type, but the high resistance R1 is formed to have a smaller resistance value than the high resistance R2. You may make it implement | achieve by making it asymmetrical. At this time, the data stored in the memory cell C by the flash write is "1" contrary to the first embodiment.
Will be stored.

In the first embodiment, the high resistance R1,
Although the memory cell C is formed asymmetrically by changing the resistance value of R2, the driver transistor NT1, the transfer transistor NT3, and the driver transistor NT2 are formed.
Alternatively, the transfer transistor NT4 may be formed with a different size so that the memory cell C is formed asymmetrically.

Further, in the first embodiment, the flash memory may be written by applying the input voltage Vin to the P-type well 12 which is the back gate by using the symmetrical memory cell C.

Further, using the asymmetrical memory cell C, as shown in the second embodiment, a P channel MO is provided between the bit line pair BL, bar BL and the P type well 12 which is a back gate.
Flash write may be performed by providing elements such as S transistors 31 and 32 to short-circuit the bit line pair BL, bar BL and the P-type well 12. At this time, by inputting one of the flash write signal FL and the bar FL to the gate terminals of both transistors 31 and 32,
The data stored in the memory cell C can be "0" or "1".

Further, as shown in FIG. 14, the flash write signal generation circuit provided in the input circuit 106 of the second embodiment uses the input data Din, the write enable signal bar WE and the chip select signal bar CS for flash write. The signal FL and the bar FL are generated. The generated flash write signals FL and FL may be input to the gate layer 38 of FIG. 6 to operate as the P-channel MOS transistors 31 and 32 to perform fresh writing.

In this case, the write enable signal bar WE
A voltage detection circuit 55 is inserted and connected between the external terminal 50 for inputting and the inverter circuit 43. When performing flash writing, the write enable signal bar WE
Is inputted as a super H level having a voltage higher than the normal H level (power supply voltage Vcc). The write enable signal bar WE is at the H level or the L level when the normal writing and reading operations are performed. At this time, the voltage detection circuit 55
Normally outputs an L level.

Then, when the super H level is input to perform flash writing, the voltage detection circuit 61 outputs the H level. Therefore, the flashlight signal FL and the bar FL are output only when a flashlight is to be performed. In this case, since it is not necessary to provide an external terminal for inputting the clear signal CLR of the second embodiment, it is possible to prevent the size of the device itself from increasing.

Further, the generated flashlight signal F
Flash write may be performed by inputting L and bar FL to the base terminals of the NPN bipolar transistors 63 and 64 of FIG. Further, even if flash write signals FL2 and FL2 are generated via the inverter circuit shown by the dotted line in FIG. 14 and input to the gate terminals of the N channel MOS transistors 61 and 62 shown in FIG. Good. Further, by inputting the flash write signals FL2 and FL2 to the contactor 73 of FIG. 12, a PNP type bipolar transistor 65 which is a parasitic bipolar transistor of a lateral structure shown in FIG.
The flash light may be operated by operating as 66.

Further, in the input circuit 106 of FIG.
Although the voltage detection circuit 55 is provided in the write enable signal bar WE to detect the super H level and generate the flash write signals FL and FL, the voltage detection circuit 55 is used for other signals such as a specific address Add. Alternatively, the flash write signal FL and the bar FL may be generated by setting the signal to the super H level.

Further, when implementing flash writing for the synchronous SRAM, the flash writing may be implemented by generating a flash writing signal by the clock signals CLK and CLK input to the SRAM. . FIG. 15 is a partial circuit diagram of the input circuit 106 and shows a clear signal generation circuit. The clear signal generation circuit generates a clear signal CLR based on the input clock signal CLK and bar CLK. The clear signal generation circuit includes an input circuit unit 81, a removal circuit unit 82, and a shaping circuit unit 8.
3 and 3.

The input circuit section 81 is a prohibition logic detection circuit, and detects the prohibition logic (both H level or both L level) that the input clock signals CLK and CLK are not input in the normal operation. , The detection result is output. The removing circuit unit 82 is provided to prevent an erroneous operation by removing an input having a short pulse width, and can remove an input having a pulse width shorter than a time set by the number of inverter circuits connected in series. .

The shaping circuit section 83 is also provided to generate a clear signal having a pulse width corresponding to the time required for flash writing, and the pulse width to be generated is determined by the number of inverter circuits connected in series with the input pulse signal. To be done.

The generated clear signal CLR is input to the input circuit 106 shown in FIG.
It may be used as an LR to perform flash light. At this time, it is not necessary to provide the external terminal 50 for inputting the clear signal CLR in FIG. 8, the number of input terminals of the SRAM can be reduced, and the size of the SRAM itself can be reduced.

Further, the generated clear signal CLR may be input to the P-type well 12 which is the back gate of the asymmetrical memory cell C of the first embodiment for flash writing.

In each of the above embodiments, the present invention is
Although it is applied to RAM, it may be applied to dynamic random access memory (DRAM).

[0100]

As described in detail above, according to the present invention,
There is an excellent effect that the flash write can be performed surely while suppressing the increase in the chip area of the circuit for the flash write with a simple configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a memory cell according to a first embodiment.

FIG. 2 is an equivalent circuit diagram of a memory cell for explaining the flash write of the first embodiment.

FIG. 3 is a schematic diagram illustrating a memory cell according to a first embodiment.

FIG. 4 is a circuit diagram illustrating a memory cell using a P-channel MOS transistor of a second embodiment.

FIG. 5 is an equivalent circuit diagram illustrating an operation of a memory cell using a P-channel MOS transistor of the second embodiment.

FIG. 6 is a schematic diagram illustrating a memory cell according to a second embodiment.

FIG. 7 is a circuit diagram of a main part of a memory cell according to a second embodiment.

FIG. 8 is a partial circuit diagram of an input circuit for generating a flash write signal according to a second embodiment.

FIG. 9 is an equivalent circuit diagram illustrating an operation of a memory cell using an N-channel MOS transistor according to another example of the second embodiment.

FIG. 10 is an equivalent circuit diagram explaining an operation of a memory cell using a PNP type bipolar transistor of another example of the second embodiment.

FIG. 11 is an equivalent circuit diagram illustrating an operation of a memory cell using an NPN bipolar transistor of another example of the second embodiment.

FIG. 12 is a schematic diagram illustrating a memory cell using an NPN bipolar transistor showing another example of the second embodiment.

FIG. 13 is a circuit diagram of an essential part of the memory cell of FIG.

FIG. 14 is a partial circuit diagram of an input circuit for generating a flash write signal according to another example of the second embodiment.

FIG. 15 is a partial circuit diagram of an input circuit that generates a clear signal.

FIG. 16 is a block circuit diagram showing a configuration of a general SRAM.

FIG. 17 is a circuit diagram of a memory cell for explaining a conventional flash write.

[Explanation of symbols]

 11 semiconductor substrate 26 contactor BL, bar BL bit line C memory cell NT1, NT2 driver transistor NT3, NT4 transfer transistor Vin input voltage Vss low potential side power supply

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroaki Unkai 1844-2, Kozoji-cho, Kasugai-shi, Aichi Prefecture Within Fujitsu Vieruesuai Inc. (72) Inventor Shuhei Yamaguchi 1844-2, Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu Within VIS Co., Ltd.

Claims (8)

[Claims] 1. A method for writing data in a semiconductor memory device, wherein the semiconductor memory element is a memory element having a MOS structure, wherein the back gates of a plurality of predetermined memory elements have the M
A data writing method for a semiconductor memory device, wherein a voltage for operating a memory element having an OS structure as a bipolar parasitic transistor having a lateral structure is applied to rewrite each memory element to the same content. 2. A pair of MOS transistor driver transistors (NT1, NT2) on the semiconductor substrate (11) have their gate terminals connected to the other driver transistor (NT2, NT2).
A flip-flop circuit connected to the drain terminal of NT1) and the source terminal of each driver transistor (NT1, NT2) to the low potential side power supply (Vss);
A MOS structure transfer transistor (NT) that connects the drain terminals of the pair of driver transistors (NT1, NT2) to the pair of bit lines (BL, bar BL).
In the semiconductor memory device in which a plurality of memory cells (C) each including (3, NT4) are arranged, an input voltage (Vi
A semiconductor memory device characterized in that a contactor (26) for inputting n) is formed. 3. A pair of driver transistors (NT1, NT2) on a semiconductor substrate (11) are connected at their gate terminals to the drain terminals of the other driver transistor (NT2, NT1), and at the same time, each driver transistor (NT1, NT1) is connected. The source terminal of NT2) is the low potential side power supply (V
and a transfer transistor (NT3, NT4) connecting the drain terminals of the pair of driver transistors (NT1, NT2) to the pair of bit lines (BL, bar BL). In a semiconductor memory device in which a plurality of (C) are arranged, a contact / separation element that connects or separates the pair of bit lines (BL, bar BL) and the back gates of the transistors (NT1 to NT4) is provided. And semiconductor memory device. 4. The semiconductor memory device according to claim 3, wherein the contact / separation element is a P-channel MOS transistor (3
1, 32), and a flash write signal (FL, bar FL) for controlling ON / OFF of the P-channel MOS transistor (31, 32) is input to its gate terminal. 5. The semiconductor memory device according to claim 4, wherein the flash write signal (FL, bar FL) is input data (Din) which is data to be input to the semiconductor memory device.
And a clear signal (CLR) which is a control signal input to the semiconductor memory device and a chip select signal (bar CS) which controls switching of the semiconductor memory device between a standby state and an active state. Storage device. 6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is a clock signal (C
Synchronous SRA driven by LK, CLK)
The clear signal (CLR) is M, and the detection circuit unit (81) for detecting the inhibition logic of the clock signal and the detection result of the detection circuit unit (81) are input, and a pulse having a predetermined pulse width or less is input. A semiconductor memory device characterized by being produced by a removal circuit section (82) for removal and a shaping circuit section (83) for shaping a pulse input from the removal circuit section (82) into a predetermined pulse width. 7. A driver transistor (N) which is a pair of N-channel MOS transistors on a semiconductor substrate (11).
The gate terminals of T1 and NT2) are connected to the drain terminals of the other driver transistors (NT2 and NT1) and the driver transistors (NT1 and NT2) are connected.
A flip-flop circuit in which the source terminal of 2) is connected to the low-potential side power supply (Vss), and an N channel that connects the drain terminals of the pair of driver transistors (NT1, NT2) to the pair of bit lines (BL, bar BL) Transfer transistors (NT3, NT) that are MOS transistors
4) and a plurality of memory cells (C) are arranged, and a pair of P-channel MOS transistors (33, 3) connecting the pair of bit lines (BL, BL) to the high potential side power supply Vcc.
4) In the semiconductor memory device, the pair of P-channel MOS transistors (33, 3)
4) drain region (36) and each transistor (N
A semiconductor memory device characterized in that a gate layer (38) is formed on a channel between the back gates of T1 to NT4) via an insulating layer. 8. A driver transistor (N) which is a pair of N-channel MOS transistors on a semiconductor substrate (11).
The gate terminals of T1 and NT2) are connected to the drain terminals of the other driver transistors (NT2 and NT1) and the driver transistors (NT1 and NT2) are connected.
A flip-flop circuit in which the source terminal of 2) is connected to the low-potential side power supply (Vss), and an N channel that connects the drain terminals of the pair of driver transistors (NT1, NT2) to the pair of bit lines (BL, bar BL) Transfer transistors (NT3, NT) that are MOS transistors
4) and a plurality of memory cells (C) are arranged, and a pair of P-channel MOS transistors (33, 3) connecting the pair of bit lines (BL, BL) to the high potential side power supply Vcc.
4) In the semiconductor memory device, the pair of P-channel MOS transistors (33, 3)
4) A semiconductor memory device characterized in that a buried layer (71) for separating the back gate (72) and the semiconductor substrate (11) is formed and a contactor (73) is formed on the back gate (72). .