JPS5832462A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the injection of electron into a gate oxide film by a method wherein a drain region is buried below the surface of a semiconductor region. CONSTITUTION:In the MOSFET consisting of a source region 30, a drain region 31, a gate oxide film 34 and a gate electrode 36, the region 31 is buried under the surface of an Si substrate 32. Accordingly, as the hot electron, which was generated in the vicinity 33 of the boundary of a p layer and an n layer, loses its energy due to the phonon scattering with a lattice before it reaches an oxide film 34 and said hot electron is unable to pass the potential barrier of the oxide film 34, the fluctuation of threshold voltage can be prevented. Also, according to this constitution, the fundamental operation of the transistor is not impaired. As a result, the deterioration of reliability of the transistor caused by the implantation of hot electron into the oxide film 34 can be effectively improved without lowering the integration.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a MOS transistor is formed.

In recent years, semiconductor integrated circuits have become increasingly finer and more highly integrated.
e-Integration).

Using the channel length as a guideline for the degree of miniaturization, it is 1 to 24 m.
It is predicted that this will develop into the submicron range in the future.

This fine transistor used in VLSI is
According to the so-called scaling law. However, the gate oxide film has become thinner and the height of the channel region substrate has become higher.

A conventional micro MO8 transistor is shown in FIG.

A source region (2) and a drain region (3) are formed in a semiconductor substrate (1) as an n-type impurity region doped at around 102°/1, and a channel region (4) is formed as a source, drain, and drain region. Regions (2) and (3) are formed as P@ impurity regions with a higher concentration than in the case of long channel transistors, for example, about 10"/d.The gate oxide film 15 is It is 300 to 400 A, which is thinner than that of a long channel transistor.

Such conventional fine transistors have problems such as rounding in which the threshold voltage vT changes when used for a long time, and device reliability decreases.

In other words, the electrons flowing through the pentode operating region of the MOS transistor are transferred to the substrate region (1) and the train region (1).
3) Due to the high electric field in the p-n9 coupling depletion layer (6), hot electrons acquire high energy and generate electrons and main pairs by colliding with the lattice. They also have high energy S%.

This series of processes are called avalanche and breakdown.

This avalanche breakdown generates a large number of carriers, some of which penetrate into the gate oxide film and are captured by the oxide film at a certain rate.

(Hole has a larger potential barrier to the oxide film than electrons, and the number of holes that penetrate into the oxide film is negligible.) Captured electrons become fixed charges on the oxide film and change the threshold voltage. . Considering the gate current, 1o-
Even if it is as low as 14 A/sn' 8 degrees, the threshold voltage changes due to long-term use, causing a decrease in reliability. This is due to the fact that in fine transistors, the substrate concentration is very high, so the electric field in the pn junction in the drain region becomes extremely loud, and as the gate oxide film becomes thinner, the electric field in the oxide film becomes higher and the potential barrier of the oxide film lowers. In addition, the threshold voltage changes less easily than with long channel transistors. One possible solution is to lower the substrate concentration, but
There was a drawback that punch-through was likely to occur in the ninth position of the short channel.

The present invention has been made in view of the above points, and includes a first conductive semiconductor region, a second conductive type source region and a drain region formed in this semiconductor region, and a second conductive type source region and a drain region formed in this semiconductor region. In a semiconductor device having a gate electrode formed on the surface of the semiconductor region between them via an insulating film, at least the drain region of the source region and the primary drain region is placed below the surface of the semiconductor region. Electron injection into the gate oxide film 1 due to the fact that
The object of the present invention is to provide a semiconductor device in which transistor reliability can be improved by preventing 1:V.

Hereinafter, the present invention will be described in detail based on embodiments with reference to the drawings. FIGS. 2(1) and 2(b) show the impurity concentration from the p-n 11 joint surface and the electric field strength in the depletion layer when the drain-side p-n junction is assumed to be a step junction. As shown in FIG. 2(b), the electric field is strongest at the boundary between the Kp region and the n region. Therefore, avalanche breakdown, which largely depends on the strength of the electric field, is likely to occur at this point.

By keeping the pn junction away from the gate oxide film, generation of hot electrons can be prevented.

A schematic cross-sectional view of the structure of the present invention is shown in FIG. Figure 3 By setting K in this manner, hot electrons generated near the boundary between the p-layer and n-layer lose energy through phone scattering with the lattice before reaching the gate oxide film. -, the potential barrier of the gate oxide film cannot be exceeded, and fluctuations in the threshold voltage can be prevented. Furthermore, this structure does not impair the basic operation of the transistor.

That is, the distance d between the drain region 61 and the drain side end of the gate (to) and gate oxide film (b) is set appropriately.

The potential barrier between the gate end and the drain region C11l can be sufficiently controlled by the drain voltage and may be provided at a position where it does not act as a barrier.

On the other hand, one object of the present invention can be achieved by separating the boundary between the p layer and the n layer from the oxide film by at least the mean free path of electrons in Si. Usually the mean free path is 1
00 to 200, the potential barrier between the channel and drain region can be sufficiently lowered by the drain voltage.

Furthermore, in the conventional structure, the breakdown of the γ, rain region occurs on the surface, so-called surface bream.
It is akdown. This is a common ulk 84
Although the breakdown occurs at a lower voltage than that of the p-n11 coupling in the bulk silicon, the structure according to the present invention has the advantage that the breakdown occurs in the bulk silicon and the withstand voltage is improved.

Next, an easy and reliable manufacturing method for rounding to realize the structure according to the present invention will be explained with reference to FIG.

First, as shown in FIG. 4(a) K, the surface of the silicon substrate was made to have a value of 300 A, and this was used as a gate oxide film. In order to obtain the desired threshold voltage, poron was irradiated with 50 keys.
x 10”/a11 selective ion implantation and further 10 h
K poly-81 was deposited at 300OA and poly-
An n-type impurity is introduced into 8i by POCl3 diffusion or PSq diffusion to lower the resistance, and 9gipoly-81 and an oxide film are patterned to form a gate electrode.

Next, impurity ions are selectively implanted into the portion that will become the channel region, and the threshold voltage is controlled to a desired threshold voltage.

Threshold voltage control can also be achieved by selecting the degree of impurity penetration into the silicon wafer used, in which case channel ion implantation can be omitted. Next, Figure 4 (b
), after applying the resist ■, selectively create openings and apply arsenic at 50 KeV 2 x 1r)''/
CD ions are implanted to form a source region. Then the fourth
As shown in Figure (e), resist is applied, openings are selectively formed, and arsenic is applied at 500 KeV at 2 x 10”/
CSF ions are implanted to form a drain region so that the arsenic concentration peaks at approximately 0.28j+m from the surface of the 8i substrate.

Thereafter, after stripping off the resist, heat treatment is performed at 1000'C for 10 minutes to activate arsenic in the source and drain regions. As an impurity to be ion-implanted into the drain, arsenic has a small diffusion coefficient.

In order to obtain the structure of the present invention, it is possible to control the process with high precision and is optimal. In addition, any impurity that becomes an all impurity in the 81 substrate may be used, and the present invention can be realized even with phosphorus or the like.

In addition, in the case of a p-channel transistor, the source
For forming the train region, an element such as boron that becomes a PW impurity in Si may be used.

This is because, as explained above, ion implantation is used to form the drain region in the present invention.

The source and drain can be formed with self-alignment lines relative to the gate, making it ideal for fine devices and highly integrated LSIs.

However, since the gate and the train are separated from each other compared to the conventional structure, the gate-drain capacitance is small and Miller electrodynamics is reduced.

Next, another embodiment of the present invention will be described with reference to FIG. In the above embodiment, only the drain region (51) is connected to the St substrate (52).
The source region (9) buried below the surface is shown in Figure 5.
53) can also be buried in the same way.

The source region (53) is about 0.0 mm away from the gate oxide film (54).
If the distance is about 2s, the Bul between the north and the board
Due to lt-in pot@ntial and the extension of the depletion layer from the gate side due to the gate voltage, the source channel can be sufficiently connected.

In the case of this embodiment, the MO8) transistor is bidirectional, has more generality, and has the advantage that the manufacturing process is simplified because the source region and drain region can be formed at the same time.

In addition, as another method for obtaining the structure of the present invention, first, a drain region is formed on the surface of the 81st layer with a thickness of about 0.211m.
Epitaxially grow and bury the drain, then
There is also a method of forming a source region and a gate electrode.

As described above, by using the present invention, it is possible to effectively improve the low reliability of transistors caused by the injection of hot electrons into the gate oxide film, which is a big problem in fine transistors, without reducing the degree of integration. Moreover, the capacitance between the gate and V1 can be reduced.

In addition, based on the above explanation, an N-channel rJO8 transistor is a device on a silicon JIl board! Although we have described the case where it is fabricated, it can also be applied to P-channel MO8)2 transistors, and furthermore, it may be fabricated on an insulating substrate. J.O.
Of course, the same applies to s transistors as well.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional schematic diagram showing an M08 transistor with a conventional structure, Figures 2 (a) and (b) are diagrams showing the substrate impurity concentration distribution and electric field strength distribution of the pn junction, respectively, and Figure 3 is a diagram showing the 1
FIG. 4 is a schematic cross-sectional view showing the transistor structure of the present invention (
1) to (C) are cross-sectional diagrams illustrating the rounding manufacturing process for realizing the present invention; FIG. 11E5 is a cross-sectional schematic diagram showing another embodiment; 30... Source area. 31...Drain region. 32...Substrate area. 34...Gate oxide film. 36...Gate electrode. 44.46...Resist. (7317) Agent Patent Attorney Noriyuki Chika (Haga1
name) Fig. 2 P1 # ji (plane 0, ri 1 position bn f'-n joint surface 1)

Claims (1)

[Claims] tl) A semiconductor region of an alE1 conductivity type, a source region and a drain region of a second conductivity type formed in this semiconductor region, and an insulating film on the surface of the semiconductor region between the north region and the drain region. A semiconductor device having a gate electrode formed through a gate electrode, wherein at least the drain region of the source region and the drain region is buried under the surface of the semiconductor region. (2) The semiconductor device according to item 1 of the patent scope, wherein the drain region is provided with a diameter of at least 100 A or more.