JPS5832456A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To substantially simplify the manufacturing process as well as to contrive high speed operation and high density for the titled device by a method wherein a high density inert base layer and an emitter are formed in a self- matching manner by performing a mask-matching. CONSTITUTION:An n<+> buried layer 12, an n type epitaxial layer 13, a polycrystaline Si 14, an isolation oxide film 17 and an active base layer 18 are formed on a p type semiconductor substrate 11. Subsequently, after a polycrystalline Si 19 and a nitride Si film 20 have been formed on the whole surface, a patterning is performed on a resist film 21. Then, an etching is successively performed on the film 20, the Si 19, and a nitride Si film 16 using the film 21 as a mask. A high density inert base layer 22 is then formed by implanting a B<+> ion under the condition wherein the film 21 is left over. Then, after the film 21 has been removed, an oxide film 23 is formed on the Si 14 by performing selective oxidization using the film 16 as a mask. The film 20 is then removed. At this time, a side etching is performed on the film simultaneously. Then, the exposed base oxide film 15 is removed. An oxide film 24 is then formed by performing selective oxidization using the film 16 as a mask. Then, the film 16 is removed and an emitter 25 is formed in a self-matching manner.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and the base resistance is extremely small compared to conventional bipolar transistors, and the high frequency characteristics are improved by forming the base resistance in a self-aligned manner. This technology has been improved to achieve higher speed and higher density.

In recent years, semiconductor devices have become increasingly denser and faster, creating a need to reduce element dimensions and further improve performance.

Generally E CL (Emitter Coupled
Logic) circuit, it is effective in improving the delay time (that is, increasing the speed) (Tr parameters in the small current region are: ■ base resistance rbbl, ■ base-collector capacitance CBc1, ■ gain bandwidth product fT1. ■ The isolation method is widely used as a method to reduce the base-collector capacitance CBc and other capacitances.In order to increase the gain bandwidth product fT of Improvements have been made by making the base width thinner.

Therefore, in order to further increase the speed of the Tr, an important issue is how to reduce the base resistance rbbl. In order to maximize the speed and density of transistors, it is necessary to reduce the junction capacitance by using an insulation separation method and further to reduce the base resistance as much as possible.

FIG. 1 shows the structure of a bipolar transistor in a conventional insulation isolation system. In FIG. 1, 1 is a p-type semiconductor substrate, 2 is an n+ buried layer, 3 is an n-type epitaxial layer, and 4 is a p-type semiconductor substrate.
is an isolation oxide film formed by selective oxidation, 6 is a base layer, 6 is an emitter, 6' is a collector contact portion, 7
1 is an oxide film for opening a contact portion, and 8 indicates an At wiring.

In the insulation isolation method shown in FIG. 1, the side surfaces of the base layer 6 and the side surfaces of the emitter 6 are partially covered with the isolation oxide film 4, so that the capacitance on the side surfaces of the junction is removed. In addition, since the isolation is formed by an oxide film, there is no need to increase the distance between the base layer and the p-type isolation region as in the pn junction isolation method, so the area of the junction can be reduced. The capacity is reduced.

FIG. 2 shows the main parts of the Tr shown in FIG. 1, and the numbers in the figure are the same as those in FIG. 1. In Fig. 2, the distance from the end of the emitter 6 to the base contact (distance # already shown in the figure) is mainly the distance between the emitter electrode 8 and the base contact.
It is determined by the distance between the base electrode and the base electrode (distance indicated by C in the figure). That is, the distance between the electrodes 8 and 8', which are made of At wiring, must be large enough to prevent short-circuiting.

By the way, the base resistance TbbI is expressed as a series resistance of two parts as follows. That is, it is expressed as a series resistance of the part immediately below the emitter (the part indicated by a in the figure) and the part from the emitter end to the base contact (the part already indicated in the figure).

The part directly under the emitter cannot be made very small because it is determined by the emitter size. The portion from the emitter end to the base contact is determined by the At interconnect spacing as described above.

Therefore, by reducing the distance from the emitter end to the base contact, the base resistance rbbl
can be made smaller. Furthermore, if the distance from the emitter end to the base contact is made smaller, the base area will inevitably become smaller, resulting in a reduction in the base-collector capacitance CBc.

In consideration of these problems, the present invention reduces the junction capacitance by using an insulation isolation method, and furthermore makes the distance from the emitter end to the base contact extremely small in a self-aligned manner. The present invention aims to provide a method of manufacturing a semiconductor device that enables higher speed and higher density by reducing the base resistance so that wiring can be easily performed without causing short circuits.

An example of a specific manufacturing method to which the present invention is applied will be shown below with reference to FIGS. FIG. 3 shows a manufacturing process in which the present invention is applied to an insulation isolation type bipolar transistor.

In FIG. 3, 11 is, for example, a p-type semiconductor substrate, 1
2 is an n+W embedded layer, and 13 is an n-type epitaxial layer, which are formed to have a thickness of, for example, 1.2 μm. 14 is pol
y si (polycrystalline silicon) to a thickness of, for example, 4000A, 16 is a base oxide film with a thickness of 6oOA, 1
6 is a nitride film that does not pass oxygen 17 is a silicon nitride film 16. Base oxide film 16゜pOl''l l1il 4. This is an isolation oxide film formed by selective oxidation after etching the n-type epitaxial layer 13, for example, 1.9
It is formed to have a thickness of μm. At this time, it is desirable to use high-pressure oxidation for selective oxidation in order to prevent deterioration of breakdown voltage due to lifting of the male buried layer 12. For example, 1000℃, 6.5K
When oxidized under the conditions of g/ct/I, an oxide film of 1.9 μm can be formed in a short time of about 140 minutes. Reference numeral 18 denotes a low concentration active base layer formed by selective oxidation and boron (B+) ion implantation, and is formed to a depth of 0.4 μm from the n-type epitaxial layer 13.

After that, a poly sit 9 of 100 OA and a silicon nitride film 20 of 600 Å are formed on the entire surface, and then a resist film 21 is formed on the emitter and collector by photolithography.
Pattern it so that it is slightly wider than the contact part (Fig. 3B).

FIG. 3 (in q, the resist film 21 is masked,
Silicon nitride film 20. The three layers of silicon nitride film 16 are etched successively. This CF4
In plasma etching using gas, the selectivity ratio between the silicon nitride film and the oxide film is 10 or more, and the selectivity ratio between potyBl and the oxide film is 26 or more, so the underlying oxide film 16 has the effect of acting as an etching stopper. ing. After etching these three layers, a high concentration inert base layer 22 is formed in a self-aligned manner by ion-implanting boron (B+) with the resist film 21 attached.

This inactive base layer 22 is a so-called graft base, and is formed to a depth of, for example, 0.6 μm, and has the role of lowering the base resistance and forming a base contact.

Thereafter, after removing the resist film 21, a 3000A oxide film 23 is formed at 0'' poty ail At by selective oxidation using the silicon nitride film 16 as a mask.

At this time, the first formed 4000A (D poty s
Approximately 1500 A of the i 14 is converted into the oxide film 23, so that 2500 A (D poty s i 14 remains). No oxide film is formed on the silicon nitride film 2o (FIG. 3D).

Figure 3 (g) shows the step of removing the silicon nitride film 2Of, which is the biggest feature of the present invention, by chemical etching with hot phosphoric acid. The silicon film is also side etched at the same time.While the 600A silicon nitride film 2o is completely etched, the side etching of the silicon nitride film 16 is approximately 0.2 to 0.3 μm. The base oxide film 16 exposed by the sand etching is removed by buffer etching.In this state, only the side-etched portion of the silicon nitride film 16 of the poty gN4 is exposed.400 OA of Tsurekara pO4y8114 remains. N-type epitaxial layer 1 is etched using a hydrofluoric acid/nitric acid etching solution.
Chemical etching is performed until reaching 3. At this time, poty sN 9 is also removed at the same time. A hydrofluoric acid/nitric acid based etching solution etches pozy st, but does not etch oxide films or silicon nitride films. In this state, the poly si of 14 is 0.7~o,s
Apertures are self-aligned at a distance of μm (Fig. 3F)
. A major feature of using the present invention is that when the silicon nitride film 2o is removed, the silicon nitride film 16 is also side-etched at the same time, so that all poly sit 4 is self-aligned.
The reason is that the aperture can be made at a submicron distance.

In FIG. 3, an oxide film 24 of 3000 Å is formed by selective oxidation using the side-etched silicon nitride film 1e as a mask. Through this selective oxidation, the formed oxide film 24 makes contact between the emitter part and the base.
This means that they are separated by a distance of 1 μm or less. After that, after removing the silicon nitride film 16 and the base oxide film 16, polysil 4 was heated at 1000 to 1500 A.
X-y te7gu.

In this state, pozy at is exposed in the portions that will become the emitter and collector Φ contacts, but an oxide film of 260 OA or more is formed in all other portions.

Therefore, by implanting arsenic (As) using the oxide film as a mask, the emitter 25 and the collector
Contact 26' can be formed in a self-aligned manner. The emitter is formed to a depth of 0.2 μm. Now the distance from the emitter end to the base contact is 1
It can be formed very small, less than μm, and the base resistance can also be made as small as possible. Furthermore, since the highly doped emitter 26 and the highly doped inactive base layer 22 are not in direct contact with each other, the junction between the emitter and the base is not deteriorated, which also has the effect of preventing noise. Then p
The device is completed by opening an electrode outlet in the ozy ail At and connecting the At wiring 26 (Fig. 3H).
.

As described above, in the present invention, a high concentration inactive base layer for lowering base resistance and an emitter can be formed in a self-aligned manner without direct contact with each other by one mask alignment, and the mask alignment process The number of steps can be reduced and the overall process can be greatly simplified. Moreover,
In the three-layer structure 1 1 <-; of the first silicon nitride film, poz7 si, and second silicon nitride film, the first silicon nitride film is also side-etched at the same time as the second silicon nitride film is removed. , the distance between the emitter and the base contact can be formed in a self-aligned manner with a distance of 1 μm or less. Therefore, the base resistance r
bb/ can be made as small as possible, high frequency characteristics are greatly improved, and high speeds can be achieved.

As described above, the present invention can be formed in a self-aligned manner, which greatly simplifies the process and speeds it up.

It greatly contributes to the manufacturing method of high-density semiconductor devices, and is also of great industrial value.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the structure of a transistor using a conventional insulation isolation method, FIG. 2 is a cross-sectional view of a main part of the transistor shown in FIG. 1, and FIG. It is a manufacturing process diagram of the main part of the device. 14, 19--...-pot78i, f 6.2
0--Silicon nitride film, 21--Resist film, 22--Inactive base layer, 23,24-
...Insulating film formed by selective oxidation, 26...
...Emitter. Name of agent: Patent attorney Toshio Nakao and one other person1 Figure 1. Figure I2 Maple Figure 3 /l /Z

Claims (1)

[Claims] A first conductive material and a first insulating film are formed on a semiconductor region of one conductive type that will serve as a base, and then a predetermined pattern made of a second conductive material and a second insulating film is formed thereon. forming using a resist film, further removing the first insulating film using the resist pattern as a mask, forming a high concentration one conductivity type semiconductor region to serve as an inactive base using the resist pattern as a mask, oxidizing using the first insulating film as a mask; side-etching the first insulating film under the second conductive material and oxidizing using the remaining first insulating film as a mask; and oxidizing the remaining first insulating film as a mask; 1. A method of manufacturing a semiconductor device, comprising the step of forming another conductive semiconductor region to serve as an emitter from a portion from which an insulating film has been removed.