JPS5831645A - Timing regenerating system in orthogonal modulation type modem - Google Patents

Abstract

PURPOSE:To digitize a timing regenerating section of an orthogonal modulation type MODEM, by forming a phase error signal for timing regeneration based on Baud-rate information after digitizing through the demodulation of a modulated signal. CONSTITUTION:An input signal 1 becomes an eye-pattern (d) via a BPF2, an AGC3, tuning detectors 4, 5, an A/D converter 101, and LPFs 102 and 103. A sampling pulse (c) A/D-converted at the maximum opening of the pattern (d) is transmitted from a frequency divider 107 to an A/D converter 101 in a frequency N-times that of the pattern (d), allowing to obtain a Baud-rate information (a) N-times that of the pattern (d) from a transmission Baud-rate pickup section 104. From this signal (a), the phase error of a reproduced clock pulse to the modulation timing is detected with a phase comparison circuit 105. Based on this output, the reproduced clock pulse is synchronized with the modulation timing with a staff/destaff controlling circuit 106.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing recovery method in a quadrature modulation modem, and more particularly to a method for digitally performing timing recovery.

The QAM (I! cross modulation) method is suitable for high-speed transmission, for example, 9600 bp @ and modulation rate 2400/-.

Below is a block diagram of a conventional QAM modem (Figure 1)
The tizing playback method will be explained with reference to the waveform diagram (FIG. 2) for explaining its operation.

FIG. 1 shows an IFi input signal, and it is assumed that this input signal IFi is orthogonally modulated. 2ti pan h%
, 4 filter (B P F )eThis B P F 2tj has a function of removing noise contained in the input signal 1. 5Fi automatic gain controller (Ae
c) shows Jin's AGC3Fi, which has the function of restoring the gain of the noise-cut signal.

The signals output from the AGC 5 are simultaneously supplied to the synchronous detection circuit 4.5. This synchronous detection circuit 4.5Fi is a circuit for obtaining a reception base non-r signal. For example, if the quadrature modulated signal is f(t) = dt)Coswa, t + 7
(11) If @ii, yct, then the piI period detection circuit 4ij, for example, is a circuit that multiplies f(s)KCO@viewt, and the synchronous detection circuit 51d f(t)Ksin
This is a circuit that multiplies vyωct. In other words, the output of the synchronous detection circuit 4 becomes: On the other hand, the synchronous test
The output of the direction path 5 is as follows.

The output signal of the synchronous detection circuit 4 (represented by equation (1)) is filtered through a low-pass filter (LP) that cuts harmonic components.
F) 6, the output signal of the synchronous detection circuit 5 (shown by equation (2)) is filtered through a filter (L) that cuts harmonic components.
PF) 7 respectively.

This LPF6 height g411i cut, LPF7Fi harmonics It has the ability to cut.

The output signal Vin is also used.

In order to obtain Zeley P information from this base non-r signal,
The configuration is such that the flat signal is input to BPF8, and the X-+l input signal is input to BPF9.

The signals are input to absolute value circuits (rectifier circuits) 10 and 11, respectively, and then added by an adder 12, and further added at a frequency of 2400 Hz.
It is input to BPFL 3 of .

As a result, the BPF of 1200Hz is 8.9. Absolute value circuit 1
0.11, an adder 12. The transmission 2-rate information extracting unit 14, which includes a BPF13 with a frequency of 2400 Hz, outputs Zee rate information such as that shown in FIG. 2 as a 2400 Hz sine wave. For convenience, this is referred to as analog I-rate information.

This rate information Aij is input to the phase comparator 15. The phase comparator 15 is a circuit that compares the phase of the square wave (FIG. 2) B output from the frequency divider 17 with the rate information A, and outputs a signal with the phase difference as the pulse width. be.

The signal output from this phase comparator 15 is stuffed/
It is configured to be supplied to the distuff control circuit 16 and also to the branch unit 17 .

The stuff/distuff control circuit 16 is a circuit that receives a high-order clock from a clock generator (not shown) and performs stuffing/distuff processing of the high-order clock based on the signal sent from the phase comparator 15. be. Here, stuffing/distuffing refers to processing that adds or deletes several bits of clock from a high-order clock.

In this way, stuff/distuff control circuit 16
The predetermined lock output from the divider 17Fi is input to the divider 17, which divides the frequency of the clock given to the divider 17Fi and sends it to the phase comparator 15. The sampling pulse (tJX2hc) is applied to the /D converter 18, and the auto'4I
The configuration is such that it is supplied to the J equalization/judgment scrambler circuit 19 as various clocks necessary for automatic equalization/judgment scrambler processing.

On the other hand, the output signal of the phase comparator 15 is input to the branching unit 17 as an initial setting signal.

The following describes the operation of this modem from the 7th running state to the initial setting and the establishment of synchronization.

In the free run=y state, the eye pattern for x(t) output from 1f-1 and LP11 is
The eye pattern opens and closes repeatedly like gAD.

On the other hand, since the divider 17 is also in a free roughing state and is outputting the amplifier/debug pulse C1, from the point of view of the Zee rate information person, there is a phase difference. The output signal B of the divider 17, which is output to the phase comparator 15, rises with a delay of e from the zero point of the I-rate information A.

Therefore, the output signal of the phase comparator 15 becomes a Norse corresponding to e and is given to the branching unit 17 as an initial setting signal. The branching unit 17 causes the output signal of the branching unit 17 to rise and output 9 times earlier (point P in FIG. 2). As a result, there is no phase difference, and the rising timing of the signal C2 sent to the A/D converter 18 also coincides with the timing of the maximum amount of eye pattern/D. Therefore, when the eye J turn of x(t) is at its maximum, A/
A D converter 18 can perform digitization.

Further, each time the Zee rate information A repeats one cycle, a pulse corresponding to the phase error is generated from the phase comparator 15Fi#-rate information 1iA and the output signal of the divider 17, and this is controlled by the stuff/distuff tlllj. Output to circuit 16. As a result, the stuff/distuff control circuit 16 adds or removes a clock from the high-order clock and outputs it to the branching unit 17 . The splitter 17 separates this signal and outputs it. By the aforementioned stuffing/distuff processing, Fi synchronization is established with the zero point of the Zee rate information at the second @P3 point, the rising edge of the output signal of the branching unit 16, and the 9th pulse C of the splitter 16. ! I] T-
Aino (sampling in synchronization with the maximum opening of the turn)
9 pulses C are output at a cycle of 2400 Hz, and A/D conversion is performed at the optimum position.

However, with the availability of inexpensive Zorosena and the ability to perform various digital processes at high speed,
By reducing the number of analog parts and converting them to digital, it is possible to reduce the size and cost.

This decision was made in light of the circumstances explained above. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a typing regeneration method for digitizing the timing regeneration section of a quadrature modulation modem.

Therefore, in the present invention, it was decided to generate a small amount of phase error information for tie-in/1% generation based on one rate information after digitizing the modulated signal with 113N. .

A detailed explanation will be given below based on examples, and the gist thereof is as follows.

■ First, pace/? A/D conversion is the process of sampling a signal at an integer frequency twice the rate of 11 to obtain digitized rate information.

Q: Processing the m-rate information obtained in step (1) to detect the phase width difference of the reproduced clock pulse with respect to the modulation timing.

(2) Synchronize the reproduced clock pulse with the reception timing based on the phase error information Kjli obtained in (2).

Regarding the above item (2), this is a summary of the table of contents of the processing procedure in the embodiment for detecting the initial phase error easily and with relatively high accuracy, which will be described later.

In this case N=5.

- Select the Zee rate information Xm1n'i (with the minimum absolute value) from the rate information obtained in ■, and select this minimum 2
- Determine the sampling timing of another I-rate information relative to the rate information, and whether the sign thereof is positive or negative; and, as a result, select the first phase error range.

OW! and selecting a second phase difference range Wi based on the sign of the minimum I-rate information.

θ Furthermore, the minimum l-rate information is compared with a threshold of 1/predetermined value of the second phase error range,
and determining an intermediate value within this third phase error range as the phase error.

FIG. 5 shows a block diagram of a circuit that realizes the methods 0 to ■. In FIG.
The configuration is the same as that shown in the figure, and orthogonal component signals are obtained using a synchronous detector of 4.5t.

101 indicates an A/D converter. This A/D converter 101 is a tortoise for digitizing the output signal of the synchronous detector 4.5. Reason for placing this A/D converter 101 after the synchronous detector 4.5 #1: If it is placed after AGc3, then sample! This is because high speed is required. Therefore, in theory, if it meets the purpose of digitization, the automatic equalization judgment scrambler circuit 19
It would be better if it was in the earlier stage.

102.10! The LPF for the IFi digital wave is shown. L P F 102.103tj, the roll-off characteristic is steep with 10% to 15%. L P F
From l 02, as in Fig. 1, for example, x(z)sc
The corresponding digital signal is transmitted from the LPF 103 to Fiy (
A digital signal corresponding to t) is output.

104Fi, transmission--this transmission I, indicating the rate extractor
-Rate extractor 10.4 is a digital version of each part of the transmission I-rate extractor 14 shown in No. 1- corresponding to the input signal being a digital signal, and is an A/D
Together with the converter 101, it has the function of obtaining digital Zee rate information corresponding to analog rate information subjected to insoring at a frequency that is an integer multiple of the 11 rate from the baseband signal described in Summary (2) of the present invention. In other words,
The A/D converter 101 is supplied with a sampling pulse C, and A/D conversion is performed every cycle of the sampling pulse C.
The m-site information a, which is the output signal from 4, is output as a discrete value having a magnitude and a positive/negative sign for each of the above-mentioned frequencies. The above configuration is the first means.

105tl, showing a phase comparison circuit, this phase comparison circuit 1
05Fi, for example, is composed of a micro combination crystal and has the functions of Φ to θ.

The function of Φ~ of the phase comparator circuit 104 is performed by simply working through the initial setting circuit 108 at the time of initial setting.
i, the sign of the m-item information a at the rising edge of the branch output signal fed back from the branch unit 107 is stuffed/
The signal is sent to the distuff control circuit 106.

Based on the positive and negative signs output by the stuff/distuff control circuit 1061j and the phase comparator circuit 105 during normal operation, it adds or deletes several bits of Jrus from the input high-order clock.

Brancher 107Fi, stuff/distuff control circuit 1
06 and the initial setting circuit 10B, and outputs a signal with a predetermined period. Sypurin! output from this branch unit 107! The Nors C is output to the A/D converter 101, the 6 grains of black is output to the automatic solubilization judgment block 2 frame circuit 19, and the branch output bI11 phase comparator circuit 10.
It is configured to be fed back to 5.

Initial setting port 4108tj, phase comparison circuit 1 during initial setting
A branch unit 10 receives and receives the phase error signal output from 05.
7.

In the above configuration, the stuffing/distuffing control circuit 106, the branching unit 107, and the initial setting circuit 108 have the function of carrying out (1) the gist of the present invention. The above is the second and third
This is the configuration of the means.

Here, in the above circuit configuration, 9600 bplI (
In a modem with a modulation rate of 2400/-), I-rate (
The present invention will be described in detail below, taking as an example a case where sampling is performed at a sampling frequency three times that of 2400 Hz (7200 Hz).

Input signals IFi, BPF2, AGC3,
Synchronous detector 4.5, A/D converter 101, LPF
Through 102.103 it becomes Ai I Setan d, but that! (t) Eye pattern of component a#i 4th - 2
The shrimp will be wide open every 4001'L.Therefore, if you send the sampling pulse C to check the A/D at the maximum opening, you can achieve the optimal tying and compare with the thread line. I can do it.

Therefore, the frequency of the sampling pulse C sent from the divider 107 to the A/D converter 101 is set to 7200 Hz.

Then, for every 7200Hg of the m-rate information aa output from the transmission rate information extraction unit 104,
, xs −”.

However, in the state of 7 re-running where timing regeneration synchronization is not established, the rising edge of the output signal S fed back from the 1 frequency divider 107 to the phase comparator circuit 105 and the l
- The phase difference between the point information a and the zero point is e. However, in order to find this e, tfX s, X s, X s
・If we don't estimate the sine wave like the broken line from...
Since Xs, Xs, Xs... are discrete values, e cannot be determined.

Therefore, the phase comparator circuit 105Fi of this embodiment functions as a microconbeater to estimate the sine wave at i, and in order to obtain a highly accurate phase error, the Kll dispersion value 'X 1, x 3Xs (1
Input the I-rate (information) present during the cycle and check their magnitude.

Here, the phase error e and the ze rate information
, ,X, ,xl will be considered. Figure 5 is 1
It is a graph showing the relationship between phase difference θ and Xl, Xl, and Xs. Moreover, the sixth direction is a partially enlarged view of the fifth factor. Assuming that sampling is performed at a certain point on this graph, the distance between the intersection of the horizontal axis and xIXs and Xl and the 0 point is l.

The magnitude of mm1jXs, Xs,
There is a difference of 0, and the phase shift with respect to Xa is θt,
Phase shift rjQ based on Xmaro.

Once either the phase melee iiem or i with respect to
- It is 41111 that the phase shift for the rate information (tf X s in this example) is determined.

For this purpose, we compare the sizes. This comparison procedure may be performed by sequentially comparing all data, by leaving only small l-rate information, or by any other comparison method. In this example, the minimum amount of information is #iX. Next, the phase error of l-site information xm is ±180
can be taken. IIJ, it is either delayed or advanced to 180@. This is because for those that can measure ±180@, that is, 360°, they enter the next cycle. Therefore, the sign of other i-rate information (for example, Xs) during one game period in which Xs is 1 is determined. Since Xmtj is positive, in the 41st, the range 7'1.XI can exist. p
m, P = medium Bg is selected as the first phase error range. Here, the first phase error range 11fl Id
l, Xs is the cutoff range -C: @ff), 60@ range.

Next, in order to determine which Kx value exists in the first phase error range l#ius, the sign of the minimum l-item information XI is checked. Then, since xl〈0, P
It can be seen that the range is in the lower half of s. The lower half range of this P yuzumi is the second phase error range, where Xs is negative and 60
Since it is less than half of °, -30@<8 (phase shift)<0.

Next, Ma (Kurokonobi Tame - Yuke s Minimum F) d
Absolute value of rate information IX, l and threshold value 1 vs.
Compare with hl. Here 1Vthj=lK X1l(
However, l Vth lrt, corresponding to the area of 30'' units obtained at this stage 11t, is determined by -*D, K#i constant,
In this case, the value is set to Xl. ). Then, in this example, Id fx DIVthl is 6
$b, -50<8<-15°.

Therefore, the third phase error range 11tj -50° to -15
Next, let the intermediate value within the third phase error range of the microconverter d1 be the phase error.

In this example, the median value = median value θ=θ knee 22.5°.

In this way, the phase comparator circuit 105 outputs the phase error θ as a digital signal to the initial setting circuit 108. In this example, it is assumed that a value displayed 24 times in units of 7.5@ is output. Therefore, it is output as -22,5'h-s.

Now, the initial setting circuit 108I/i, for example, a timer indicated by the reference numeral 201 in FIG.
5, inputs a clock of 24 times 7.2 KHs, and outputs a signal to the reset terminal of the branching unit 107.

Now, it is preset by the timer 201tlj,e, and in this example, -3 is preset and 7.
A clock of 24 times 2KHz is output.

Then, since -3 was preset, when 1/7200 seconds passed from the time when XS in Figure 4 was obtained, 3 clocks (3X1/7200X1/24 seconds) earlier, the reset signal or tie! As a result of output from -201, there is no phase error θ, the rising edge BL of the frequency divided output signal and the sampling frequency C1 are outputted. It can be seen that at this time, the Aino Turn dFi is at its maximum opening.

In this way, after initial settings have been made and synchronization of timing playback has been established, an operation is performed to detect the absolute value of the rate information (X6), which should normally be a 0 value, and its code is stuffed/discarded. Output to the stuff control circuit 106. Stuff/distuff control circuit 106 #''t1 From this result, one or several bits are added or deleted from the island clock. This makes it possible to establish simultaneous synchronization.

As explained above, according to the present invention, it is possible to digitize the timing reproducing section of a quadrature modulation modem. Therefore, it is possible to realize miniaturization and cost reduction of the circuit. Furthermore, the method of the present invention is suitable for program processing,
In particular, if N=5 as in the *S example, it can be realized only by comparison operations without performing complex calculations, which is convenient for high-speed modem timing processing. In other words, since it does not include time-consuming processing such as multiplication, it will be understood that this method is optimal as a tie-inter playback method.

In this embodiment, the sampling of integral multiples of the rate is tripled, but other integral multiples are also possible, although the comparison process becomes complicated.

Furthermore, the phase comparator circuit can also be realized as an assembly of comparators and gates.

[Brief explanation of drawings]

The first part is a block diagram of a conventional modem. Figure 2 is a waveform diagram to explain the conventional example. Figure 3 is a block diagram of a modem to which the present invention is applied. Figure 4 is a waveform diagram to explain the present invention. Fig. fIA5 is a graph for explaining the phase shift for explaining the present invention. Fig. 6 is a partially enlarged view of the fifth factor. Fig. 7d is a block diagram of the main part of a modem to which the present invention is applied. 2...Band male filter...Automatic gain control circuit 4.5...Synchronous detector 101...A/D@converter 102.103...Lono filter 104...Transmission rate information extraction unit 105.-Phase comparison circuit 106...stuff/distuff control circuit 107.
... Frequency divider 108 - Initial setting circuit 201 ... Timer patent applicant Tokyo Shibaura Electric Co., Ltd. (7414) Agent Patent attorney Hon 1) Takashi

Claims (2)

[Claims] (1) A baseband signal is generated in a modem that synchronously detects a quadrature-modulated north reception signal to obtain an eastpant signal, and reproduces the desired chronolux based on the rate information included in this eastpant signal. A first means for obtaining digital rate information corresponding to sampling analog rate information at a rate N times faster than the I-rate by digitizing the information; The present invention is characterized by comprising second means for detecting a phase error of the reproduced clock signal R with respect to the second means, and a fifth means for synchronizing the reproduced clock signal A with a modulation tie based on the output from this means. Orthogonal II! Timing recovery method in true system i-dem. (2) When N is 6, the second means is a Santa ringer of another 1 for the one with the minimum absolute value among the continuous 51i digital Zee rate information, the timing before and after, and the other 1. A first phase error range is selected based on the sign, and a second phase error range is selected, which is either one of the first phase error ranges divided into two based on the sign, for which the absolute value is the smallest. , Furthermore, the second value is determined from the magnitude of the minimum absolute value for a predetermined thread shield level.
is constant at a third phase error range 1 within the phase error range of , and the sixth means is initialized based on the phase error determined within the third phase error range. A timing recovery method in a quadrature modulation modem as described in the first section of the patent.゛