JPS6016049A - Demodulator - Google Patents

Abstract

PURPOSE:To release different-frequency pseudo acquistion and to expand the range of normal synchronism acquistion by detecting an eye pattern of a base band signal obtained through synchronism detection to discriminate the correlativity between adjacent time slots. CONSTITUTION:A poly phase modulation input signal is inputted to phase detectors 11, 12 detected synchronously by orthogonal regenerated carriers C1, C2, its output is inputted to LPFs 14, 15 and then base band signals B1, B2 are obtained. The signals B1, B2 are rectified by full wave rectifiers 21, 22 and rectified outputs G1, G2 of the eye pattern are sampled respectively by FFs 23, 24 and applied to an exclusive OR circuit 27. The correlation between adjacent time slots is discriminated from an output signal I of the circuit 27 by using FFs 25, 26 and an exclusive OR circuit 28, and this output passes through an LPF29 and a reset signal R is obtained. The signal R becomes logical L at the normal synchronism and become logical H at wrong synchronism and the signal R at a level of logical H opens an output switch device 19 of a phase error detecting circuit 19 to interrupt a phase locked loop and release the different-frequency pseudo acquistion, thereby restoring the state to the state of out of out of synchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulation device (2) applied to a digital wireless communication system using a polyphase phase modulation method or a multi-value quadrature amplitude modulation method.

Conventionally, the demodulator on the receiving side applied to this type of communication system consists of a phase detector that performs synchronous detection using a carrier wave that is regenerated by receiving an input signal, a low-frequency wave generator, two phase error detection circuits, and a voltage-controlled oscillator. It consists of a feedback system PLL (phase locked loop). According to such a configuration, the voltage controlled oscillator is controlled according to the phase error output obtained from the phase error detection circuit, and generates a frequency output equal to the carrier wave included in the received signal in the synchronous pull-in state, which is used for the above-mentioned reproduction. It is given to the phase detector as a carrier wave.

In this state, a baseband demodulated output is obtained from the output of the low-band ν wave generator.

However, the demodulator described above causes a synchronization pull-in state even though the regenerated carrier frequency generated by the voltage controlled oscillator is different from the carrier frequency of the received wave.

Such a state of erroneous synchronization is called a different frequency pseudo-entrainment phenomenon.

Due to the existence of this phenomenon, the normal synchronous pull-in range is significantly narrowed, and once the normal synchronous pull-in state becomes out of synchronization, it takes a long time to return to the normal synchronous pull-in state. An object of the present invention is to detect an eye pattern of a baseband signal wave obtained by synchronously detecting a multiphase phase modulation input or a multilevel quadrature amplitude modulation input using a phase detector, in order to eliminate the above-mentioned conventional drawbacks. Then, by determining the correlation between adjacent time slots, the different frequency pseudo pull-in is canceled.

It is an object of the present invention to provide a demodulator that can widen the range of normal synchronization pull-in.

According to the present invention, first and second
a phase detector; first and second low-pass filters that receive output signals from the first and second phase detectors and remove unnecessary high-frequency components, respectively;
and a phase error detection circuit that receives first and second baseband signals respectively obtained from a second low-frequency F-wave device and detects a phase error between a carrier wave of the input signal and the reproduced carrier wave; a third low-frequency p-wave device that receives the phase error signal obtained from the phase error detection circuit and removes unnecessary high-frequency components therefrom;

A regenerated carrier wave is generated under the control of the output signal of the third low-pass filter, and its output is applied directly to one of the two phase detectors, and to the other through a 90 degree phase shifter. In the demodulation device for demodulating a multi-phase phase modulation signal or a multi-level quadrature amplitude modulation signal, the demodulation device includes a voltage controlled oscillator that adds First and second sample circuits that sample their respective outputs, and a correlation between the respective outputs of these first and second sample circuits are detected to determine whether the synchronization is in a normal pull-in state or in a pseudo-pull-in state. A circuit is provided to determine whether the

Furthermore, a circuit for cutting off the output of the phase error detection circuit is added inside the phase error detection circuit or on its input side (or output side), and when the judgment circuit determines a pseudo-synchronization pull-in state, A demodulator is obtained in which the output (5) of the phase error detection circuit is controlled to be in a cut-off state by the output of the determination circuit.

Here, in order to facilitate understanding of the present invention, a conventional example of a demodulator will be described with reference to the block diagram of FIG. Note that this example is applied when demodulating a four-phase phase modulated wave signal as an input signal, but basically it can also be applied when using other multiphase phase modulation methods or multilevel quadrature amplitude modulation methods. can be explained similarly. In this figure, an input signal Sin subjected to quadrature phase modulation is applied to two phase detectors 11 and 12, respectively, and is synchronously detected by mutually orthogonal reproduced carrier waves C1 and C2, respectively. The detection output D1 of the phase detector 11 and the detection output D2 of the phase detector 12 become baseband signals B1 and B2, respectively, after unnecessary high-frequency components are removed by low-pass filters 14 and 15, respectively. These baseband signals Bt and B2 are used as output signals Bout as demodulated signals for original data reproduction.

It is applied to the phase error detection circuit 16. This phase error (6) difference detection circuit 16 inputs these baseband signals Bt and B2, and calculates the phase difference between the carrier wave of the received signal and the phase of the recovered carrier wave applied to the phase detectors 11 and 12. A phase error signal E containing the error θ as a component is output. The phase error signal E obtained from the phase error detection circuit 16 is applied to the voltage controlled oscillator 18 after unnecessary high frequency components are removed by the low frequency filter 17 . The voltage controlled oscillator 18 is controlled by this error signal and outputs a reproduced carrier wave that is phase synchronized with the carrier wave of the received signal. Voltage controlled oscillator 1
The output signal C1 of No. 8 is directly applied to the phase detector 11 as a regenerated carrier wave, and at the same time creates another regenerated carrier wave C2 orthogonal to the output signal C1 via the 90 degree phase shifter 13. applied.

In such a configuration, let f be the carrier wave frequency of the received input signal Sin, and let fv be the frequency of the reproduced carrier wave C1 obtained at the output of the voltage controlled oscillator 18.

Normal phase locking occurs at f8-fv, but in addition to this condition, phase locking also occurs under f8-fv±(fc/8), where +fc represents the modulation Sindel frequency.

The operation when this non-normal erroneous synchronization phenomenon (different frequency pseudo pull-in) exists will be explained below with reference to the graph in Fig. 2.Now, when normal S v normal synchronization is performed at f , if the carrier frequency f8 of the received signal decreases for some reason, the normal synchronization retention range P-
Synchronization is lost at point P, which is the lower limit of Q.

C: Different frequency pseudo pull-in is performed in the false synchronization holding range A-B near f5=fv--T. Once a different frequency pseudo pull-in state occurs, even if the carrier frequency f8 of the received signal increases again and approaches fv, the pseudo pull-in will continue until it reaches point B, which is the upper limit of the false synchronization holding range A-B. Since it is maintained without falling off, the pull-in range of regular synchronization is significantly narrowed.

The above also applies to the operation due to pseudo-retraction, f=t+Ls
The same explanation can be given in relation to the false synchronization holding range C-D near -8vB. In this way, in conventional demodulators, there is a phenomenon of pseudo-pulling of different frequencies;

If normal synchronization is lost and incorrect synchronization occurs, normal synchronization cannot be achieved while incorrect synchronization is maintained.

As a result, the pull-in range of regular synchronization is significantly narrowed.

Here, we will analyze the occurrence of the above-mentioned different frequency pseudo-entrainment phenomenon. First, referring to the baseband signal waveform in FIG. 3, during normal synchronization in FIG. 9(a), all sample points 1, 2, 3, . ..., the signal waves all show binary values, whereas in the case of erroneous synchronization as shown in Figure 2(b).

Binary and ternary values appear alternately. To further explain this phenomenon using the vector coordinates indicating the signal points in FIG.
, D become binary points on each axis after orthogonal detection, as shown by R, S and T, U, which are orthogonal projections onto the P axis and the Q axis, respectively. On the other hand, during the erroneous synchronization vB due to different frequency pseudo attraction of f=f±(Z (= )), the phases of the reproduced carrier waves C1 and C2 are on the P axis.

In addition to the Q-axis, phase synchronization is also achieved on the Y-axis and the Y-axis, which are rotated by 45° (2π/8 radians) from the P and Q axes (9), so signal points A, B, C, and D are Three points A, O, and C are orthogonally projected onto the axis, and three points B, O, and D are orthogonally projected onto the Y axis. Namely.

At the time of false synchronization, the phase of the recovered carrier wave at each sample point is, for example, P −+ X −+ Q −+ Y→(
-P)→(-X)→(-Q)→(-Y)→P as the phase synchronizes while rotating, so the eye/mother turn alternately repeats binary and ternary values as mentioned above. .

Therefore, the purpose of the present invention is to detect a special signal correlation between adjacent time slots in response to the pace/gundo signal that appears at the time of erroneous synchronization due to the above-mentioned conventional example of pseudo-induction of different frequencies, and to use this as a reset signal. The purpose of this method is to cut off the phase error signal that controls the voltage controlled oscillator and apply a disturbance instead to remove the false synchronization.

Next, examples will be given of nine demodulators according to the present invention,
This will be explained with reference to the block diagram in FIG.

This example shows the case of demodulating the same four-phase phase modulated input signal as in the conventional example in Fig. 1, and reference numbers 11 to 18 are indicated by the same symbols as in the conventional example (10). It has the same functionality. however.

A switch 19 with a cutoff control function is provided on the output side of the phase error detection circuit 16 , and is connected to a low-frequency F wave generator 17 via the switch 19 .

Further, the baseband signals B1 and B2 obtained from the low-pass filters 14 and 15 are transmitted to the full-wave rectifier 21, respectively.
and 22, resulting in full-wave rectified signals G1 and G2 in which the negative portion of the voltage is folded back. These full-wave rectified signals G1 and G2 are then sampled by flip-flop circuits 23 and 24, respectively, to generate binary dezotal signals H1 and H2.

Output signals H1 and H2 of Fritzno flop circuits 23 and 24 are applied to exclusive OR circuit 27.

Produces an exclusive OR output ■. This output I is supplied to flip-flop circuits 25, 26 . and exclusive OR circuit 28
The exclusive OR between two adjacent bits is taken by
An output signal can be obtained. This output signal is the low frequency F wave generator 2.
After removing unnecessary high-frequency components caused by thermal noise and the like contained in the signal, a DC signal R is obtained as an output.

This signal R controls the switch 19 as a reset signal to return to the asynchronous state according to its value.

This reset signal R has a logic level of ° during normal synchronization.
``L'' (Low), and in the case of incorrect synchronization, it takes the logic level I (H'' (T(igh)), so the switch 19
If this reset signal R is set to open only when it is at °°H'', the phase-locked loop will open at the time of incorrect synchronization, and the state will be returned to the out-of-synchronization state.As a result.

As seen in Figure 6, S v near f=f±(mu)
8 No false synchronization due to different frequency pseudo pull-in occurs. That is,
The normal synchronization pull-in range is between E and F, which is significantly larger than the normal synchronization pull-in range between B and C by the conventional demodulator shown in FIG.

Here, the generation process of the reset signal R will be explained in detail with reference to the time chart of FIG. 7 and Table 1. 7(a) shows the operating waveforms of the signals G15G2, H1sH2, etc. during normal synchronization, and FIG. 7(b) shows the operating waveforms of signals G15G2 and H1sH2 during erroneous synchronization, respectively. In these figures, ■ is the threshold voltage for sampling (A/'D conversion),
Arrows indicate sample points. During regular synchronization in Figures (,), the full-wave rectified waveforms G1 and G2 are as shown in waveforms (1) and (2).

Take logic level H# at every sample point. Therefore, as shown in Table 1, the reset signal R is L
”.On the other hand, in the case of incorrect synchronization as shown in Figure 2(b), the full-wave rectified waveforms G1 and G2 are at °t when the baseband signal is binary, as shown in waveforms (1) and (2). Hz
7. For 3 values, II H$1. Or “L”
Wotoru. Here, baseband signals B1 and B2 are 3
value, one of the full-wave rectified signals Gl and G2 is It H
”, then the other one will always be L#.

This is clear from the fact that in Fig. 4, for example, the orthogonal projection of signal point A onto the Therefore, when the baseband signals B1 and B2 are binary, the exclusive OR output (■) of the Sancilling output H! and H2 of the full-wave rectified signals G1 and G2 is II L''
', when it is 3 values, it becomes "H" (13). Therefore, if you take the exclusive OR between adjacent bits of the exclusive OR crab, it will always be "It H".
. As a result, the reset signal R always becomes H# at the time of erroneous synchronization.

Table 1 Note that in the above embodiment, a switch whose opening/closing is controlled by a reset signal is installed on the output side of the 9-phase error detection circuit as a means for removing erroneous synchronization by a reset signal, but as another method, For example, it goes without saying that a method of cutting off the input to the phase error detection circuit or a method of cutting off the clock signal for sampling if the two-phase error detection circuit uses digital processing can be used.

In addition, although the above embodiment has been described as an example in which a four-phase phase modulated wave signal is demodulated as an input signal, it is obvious that it can be applied to other multiphase phase modulation methods or multilevel quadrature amplitude modulation methods. be. For example, for an 8-phase phase modulation method, in the circuit shown in FIG.
A pace/4-nd demodulated output can be obtained by applying a phase modulated wave and signal processing the outputs of the low-pass F wave generators 14 and 15, which are separated by quadrature phase detection during normal synchronization. The reset signal generation circuit at the time of erroneous synchronization in this case is also configured in a similar manner.

As is clear from the above description, according to the present invention, the eye-turn of the Tahe spanned signal wave obtained by synchronously detecting a multiphase phase modulation input or a multilevel quadrature amplitude modulation input using a phase detector is detected. .

By determining the correlation between adjacent time slots, it is possible to cancel the different frequency pseudo pull-in.

As a result, the normal synchronization pull-in range can be expanded, and a great effect can be obtained to improve the reliability of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a conventional demodulator, FIG. 2 is a graph for explaining the synchronization pull-in operation in which a different frequency pseudo pull-in phenomenon exists in the conventional example of FIG. 1, and FIG. a) and (b) are time charts showing baseband signal waveforms during normal synchronization and incorrect synchronization, respectively, in the conventional example shown in FIG. A coordinate diagram for explaining vector values of signal points during synchronization, FIG. 5 is a block diagram showing the configuration of an embodiment according to the present invention, and FIG. 6 explains a synchronization pull-in operation in the embodiment of FIG. 5. The graphs of FIGS. 7(a) and Φ) are time charts for explaining the operations during normal synchronization and incorrect synchronization, respectively, in the embodiment of FIG. 5. In the figure, 11.12 is a phase detector, 13 is a 90 degree phase shifter, 14, 1'5, 17, 29 are low-pass P wave generators, 16 is a phase error detection circuit, 18 is a voltage controlled oscillator,
19 is a switch, 21.22 is a full wave rectifier. 23 to 26 are Frizzo flop circuits, and 27 and 28 are exclusive OR circuits. (17) Figure 1 Figure 2 f well fy f, + (f fs

Claims (1)

[Claims] 1. First and second phase detectors that receive an input signal and perform synchronous detection using mutually orthogonal regenerated carrier waves, and outputs from these first and second phase detectors, respectively. first and second low-pass filters that receive the signal and remove unnecessary high-frequency components, respectively; and first and second pace filters obtained from the first and second low-pass filters, respectively. a phase error detection circuit that receives a digital signal and detects a phase error between the carrier wave of the input signal and the regenerated carrier wave; The third filter removes the high-frequency components of
A regenerated carrier wave is generated under the control of the output signal of the low-pass F wave filter and the third low-pass filter, and the output thereof is directly applied to one of the two phase detectors (1). , and a voltage controlled oscillator which is applied via a 90 degree phase shifter on the other hand. first and second sample circuits that sample the respective outputs obtained from the first and second low-pass filters; and detecting the correlation between the respective outputs of the first and second sample circuits; , and a circuit for determining whether the synchronization is in a normal pull-in state or a pseudo pull-in state,
Furthermore, a circuit for cutting off the output of the phase error detection circuit is added inside the phase error detection circuit or on its input side (or output side), and when the judgment circuit determines a pseudo-synchronization pull-in state, A demodulator characterized in that an output cutoff circuit of the phase error detection circuit is controlled to be cut off based on the output of the determination circuit.