JPS5831591A - Buried semiconductor laser - Google Patents
Buried semiconductor laserInfo
- Publication number
- JPS5831591A JPS5831591A JP12905581A JP12905581A JPS5831591A JP S5831591 A JPS5831591 A JP S5831591A JP 12905581 A JP12905581 A JP 12905581A JP 12905581 A JP12905581 A JP 12905581A JP S5831591 A JPS5831591 A JP S5831591A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- buried
- current
- type
- semiconductor laser
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
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- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、埋め込み構造半導体レーザの改良に関する。[Detailed description of the invention] The present invention relates to improvements in buried structure semiconductor lasers.
第１図に、従来における１ｎＧａＡａＰ／Ｉｎ）’埋め
込み構造中導体レーザを示す。第２図に仁のタイプの半
導体レーザの電訛−光出力特性の一例ｔ−不す０この様
なレーザにおいてに、活性層３に流れる＠ｇｉｅに比べ
て、リーク電＆：ｌｔ、６小さくすることが、低しきい
値及び高効率￥ｒ央現する上で重要となっている。活性
層３０両脇を流れるリーク電流１ｔ、ｉｊ、 上側ク
ラッド層（ｐ−１ｎ）’）４． ｍめ込み４（ｎ−１
ｎＰ）？、電流プＢｙり）−（Ｐ’−１［ＩＰ）６１下
備ｌ ２ ｙ ｋ”１−（ｎ−ＩＥＩＰ）２からなるｐ
ｎｐｎ構造によって極めて小さく出来るΩしかしｐｎｐ
ｎ構造がターンオンすると過大なリーク電υｉｌＬが流
れるため、 ｐｎｐｎ＃造のターンオン電圧會＾くする
ことが必賛である。このターンオン電圧ケ高くすること
は各層のキャリア濃度ｔ−過当にすることにより容易で
ある。しかし第１図のＩｏで示す様なゲート電流が流れ
るとナイリスタ作用により、ターンオン電圧が極端に低
下する。この様なゲート電流ＩＧｔ焦（すことは活性層
３と電流ブロック層６の上の境界とを合わせて、電流通
路ｔなくすことによって可能である０しかし実際に、ゲ
ート電流ＩＱの電流通路のない構造を再現性良く製作す
ることは製造技術上はとんど不可能である。FIG. 1 shows a conventional 1nGaAaP/In)' buried structure conductor laser. Figure 2 shows an example of the voltage-light output characteristics of a jin type semiconductor laser. It is important to achieve low threshold and high efficiency. Leakage current 1t, ij flowing on both sides of the active layer 30, upper cladding layer (p-1n)')4. m inset 4 (n-1
nP)? , current pressure) - (P'-1[IP)61
Ω, which can be made extremely small by the npn structure, but pnp
When the n structure turns on, an excessive leakage current υilL flows, so it is essential to increase the turn-on voltage of the pnpn structure. This turn-on voltage can be easily increased by making the carrier concentration t of each layer excessive. However, when a gate current as shown by Io in FIG. 1 flows, the turn-on voltage is extremely reduced due to the Nyristor action. Such focusing of the gate current IGt is possible by aligning the upper boundary of the active layer 3 and the current blocking layer 6, eliminating the current path t. Manufacturing the structure with good reproducibility is almost impossible in terms of manufacturing technology.
すなわち、実際の半導体レーザでは、ゲート電流Ｌａが
多かれ少なかれ流れるため、半導体レーザの注入電流を
増すにつれ、ゲート電［１ｏが増大しｈ ｐ”９ｎ構造
のターンオン電圧が低下する。そして、半導体レーザに
加わる印加電圧がター／オン電圧になったとき、 ｐｎ
ｐｎ構造がターンオンして、過大なリーグ電流ｌＬが流
れるため、ｌ＠２図に示す様に光出力が激減する。その
ため、第２図に示す様な素子では、ｓｋ高出方が３０”
Ｏで約２０ｍＷ根度とはかった◎又、高温になるほど、
小さい注入電流でターンオンするため、高温の出方が特
に低下する。この様に、従来の埋め込み構造半導体レー
ザではｈ ｐ”ＰＩ”構造にゲート電ＩＬＬａが流れる
とター／オン電圧が低下して、低い注入電高温での出力
が特に低下するという欠点を有していた。That is, in an actual semiconductor laser, the gate current La flows more or less, so as the injection current of the semiconductor laser increases, the gate voltage [1o increases and the turn-on voltage of the h p''9n structure decreases. When the applied voltage becomes the turn/on voltage, pn
Since the pn structure turns on and an excessive league current LL flows, the optical output sharply decreases as shown in Figure 1@2. Therefore, in the device shown in Figure 2, the sk high output is 30"
The power level was about 20mW at O◎Also, the higher the temperature,
Since it is turned on with a small injection current, the high temperature is particularly reduced. In this way, conventional buried structure semiconductor lasers have the disadvantage that when the gate current ILLa flows through the hp"PI" structure, the turn-on voltage decreases, and the output particularly at high temperatures with low injection current decreases. Ta.
本発明の目的は、ゲート電流Ｉｏが流れてもｐｎｐｎ
構造のターンオン電圧が低下せず、Ｉｋ尚比出力高くか
つ高温時でも高出力の埋め込み構造半導体レーザを提供
する事にある０
本発明によれば給１導電型の半導体基板と、この半導体
基板の上に形成されかつ電流ブロック層の禁制帯幅に比
して小さな＠？ＩＪ帝−を有する第１導電型の第１の半
４坏層と、この第１の半導体１−の上に形成されたスト
ライプ状の第１４ｍ！ｃ型の下側クラッド層と、このＴ
ｍクラッドノーの上に形成されたストライプ状の活性層
と、この活性層の土に形成されたストライプ状の第１２
！＄電型と反対の第２導電型を有する上−クラッド層と
、第ｌの午導体層の上でかつ活性層の両側に形成された
第２導電戚の電波ブロック層と、こ０＠訛ズブロックの
上でかつ上側クラッド層の両側に形成された第１導電型
の埋め込みノーとを具備したことを特徴とする埋め込み
構造半導体レーザが得られる。The object of the present invention is that even if the gate current Io flows, pnpn
It is an object of the present invention to provide a buried structure semiconductor laser that does not reduce the turn-on voltage of the structure, has a high Ik output, and has a high output even at high temperatures. Formed above and smaller than the forbidden band width of the current blocking layer @? A first semi-conductor layer of the first conductivity type having an IJ characteristic and a striped 14th layer formed on the first semiconductor layer 1-. c type lower cladding layer and this T
A striped active layer formed on top of m-cradno and a striped active layer formed on the soil of this active layer.
! an upper cladding layer having a second conductivity type opposite to the $ conductivity type; a radio wave blocking layer of a second conductivity type formed on the lth conductor layer and on both sides of the active layer; There is obtained a buried structure semiconductor laser characterized in that it has a first conductivity type buried node formed above the block and on both sides of the upper cladding layer.
以下図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.
第３図は１本発明の一実施例の断面図である。FIG. 3 is a sectional view of one embodiment of the present invention.
図中、３０はｎ−１ｎｐ基板ｓ３１はバッファ一層（ｎ
−１ｎｐ、厚さ〜５μｍ）、 ３２はｎ−ＩｎＧａＡｓ
Ｐ層（厚さ〜Ｑ、５ＪＩｎ、λ〜１．２５＃ｍ）、３３
は下側クラッド層（ｎ−Ｉｎ）’、厚さ〜０３ａｍ）、
３４は活性層（ノンドープＩＩＩＧＪＩＡＩＰ厚さ〜０
．２Ａｍ）、３５ハ上側り２ラド層（厚さ〜２．．５４
ｍ、ｐ−１ｎ）’）、３６は’Ｆ’ｒｔプ層（？−Ｉｎ
ＧａＡｓＰ層、厚さ〜Ｑ、７７＊ｍ）。In the figure, 30 is an n-1np substrate s31 is a buffer layer (n
-1np, thickness ~5μm), 32 is n-InGaAs
P layer (thickness ~Q, 5JIn, λ ~ 1.25#m), 33
is the lower cladding layer (n-In)', thickness ~03am),
34 is an active layer (non-doped IIIGJIAIP thickness ~ 0
．． 2 Am), 35mm upper 2 rad layer (thickness ~ 2..54
m, p-1n)'), 36 is 'F'rt layer (?-In
GaAsP layer, thickness ~Q, 77*m).
３７は電流プａｙり層（ｐ、−１＋ｎＰ、厚さ〜０．５
μｍ）、３８は埋め込み層（ｎ−１ｎＰ、厚さ〜２．５
ａｍ）、３９はｎ−Ｉ鳳Ｇ５１Ａｓ）”層（厚さ〜１
＃ ｍ ）ｓ ４０はＺｎ拡散層、４１は８ｉ偽属、４
２はｐ電極、４３扛Ω電極である０本実施例においては
、上側クラッド層３５．埋め込み層３８．電流プロ、り
層３７１ｎ−１ａＱａＡｓＰ層３２．バッファ一層３１
からなるｐｕｐａ ｍ造でもれ電流ＩＬｔ−阻止してい
る０従米ｏｐｎｐｎ構造と異なｈ本実施例のｐｎｐｎ構
造Ｔｉｊ、ｎ−ＩｎＧａＡｓＰ層３２の存在が特徴であ
る〇ｎ−１ｎＧａＡｓＰノー３２があるたメ、 上ｆｆ
１ｐｎｐｎ構造の１部分であるｎｐｎ ） ？ンジスタ
４４の利得を非常に小さくすることが出来る０すなわち
、ｎ−ＩｎＧａＡｓＰ層３２がベースに相当する電流ブ
ロック層（アーＩｎ）’）３７よシも狭い娯１１ＩＪ４
Ｉ幅を有するため、エミッタ注入効率が非常ｔ／Ｃ小さ
くなり、そのため利得は非常に小さくなる。37 is a current pull layer (p, -1+nP, thickness ~0.5
μm), 38 is a buried layer (n-1nP, thickness ~2.5
am), 39 is an n-I Otori G51As)'' layer (thickness ~ 1
#m)s 40 is Zn diffusion layer, 41 is 8i pseudogenus, 4
In this embodiment, upper cladding layer 35.2 is a p-electrode and 43Ω is an electrode. Buried layer 38. Current professional layer 371n-1aQaAsP layer 32. Buffer layer 31
The pnpn structure of this embodiment is different from the pnpn structure in which the leakage current ILt is blocked by the pupa m structure, which is characterized by the presence of the n-InGaAsP layer 32. , upper ff
npn) which is a part of the 1pnpn structure? The gain of the transistor 44 can be made very small. In other words, the n-InGaAsP layer 32 is a current blocking layer (In)') 37 which corresponds to the base.
Because of the I width, the emitter injection efficiency becomes very small t/C, and therefore the gain becomes very small.
この様に上記ｎｐｎ ）ツンジスタ４４の利得が非常に
小さいため、図中のゲート電流ＩＧが流れても本実施例
のＰｉｌｐｌｌ ＋ｔ４造のターンオン電圧は低下しな
い。従がって、各層のキャリアａ度を適当にしてターン
オン′砿圧ｌ：３〜４ｖ程度に高くすることにより実用
的な注入電ｇｉａ域でｐｎｐｎ ｍ造がターンオンせず
に、ここを流れるリーク電流ＬＬ’ｔｔｔとんど零にす
ることが出来る。As described above, since the gain of the npn transistor 44 is very small, the turn-on voltage of the Pilpll +t4 structure of this embodiment does not decrease even if the gate current IG shown in the figure flows. Therefore, by adjusting the carrier a degree of each layer and increasing the turn-on pressure l to about 3 to 4 V, it is possible to prevent the pnpn m structure from turning on in the practical injection voltage range and to prevent leakage flowing through it. The current LL'ttt can be reduced to almost zero.
この様に本実施例ではｐｎｐｎ ｍ造を流れる態動電流
がはとんど無いため高出力、及び高温動作が可能な埋め
込み構造半導体レーザが得られる。As described above, in this embodiment, since there is almost no active current flowing through the pnpn structure, a buried structure semiconductor laser capable of high output and high temperature operation is obtained.
本実施例の埋め込み構造半導体レーザの＃ｉ造力法ｔＳ
単に述べる。まずｎ−１０Ｐ基板３ｏ上にバラフ７−４
４３１ｍ ｎ−ＩｎＧａＡｓＰ層３２． 下ｎクラッ
ド層３３．活性層３４．上側クラッド層３５゜キャップ
層３６を液相エピタキシャル技術等を用いて形成する。#i force forming method tS of the buried structure semiconductor laser of this example
Simply state. First, on the n-10P board 3o, put the baraf 7-4
431m n-InGaAsP layer 32. Lower n-cladding layer 33. Active layer 34. An upper cladding layer 35° cap layer 36 is formed using liquid phase epitaxial technology or the like.
次に８１０！膜等をマスクとしたホトエツチングにより
キャップ層３６上側クラッド層３５．活性層３４．下側
り２ラド層３３ｔ−ストライプ化する。その後再び液相
エピタキシャル技術等を用いて電流ブロック層３７．ａ
め込み層３８ｎ−１ｎＧａＡｓＰＪｄ３９ ｔ−形成
する。成長の際、キャップ１１３６の上にＳｉへ躾を形
成しストライプの両側にのみ成長を行なわせる。その後
、ＳＳＯ！膜４１ｉｅＶＤ法及びホトエツチング法を用
いて形成し、Ｚｎ拡散層４０、ｐ電極４２．ｎｕｌｌ極
４３全４３する。Next is 810! The cap layer 36 and the upper cladding layer 35 are etched by photoetching using a film or the like as a mask. Active layer 34. The lower two rad layers 33t are made into stripes. Thereafter, a current blocking layer 37 is formed again using liquid phase epitaxial technology or the like. a
An embedded layer 38n-1nGaAsPJd39t- is formed. During growth, a groove is formed in the Si on the cap 1136 to allow growth to occur only on both sides of the stripe. After that, SSO! The film 41 is formed using a VD method and a photoetching method, and includes a Zn diffusion layer 40, a p-electrode 42. Null pole 43 all 43.
最後に本発明が有する特徴を要約すると、リーク電流の
極めて小さな、高出力及び高温動作が可能な埋め込み構
造半導体レーザが得られることである。Finally, to summarize the features of the present invention, it is possible to obtain a buried structure semiconductor laser with extremely small leakage current and capable of high output and high temperature operation.
第１図は従来のＩｎＧａＡｓＰ／ＩｎＰ埋め込み構造半
導体レーザの断面図である。第２図は従来のＩｎＧａＡ
ｓ）’／Ｉｎ）’ｇめ込み構造牛導ＫＬ／−ザノ電流−
光出力特性の一例である０第３図は本発明の一実施例の
ＩｎＧａＡｓＰ／ＩｎＰ埋め込み構造半導体レーザの断
面図である。
図中、ｌ・・・・・・ａ−１ｎＰ基板、２・・・・・・
下側クラッド層、３・・・・・・油性層、４・・・・・
・上側クラッド層、５はキャップ層、６・−・・・・電
流ブロックノー、７・・・・・・埋め込み膚、８・・・
−・・ｎ−ＩｎＧａＡｓＰ層、９・・・・・・Ｚ ｎ拡
散層、１０・−・・・・Ｓｉｎ、膜、１１・・・・−・
ｐ側電極、１２−−−−− Ｅｌ ＠電極、 ３０−
ｎ−Ｉｎ）’ ｊｌｉｉ板、 ３１・・・・・・バッフ
ァ一層、３２ ・・・・＝ｎ−ＩｎＧａＡｍ）’層。
３３・・・・・・下側クラッド層、３４・−・・・・活
性層、３５・・・・−・上側り２ラド層、３６・・・・
・・キャップ層、３７・・・・・・電流ブロック層、３
８・・・・・・埋め込み層、３９−−−−−−ｎ−１ｎ
ＧａＡｍ）’層、 ４０−・−−−Ｚｎｎ拡散層４１・
・・−８ｉ偽膜、４２・・・・・・ｐ電極、４３・・・
・・−ｎ電極、２
第１図
０ １００ ２００電
流 （−△）
姶２図FIG. 1 is a cross-sectional view of a conventional InGaAsP/InP buried structure semiconductor laser. Figure 2 shows conventional InGaA
s)'/In)'g inset structure cow lead KL/-Zano current-
FIG. 3, which is an example of optical output characteristics, is a cross-sectional view of an InGaAsP/InP buried structure semiconductor laser according to an embodiment of the present invention. In the figure, l...a-1nP substrate, 2...
Lower cladding layer, 3...Oil layer, 4...
- Upper cladding layer, 5 is a cap layer, 6... current block no, 7... embedded skin, 8...
-...n-InGaAsP layer, 9...Z n diffusion layer, 10...Sin, film, 11...
p-side electrode, 12----- El @electrode, 30-
n-In)'jlii plate, 31... one buffer layer, 32...=n-InGaAm)' layer. 33... lower cladding layer, 34... active layer, 35... upper 2 rad layer, 36...
... Cap layer, 37 ... Current blocking layer, 3
8... Buried layer, 39---n-1n
GaAm)' layer, 40-----Znn diffusion layer 41-
...-8i pseudomembrane, 42...p electrode, 43...
...-n electrode, 2 Fig. 1 0 100 200 current (-△) Fig. 2
Claims (1)
されかつ電流ブロック層の禁制帯幅に比して小さな禁制
４１Ｉ幅を有する第１導電瀝の第１０牛導体層と、この
第１の半導体層の上に形成されたストライプ状の第１導
電盛の下側クラッド層と、この下側クラッド層の上に形
成されたストライプ状の活性層と、この活性層の上に形
成されたストライプ状Ｏ第１導電型と反対の第２導電型
を有する土間クラッド層と、前記＃１１の半導体層の上
でかつ前記活性層の両側に形成された第２導電城の電流
ブロック層と、この電流ブロック層の上でかつ前記上−
クラッド層の両側圧形成された＠１導電型の埋め込み層
とをＡｍしたことを特徴とする埋め込み＃遺半導体し−
ザ〇a semiconductor substrate of a first conductivity type; a tenth conductor layer of a first conductivity type formed on the semiconductor substrate and having a forbidden band width smaller than the forbidden band width of the current blocking layer; a striped lower cladding layer of the first conductive layer formed on the semiconductor layer; a striped active layer formed on the lower cladding layer; and a striped active layer formed on the active layer. a striped O dirt floor cladding layer having a second conductivity type opposite to the first conductivity type; and a current blocking layer of a second conductive castle formed on the #11 semiconductor layer and on both sides of the active layer; above this current blocking layer and above-
A buried #1 conductivity type buried layer formed on both sides of a cladding layer.
The〇
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12905581A JPS5831591A (en) | 1981-08-18 | 1981-08-18 | Buried semiconductor laser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12905581A JPS5831591A (en) | 1981-08-18 | 1981-08-18 | Buried semiconductor laser |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5831591A true JPS5831591A (en) | 1983-02-24 |
| JPS6243356B2 JPS6243356B2 (en) | 1987-09-12 |
Family
ID=14999966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12905581A Granted JPS5831591A (en) | 1981-08-18 | 1981-08-18 | Buried semiconductor laser |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5831591A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5842283A (en) * | 1981-09-04 | 1983-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of buried type semiconductor laser |
| JPS59112671A (en) * | 1982-12-20 | 1984-06-29 | Kokusai Denshin Denwa Co Ltd <Kdd> | Semiconductor laser |
| JPS6261386A (en) * | 1985-09-11 | 1987-03-18 | Sharp Corp | Semiconductor laser element |
-
1981
- 1981-08-18 JP JP12905581A patent/JPS5831591A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5842283A (en) * | 1981-09-04 | 1983-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of buried type semiconductor laser |
| JPS59112671A (en) * | 1982-12-20 | 1984-06-29 | Kokusai Denshin Denwa Co Ltd <Kdd> | Semiconductor laser |
| JPS6261386A (en) * | 1985-09-11 | 1987-03-18 | Sharp Corp | Semiconductor laser element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6243356B2 (en) | 1987-09-12 |
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