JPS5830166A - Manufacture of semiconductor light receiving element - Google Patents

Abstract

PURPOSE:To avoid meltback, when an avalanche photodiode is prepared by a liquid phase epitaxial growth method, by providing a concave part in the substrate, laminating a multiplying layer, a light absorbing layer, and a contact layer on the entire surface including said concave part, and providing a light inputting port reaching the multiplying layer from the substrate side. CONSTITUTION:The concave part is formed at the central part of the surface of the P<+> type InP substrate 11 by etching, and a P<+> type InGaAsP etching protecting layer 12 is epitaxially grown in the liquid phase on the entire surface including the concave part. Then the N type InP multiplying layer 13, the N type InGaAsP light absorbing layer 14, and the N<+> type InGaAs contact layer 15 are epitaxially grown in the liquid phase simultaneously on the layer 12. Thereafter an electrode 18 is deposited on the layer 15. The light inputting port 17 is provided at the central part of the substrate 11 by etching. A P<+> type region 19 comprising the layer 12 is exposed in the port. An electrode 16 is deposited on the part of the substrate 11 which is left at the peripheral region. In this method, the sequence of forming the growing layers is reversed with respect to the ordinary method. Thus the generation of the meltback is avoided, and a part of the multiplying layer is used as a guard ring.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a compound semiconductor light-receiving device, particularly an avalanche photodiode.

An avalanche e-photodiode (hereinafter referred to as APD) using a 1-V group compound semiconductor can set its maximum sensitivity wavelength within a wide wavelength range of about 1 μm to 7 μIR by changing its crystal group g. can. For example, In0.79 GaO grown by liquid phase epitaxial (hereinafter referred to as LPE) on an InP substrate,
A maximum sensitivity wavelength of 1.2μ was obtained in the quaternary semiconductor APD of 21AsO, 52Po, 48, and InO, 53Ga0.47As grown by LPE on an InP substrate.
The maximum sensitivity wavelength in the ternary semiconductor APD is 1.64 μm.
Formation KF of compound semiconductor structure with 0APD obtained
! , for example, an InP layer as a buffer layer on an InP substrate,
InGaAsP layer as a light absorption layer and I as a multiplication layer
A conventional method is to perform vapor phase diffusion into the multiplication layer after nPJltMI-order LPE growth to form a pn junction.

However, a problem arises when an InP layer is grown from an In solution onto an InGaAsP quaternary growth layer by the LPE method. In other words, equilibrium between the solid phase and the liquid phase cannot be established between the InGaAsP quaternary mixed crystal and the In solution containing only P. The first crystal composition example or the wavelength is 1.
In0.70Gm0.30As corresponding to about 3μ groove
In the case of a quaternary composition containing about 0.65 Po, 35% P, by keeping the saturation level of the solution at a growth temperature of 650°C, rnPf, 1l contact L can be formed on the quaternary mixed crystal.
However, in the case of a crystal composition corresponding to a longer wavelength range, for example, the second crystal composition example, the amount of P is small and the non-equilibrium phase with respect to fi1mK containing P is small. In this case, meltback of the quaternary layer occurs], making it difficult to form a front layer structure using the InP layer as a multiplication layer. OA into the In solution at a temperature of about ℃,
A method of reducing the solubility of AI, or adding another quaternary layer (wavelength 1.2 to 1.3 μm K) as a buffer layer on top of the quaternary light absorption layer (composition corresponding to the wavelength 1.4 to 1.6 μmK).
InP LP after forming a thin spread of pc (corresponding composition)
E-growth methods have been proposed, but the manufacturing methods for all of them are complicated.Also, in APDs, local sag multiplication around the light receiving area is prevented and uniform multiplication is performed. A guard ring is required for this purpose.

InP layer InGaAsP A with hetep junction structure
A method has been proposed as a guard ring structure for a PD, the cross-sectional view of which is shown in FIG. That is, K on the n-1nP substrate 1
n-InGaAsP layer 2 and n-1nPJ*3
He then sequentially grew the P-diffusion regions 4 and 5 by two P-diffusions to form the Lpn junction and n
- The thickness of the n-InP layer between the InGaAsP layer is made thinner in the peripheral part compared to the central part, and the withstand voltage of the surrounding area is reduced by comparing with the withstand voltage of the multiplication layer of the central light-receiving part. It is raised to form a guard ring.

This structure is a method that is implemented in pull-APDs, etc., but in compound semiconductor APDKs using Peter junctions, two P-APDs are used.
- Diffusion is difficult to achieve with good control.

Furthermore, as a guard ring structure different from the above method, a method whose cross-sectional views are shown in FIGS. 2(1) to (e) has been reported.
P substrate 6 K n -InGaAsP layer 7, n--In
After the P layer 8 and the n-InP layer 9 having a higher carrier concentration are sequentially grown by LPE, the n-IfIP layer 9 is etched by Mena IIK as shown in FIG. 2(b)K, and then, as shown in FIG. By forming the P"-1nF region 10 indicated by K by vapor phase diffusion of ca, the n-I!IP layer 9 is formed.
In this method, however, a guard ring part is formed around the multiplier layer O and the n-InP layer 8). In this case, isotropic etching and precise control of the MenaO depth are required, and also for the Cd ion diffusion shown in Section 21iI←), two etchings with different carrier concentrations are required.
It is necessary to simultaneously diffuse the KCd ions in the InP layer and to precisely control the diffusion depth of both the light receiving part and the guard ring part (Be). In general, it is not easy to meet these requirements, and this results in local electric field concentration at the outer periphery of the mena, making industrial implementation difficult.
1. Since the carrier concentration of the loss multiplier layer is slightly high at 8×10"/a11, there is a drawback that 1. low noise can be achieved. The object of the present invention is to obtain an LPE growth method in which the multiplication layer has a shape in which a guard ring is formed.

The present invention consists of 1. The order of formation of the LPE growth layer is reversed from the conventional method, and a light absorption layer is formed on the multiplication layer.Finally, a contact layer with a large degree of freedom in crystal composition is formed, and then a light entrance hole is opened in the substrate. The present invention is characterized in that a concave portion is provided in advance in the substrate in order to make the thickness of the central portion of the multiplication layer serving as the light-receiving portion smaller than the thickness of the surrounding portion by LPE.

Furthermore, by including a high concentration of impurities that provide conductivity opposite to that of the multiplication layer in the substrate directly below the multiplication layer or in the LPE growth layer, a l> pn junction is formed due to the temperature increase in the LPE process. .

The present invention will be explained in detail by way of examples using FIGS. 3(a) and 3(b).

FIG. 3(a) is a cross-sectional view showing an example in which an LPE growth layer is formed. The P''-InP substrate 11 is coated with HtSO4 (9) using silicon dioxide (Sigh) as a mask.
7chi) :H*0t(31qb) :HtO=90:5
:Approximately 150 μm in diameter and approximately 2 in depth using 5 as etching solution
μmOr! ! J@ is provided in advance.

A protective layer 12 and a multiplication layer 13 are fabricated on this substrate.
, when the light absorption layer 44 and the contact layer 15 are sequentially grown by LPE as described later, the degree of supercooling is equivalently increased in the concave part compared to the flat layer 11 around the surface, so that the growth layer is grown as shown in Fig. 1. The thickness is increasing.

The growth starting position of each LPE growth layer 0 is 650'C1 cooling rate is 0.1°C/-. Nine melts 1 used for forming each layer
1! h, P''-InGaAsP as etching protection layer
Layer 12 #iIn: InAs: GaAs: In
P:Zn==1178.2Mg: 12311P:
3.11F: 0211jF, n −1n as a multiplication layer
The P layer 13 is In:I! IP = 11: l0J
III, the n-InGaAsP layer 14 serving as a light absorption layer has an In:IILAs:GaAs:InP base 1
180.1 tick 26.811F ¥1.8 n-InGaAs layer 15 as a dust layer B In: InA
s: GaAs = 1165.9 mites 351 ki.

Each layer tag length time is 10 seconds, 8 minutes, 3 minutes and 50 minutes.
The jI thickness at the flat section was 0.2μfi, IJm thickness was 2μ, and 205m. In this example, the thickness of the n-InP layer 13 serving as a multiplication layer in the center of the recessed portion is approximately 1.5 μm, and the thickness is approximately 0.5 μm compared to that in the flat portion.
It grows to a μm thickness. Next, on the opposite side of the LPE grown layer of the P+-InP substrate 11, around a circle with a diameter of about 200 m facing the LPE grown layer, a layer of gold, zinc, lead, etc. is applied to a thickness of about 300 to 400 mm. electrode 1
6, using a resist mask with a slightly smaller opening (than the opening of the electrode 16), the P+-InP substrate 11 is coated with HBr (47%) : HF (50'1G) =
P''-InGaAgP etched pupil retaining layer 12tHF (50%):HNOm (61%) with a 10:1 etching solution.
)=1:1 etching solution to form a light entrance hole 17.

Next, an electrode 18 is formed on the entire surface of the contact layer 15 using gold-tin or the like to a thickness of about 300 to 400 mm. Third
Figure (b) shows a cross-sectional view of the APD of this embodiment described above.

In order to form a P+ region in the multiplication layer 12, there is generally a method of performing ion implantation and annealing after the above-mentioned pre-injection port 17 type, but in this embodiment, the etching protection layer 12t is Znt-doped. Since it is formed from a P''-InGaAsP layer, Zn ions diffuse into the multiplication layer during the LPE process, and a P+ region 19 is therefore formed, and a pH junction is already formed, so a P+ region is formed anew. This is not necessary; furthermore, the shape of the multiplication layer 12 is such that the central portion, which is the light-receiving portion, is formed to be thicker than the peripheral portion as described above], while the thickness of this P+ region 19 is - Therefore, the distance between the % pH junction and the light absorption layer is shorter at the periphery than at the center, forming a guard ring.

In this embodiment, the line light absorption layer 14 has a maximum sensitivity wavelength of 1.
5stfi In0.58 Gm0.42 As0
．． If you try to grow a knee multiplier layer on the light absorbing layer 14 using 9 Po, 1 as in the conventional method, the above-mentioned 9 melt grasshopper problem will occur, but the present invention 15!
This problem is solved by reversing the order of LPIC growth in 0. The contact layer IB is grown by KLPE on the optical absorption layer 14! l''-4mGmAm, the problem of simmert back does not occur.The above characteristics are that the light absorption layer 14 is made of ternary In0.5 containing no P and has a maximum sensitivity wavelength of 1.64μm.
3 It also holds true even if it is a Ga0.47 As layer.

The method of the above embodiment can be applied as is even in the case of a P-rich crystal composition in which the maximum sensitivity wavelength of the light absorption layer 14 is less than 1.3 μfn, but if the contact layer 15 is further
- It is also possible to construct it by InP.

Next, in the embodiment described above, the etching protection layer 12 was interposed between the substrate 11 and the multiplication layer 13. - Layer 12 is not absolutely necessary. In the case where this etching protection layer 12 is not interposed, if a material containing a high degree of impurity that has conductivity opposite to that of the multiplication layer 13 is used as the substrate 11, the above-mentioned embodiments regarding the formation of the pH junction can be used. The same effect can be obtained.

Furthermore, the above embodiment is an InP/InGaAsP-based APD.
However, other compound semiconductors such as GaAs/AlGa
As +Garb /GaAJAa8b Misaki Nyoru AP
The same effect can be obtained by applying the present invention to D as well.

As explained above, in the present invention, a concave portion is formed for the compound semiconductors A and D, and a multiplier layer, a light absorption layer, and a contact layer tube are sequentially formed on the nine substrate surfaces, and then a light entrance that reaches the multiplier layer from the substrate side. By providing L, melt batter can be avoided and the multiplication layer can be shaped to form a guard ring.
It provides a PE growth barrier, and furthermore, it is possible to form a p-n junction in the LPE process by adding a high concentration of impurity to the LPE growth layer that gives conductivity opposite to that of the multiplication layer. 0, which has the characteristics of being completed in the middle and has great effects on the manufacturing of compound semiconductor APDs.

[Brief explanation of the drawing]

Figures 1 and 2) to (C)#i are cross-sectional views showing the prior art, and Figures 3) and 3) are cross-sectional views showing practical examples of the present invention. In the figure, 1 is an n-I-substrate, 2 is an n-InGaA
sP layer, 3tfn-ItLP layer, 4tiP diffusion region, 5
is a P diffusion region, 6 is an n+-InP substrate, 7 un −
InGaAsP layer, 8ha-1rlP layer, 9 is n-1n
P layer, 10 P"-IIP area, 11 substrate, 12 etching protection layer, 13 multiplication layer, 14 light absorption layer, 15
is the contact layer, 16 is the electrode, 17 is the light entrance, 18 is the electrode, and 19 is the P area. Spear figure (b)

Claims (1)

[Claims] In a method for manufacturing a semiconductor light-receiving element, in which a light absorption layer and a multiplication layer made of a compound semiconductor are formed on a ψ substrate by an Ebitaki V-Yal growth method, the multiplication layer and the multiplication layer are formed on a surface of the substrate provided with a recessed portion. A method of manufacturing a semiconductor light-receiving element, comprising sequentially forming a light absorption layer and a contact layer, and then selectively providing an opening reaching the multiplication layer on the substrate side.