JP2996943B2 - Semiconductor light receiving device and method of manufacturing the same - Google Patents

Semiconductor light receiving device and method of manufacturing the same

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Publication number
JP2996943B2
JP2996943B2 JP10056687A JP5668798A JP2996943B2 JP 2996943 B2 JP2996943 B2 JP 2996943B2 JP 10056687 A JP10056687 A JP 10056687A JP 5668798 A JP5668798 A JP 5668798A JP 2996943 B2 JP2996943 B2 JP 2996943B2
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JP
Japan
Prior art keywords
region
light receiving
guard ring
type
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP10056687A
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Japanese (ja)
Other versions
JPH10209486A (en
Inventor
正明 小野村
信夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Priority to JP10056687A priority Critical patent/JP2996943B2/en
Publication of JPH10209486A publication Critical patent/JPH10209486A/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体受光装置及
びその製造方法に係わり、特にガードリング構造を有す
るプレーナ型ヘテロ接合アバランシェフォトダイオード
(Avalanche PhotoDiode、以下APDと略す)等の半導
体受光装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light receiving device and a method of manufacturing the same, and more particularly, to a planar heterojunction avalanche photodiode having a guard ring structure.
(Avalanche PhotoDiode, hereinafter abbreviated as APD) and the like, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、光通信用の検出器としてフォトダ
イオードが使用されているが、その中でも受信側マージ
ンの点で内部増幅機能を有するAPDが有用である。特
に、InGaAs又はInGaAsPを光吸収層に用
い、InPを増倍層に用いたAPDは、格子整合したヘ
テロ接合が可能であり、且つ石英系光ファイバーの低損
失域である1.1〜1.6μm帯に受信感度を持つ。こ
のため、長距離大容量光通信の検出器として有望であ
り、その研究開発が盛んに進められている。
2. Description of the Related Art Conventionally, a photodiode has been used as a detector for optical communication. Among them, an APD having an internal amplification function is useful in view of a margin on a receiving side. In particular, an APD using InGaAs or InGaAsP for the light absorption layer and using InP for the multiplication layer can perform a lattice-matched heterojunction and has a low loss region of 1.1 to 1.6 μm of the quartz optical fiber. Has reception sensitivity in the band. For this reason, it is promising as a detector for long-distance and large-capacity optical communication, and research and development thereof are being actively pursued.

【0003】従来のAPD構造の一例(特開昭60−1
9876号公報)を図8に示す。n+ −InP基板81
の上にn−InPバッファ層82,n- −InGaAs
光吸収層83,n−InGaAsP中間層84,n−I
nPアバランシェ増倍層85及びn- −InP層86を
順次形成した半導体多層膜に、熱拡散或いはイオン注入
により、階段型pn接合を有するp+ 型導電領域の受光
領域87が形成され、この受光領域87の周囲に傾斜型
pn接合を有するp型導電領域の第1のガードリング領
域88が一部重なるように形成されている。
[0003] An example of a conventional APD structure (Japanese Patent Laid-Open No. Sho 60-1)
9876) is shown in FIG. n + -InP substrate 81
N-InP buffer layer 82, n -- InGaAs
Light absorption layer 83, n-InGaAsP intermediate layer 84, nI
In a semiconductor multilayer film in which an nP avalanche multiplication layer 85 and an n -InP layer 86 are sequentially formed, a light receiving region 87 of ap + type conductive region having a stepwise pn junction is formed by thermal diffusion or ion implantation. A first guard ring region 88 of a p-type conductive region having an inclined pn junction is formed around region 87 so as to partially overlap.

【0004】さらに、第1のガードリング領域88の周
囲に、第1のガードリング領域88より接合深さが浅い
第2のガードリング領域89が一部重なるように形成さ
れている。第1のガードリング領域88は階段型pn接
合のエッジブレイクを防ぐため、第2のガードリング領
域89は第1のガードリング領域88のエッジブレイク
を防ぐためのものである。なお、91は透明絶縁膜、9
2は絶縁膜、93,94は電極を示している。
Further, a second guard ring region 89 having a shallower junction depth than the first guard ring region 88 is formed around the first guard ring region 88 so as to partially overlap. The first guard ring region 88 is for preventing the edge break of the step-type pn junction, and the second guard ring region 89 is for preventing the edge break of the first guard ring region 88. Incidentally, 91 is a transparent insulating film, 9
2 indicates an insulating film, and 93 and 94 indicate electrodes.

【0005】しかしながら、この種のAPDにあっては
次のような問題があった。即ち、2つのガードリングは
形成条件が異なるため2回のイオン注入工程を必要と
し、その活性化と拡散のために高温(例えば750℃)
の熱処理工程を必要とする。また、受光部,第1及び第
2のガードリング部に対し、それぞれのpn接合位置合
わせマージンをとるため、受光部径に比べてpn接合面
積が大きくなり、接合容量や暗電流の増加を招いてい
た。
However, this type of APD has the following problems. That is, two guard rings require two ion implantation steps due to different formation conditions, and a high temperature (for example, 750 ° C.) for activation and diffusion thereof.
Requires a heat treatment step. In addition, since the pn junction alignment margin is set for each of the light receiving portion and the first and second guard ring portions, the pn junction area becomes larger than the diameter of the light receiving portion, which causes an increase in junction capacitance and dark current. I was

【0006】[0006]

【発明が解決しようとする課題】このように従来技術に
よるガードリング形成は、製造工程が複雑であるばかり
か、注入イオンの活性化のためにエピタキシャル成長温
度よりも高温に晒す必要があり半導体基板の品質劣化の
原因になる。また、ガードリング部に起因する暗電流が
受光部に起因する暗電流と共に同じ電極を通じて流れる
ため、暗電流の増大の原因になる。
As described above, the formation of the guard ring according to the prior art not only complicates the manufacturing process but also requires exposing the semiconductor substrate to a temperature higher than the epitaxial growth temperature for activating the implanted ions. It causes quality deterioration. Further, the dark current caused by the guard ring portion flows through the same electrode together with the dark current caused by the light receiving portion, which causes an increase in dark current.

【0007】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、受光部の暗電流を最小
限に抑えることができ、且つ製造工程の簡略化をはかり
得る半導体受光装置及びその製造方法を提供することに
ある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to minimize the dark current of the light receiving section and to simplify the manufacturing process. An object of the present invention is to provide an apparatus and a method of manufacturing the same.

【0008】[0008]

【課題を解決するための手段】 (構成)本発明の骨子は、ガードリング部を受光部のp
n接合の外周部分に重ねて形成するのではなく、受光部
の外周部と重ならない領域に受光部のpn接合形成と同
時に形成し、受光部及びガードリング部をそれぞれ異な
る電極に接続することにある。
Means for Solving the Problems (Constitution) The gist of the present invention is that the guard ring portion is formed by the
Instead of being formed so as to overlap with the outer periphery of the n-junction, it is formed simultaneously with the formation of the pn junction of the light-receiving unit in a region that does not overlap with the outer periphery of the light-receiving unit, and the light-receiving unit and the guard ring are connected to different electrodes. is there.

【0009】前述したように、APDは高電圧を加えて
用いるためpn接合近傍で局所ブレイクが起こり易く、
それを抑えるためにイオン注入等で緩やかなpn接合で
あるガードリングを形成する必要があった。ところが、
本発明者等の研究及び実験によれば、受光部の外周部の
重ならない領域にガードリングを形成したAPDに高電
圧を加えても局所ブレイクが起こらないことが確認され
た。
As described above, since APD is used by applying a high voltage, local break is likely to occur near the pn junction.
In order to suppress this, it is necessary to form a guard ring which is a gentle pn junction by ion implantation or the like. However,
According to studies and experiments conducted by the present inventors, it has been confirmed that a local break does not occur even when a high voltage is applied to an APD in which a guard ring is formed in a region where the outer peripheral portion of the light receiving unit does not overlap.

【0010】本発明はこのような点に着目してなされた
もので、APD等の半導体受光装置において、第1導電
型の半導体基板と、この半導体基板上に積層形成された
少なくとも光吸収層及びアバランシェ増倍層を含む第1
導電型の半導体多層膜と、この半導体多層膜上に形成さ
れた第2導電型の半導体膜と、この半導体膜に表面から
裏面に達するまで高抵抗領域又は第1導電型領域をリン
グ状に形成してなり、内側の受光領域と外側のガードリ
ング領域とを電気的に分離する分離領域とを具備し、前
記受光領域及びガードリング領域をそれぞれ異なる電極
に接続してなることを特徴とする。
The present invention has been made in view of such a point. In a semiconductor light receiving device such as an APD, a semiconductor substrate of a first conductivity type, at least a light absorption layer laminated on the semiconductor substrate, and First including avalanche multiplication layer
Conductivity type and the semiconductor multilayer film, and the semiconductor film of a second conductivity type formed on the semiconductor multilayer film, from the surface to the semiconductor film
A high resistance region or a first conductivity type region is formed in a ring shape until reaching the back surface, and includes a separation region for electrically separating an inner light receiving region and an outer guard ring region. The light receiving region and the guard ring region are connected to different electrodes, respectively.

【0011】また本発明は、上記半導体受光装置の製造
方法において、n型半導体基板上に少なくともn型光吸
収層,n型アバランシェ増倍層及び該増倍層と同種のp
型半導体層を順次成長する工程と、前記p型半導体層の
受光部となる領域とガードリング部となる領域の間に
H,D,He,Li,Be,Ne,Ar又はn型不純物
の少なくとも一つをイオン注入して、p型の受光領域と
p型のガードリング領域とを分離する工程と、前記n型
半導体基板,p型受光領域及びp型ガードリング領域の
それぞれに異なる電極を接続する工程とを含むことを特
徴とする。
The present invention also provides a method for manufacturing a semiconductor light receiving device, comprising the steps of: forming at least an n-type light absorbing layer, an n-type avalanche multiplication layer, and a p-type same as the multiplication layer on an n-type semiconductor substrate.
A step of sequentially growing a p-type semiconductor layer and at least one of H, D, He, Li, Be, Ne, Ar, or n-type impurities between a region serving as a light receiving portion and a region serving as a guard ring portion of the p-type semiconductor layer. A step of ion-implanting one to separate a p-type light receiving region and a p-type guard ring region, and connecting different electrodes to each of the n-type semiconductor substrate, the p-type light receiving region and the p-type guard ring region And a step of performing

【0012】(作用)本発明によれば、高電界がかかる
pn接合近傍で起こる局所ブレイクを防ぐために形成す
るガードリングを、従来のように受光部外周に一部を重
ねて設けるのではなく、受光部外周側の重ならない領域
に設け、受光部とガードリング部は異なる電極に接続し
て独立に電圧を印加している。このため、ガードリング
部に起因する暗電流が受光部に流れることはなく、図7
に示すように受光部に流れる暗電流を低減することがで
きる。なお、動作状態においては、独立したガードリン
グ部の電界によって受光部エッジでの横方向に延びる高
電界の発生を抑えることができ、これにより受光部の階
段型pn接合のエッジブレイクを防ぐことが可能とな
る。
(Operation) According to the present invention, a guard ring formed to prevent a local break occurring near a pn junction to which a high electric field is applied is not provided by partially overlapping the outer periphery of a light receiving portion as in the conventional case. The light receiving section and the guard ring section are connected to different electrodes to independently apply a voltage, provided in a non-overlapping area on the outer periphery of the light receiving section. For this reason, the dark current caused by the guard ring portion does not flow to the light receiving portion.
As shown in (5), the dark current flowing in the light receiving section can be reduced. In the operating state, it is possible to suppress the occurrence of a high electric field extending in the lateral direction at the edge of the light receiving portion by the electric field of the independent guard ring portion, thereby preventing the step break pn junction edge break of the light receiving portion. It becomes possible.

【0013】また、半導体結晶成長時に反対導電型半導
体層を形成しイオン注入によって受光部とガードリング
部を分離することにより、熱拡散プロセスさえ必ずしも
必要としない。従って、製造工程が簡略で、プロセスの
低温化により結晶の熱変動を最小限に抑えることが可能
で、しかも低暗電流化が可能な半導体受光装置が得られ
る。
Further, by forming the opposite conductivity type semiconductor layer during the growth of the semiconductor crystal and separating the light receiving portion and the guard ring portion by ion implantation, even a thermal diffusion process is not necessarily required. Accordingly, a semiconductor light receiving device that has a simple manufacturing process, can minimize the thermal fluctuation of the crystal due to the low temperature of the process, and can reduce the dark current can be obtained.

【0014】[0014]

【発明の実施の形態】以下、本発明の詳細を図示の実施
形態によって説明する。なお、以下の実施形態では、I
nP/InGaAsへテロ接合APDについて説明する
が、他のへテロ接合APD及びホモ接合APD等につい
ても全く同様であることは容易に理解される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. In the following embodiment, I
Although an nP / InGaAs heterojunction APD will be described, it is easily understood that the same applies to other heterojunction APDs and homojunction APDs.

【0015】(第1の実施形態)図1は、本発明の第1
の実施形態に係わるAPDの概略構造を示す断面図であ
る。
(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
It is sectional drawing which shows schematic structure of APD concerning embodiment of 1st Embodiment.

【0016】n+ −InP基板11上に、n−InPバ
ッファ層12を2μm厚に、キャリア濃度が1〜2×1
15cm-3のn−InGaAs光吸収層13を2μm厚
に、キャリア濃度が2×1016cm-3のn−InGaA
sP中間層14を0.4μm厚に、キャリア濃度が2〜
3×1016cm-3のn−InPアバランシェ増倍層15
を1μm厚に、キャリア濃度が1〜2×1015cm-3
- −InP層16を0.8μm厚に、順次エピタキシ
ャル成長により形成した後、SiO2 膜21を絶縁マス
クとして、Cdを560℃の温度で15分間熱拡散し、
所望の深さにpn接合が位置するようにp+ 型の受光領
域17及びガードリング領域18を形成した。また、受
光領域17表面の一部及びガードリング領域18の表面
に、それぞれが別電極としてとれるようにオーミック電
極22,23を形成し、さらに基板11の裏面側にオー
ミック電極24を形成した。
On an n + -InP substrate 11, an n-InP buffer layer 12 is formed to have a thickness of 2 μm and a carrier concentration of 1-2 × 1.
The n-InGaAs light absorbing layer 13 of 0 15 cm -3 is made 2 μm thick and the n-InGaAs having a carrier concentration of 2 × 10 16 cm -3.
The sP intermediate layer 14 has a thickness of 0.4 μm and a carrier concentration of 2 to
3 × 10 16 cm −3 n-InP avalanche multiplication layer 15
Is formed to a thickness of 1 μm, and an n -InP layer 16 having a carrier concentration of 1 to 2 × 10 15 cm −3 is formed to a thickness of 0.8 μm by epitaxial growth, and then Cd is deposited to 560 using the SiO 2 film 21 as an insulating mask. Heat diffusion at a temperature of ℃ for 15 minutes,
The p + -type light receiving region 17 and the guard ring region 18 were formed such that the pn junction was located at a desired depth. Ohmic electrodes 22 and 23 were formed on a part of the surface of the light receiving region 17 and on the surface of the guard ring region 18 so that they could be taken as separate electrodes, and an ohmic electrode 24 was formed on the back side of the substrate 11.

【0017】この実施形態においては、イオン注入を行
わないので活性化のための高温熱処理を必要としない。
図2に、この実施形態によるAPDに高電圧を印加した
場合の空乏層内の電気力線を示す。図2において基板と
の間に印加する電圧の絶対値は受光領域17よりガード
リング領域18の方を小さくしている。この場合、ガー
ドリング領域17に起因する電流はガードリング領域1
7上に形成された電極23に流れるので、受光領域17
の暗電流は低く抑えることができる。また、ガードリン
グ領域18によって形成される電界によって、受光領域
17のエッジで横方向に伸びる高電界を抑えることがで
き、その結果、受光領域17の階段型pn接合のエッジ
ブレイクを防ぐことができる。
In this embodiment, since no ion implantation is performed, a high-temperature heat treatment for activation is not required.
FIG. 2 shows lines of electric force in the depletion layer when a high voltage is applied to the APD according to this embodiment. In FIG. 2, the absolute value of the voltage applied to the substrate is smaller in the guard ring region 18 than in the light receiving region 17. In this case, the current caused by the guard ring region 17 is
7 flows into the electrode 23 formed on the light receiving region 17.
Can be kept low. Further, a high electric field extending in the lateral direction at the edge of the light receiving region 17 can be suppressed by the electric field formed by the guard ring region 18, and as a result, the edge break of the step-type pn junction in the light receiving region 17 can be prevented. .

【0018】かくして本実施形態によれば、受光領域1
7とガードリング領域18とを分離した構造を持つ3端
子構造APDにおいて、局所ブレイクを防ぐ効果が十分
に得られ、ガードリング領域18に起因する暗電流はガ
ードリング領域18上に形成された電極23を通じて流
れるので受光領域17上に形成された主電極21を通じ
て流れる暗電流を低く抑えることができる。しかも、製
造工程を簡略化した低温プロセスで良好な素子特性を有
する半導体受光装置を実現することができる。従って、
素子特性の優れた半導体受光装置を簡易に再現性よく実
現することができ、その有用性は絶大である。
Thus, according to the present embodiment, the light receiving region 1
In the three-terminal structure APD having the structure in which the guard ring 7 and the guard ring region 18 are separated from each other, the effect of preventing the local break is sufficiently obtained, and the dark current caused by the guard ring region 18 is reduced by the electrode formed on the guard ring region 18. 23, the dark current flowing through the main electrode 21 formed on the light receiving region 17 can be reduced. Moreover, a semiconductor light receiving device having good element characteristics can be realized by a low-temperature process with a simplified manufacturing process. Therefore,
A semiconductor light receiving device having excellent element characteristics can be easily realized with good reproducibility, and its usefulness is enormous.

【0019】(第2の実施形態)図3は、本発明の第2
の実施形態に係わるAPDの概略構造を示す断面図であ
る。なお、図1と同一部分には同一符号を付して、その
詳しい説明は省略する。
(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
It is sectional drawing which shows the schematic structure of APD which concerns on embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

【0020】この実施形態では、n+ −InP基板11
上に、各層12,〜,16を先の実施形態と同じ条件で
形成した後、図示しないSiO2 膜を絶縁マスクとして
用いてガードリングとなる領域の外周部にBeイオンを
150kVで1×1013cm-2注入し、700℃で20
分の熱処理を行うことにより、イオン注入後の活性化と
拡散を行いガードリング領域(第2のガードリング領
域)19を形成し、イオン注入のためのSiO2 膜を取
り除いた後に、新たに熱拡散のためにSiO2 膜21を
絶縁マスクとして形成し、Cdを560℃の温度で15
分間熱拡散し、所望の深さにp+ n接合が位置するよう
に受光領域17及びガードリング領域(第1のガードリ
ング領域)18を形成した。
In this embodiment, the n + -InP substrate 11
After forming each of the layers 12 to 16 under the same conditions as in the previous embodiment, Be ions are applied to the outer periphery of a region to be a guard ring at 150 kV at 1 × 10 5 using a SiO 2 film (not shown) as an insulating mask. Inject 13 cm -2 and 20 at 700 ° C
By performing heat treatment for minutes, activation and diffusion after ion implantation are performed, a guard ring region (second guard ring region) 19 is formed, and after removing the SiO 2 film for ion implantation, heat is newly added. An SiO 2 film 21 is formed as an insulating mask for diffusion, and Cd is deposited at a temperature of 560 ° C. for 15 minutes.
The light receiving region 17 and the guard ring region (first guard ring region) 18 were formed so that the p + n junction was located at a desired depth.

【0021】図3の構造は、図1のガードリング領域1
8の外周部にイオン注入を行った構造であるが、これに
よってガードリング領域18に受光領域17への印加電
圧と絶対値が同程度または僅かに高く電圧を印加できる
ようにしたものである。
The structure shown in FIG. 3 corresponds to the guard ring region 1 shown in FIG.
The structure is such that ions are implanted in the outer peripheral portion of the guard ring region 8 so that a voltage can be applied to the guard ring region 18 with a voltage approximately equal to or slightly higher than the voltage applied to the light receiving region 17.

【0022】図4に、第2の実施形態によるAPDに高
電圧を印加した場合の電気力線を示す。図4において基
板との間に印加する電圧の絶対値は、受光領域17に比
べてガードリング領域18の方が僅かに大きいか同程度
である。この場合も、ガードリング領域18によって形
成される電界によって、受光領域17のエッジで横方向
に伸びる高電界の発生を抑えることができ、これにより
受光部pn接合からの電界はアバランシェ増倍層から光
吸収層まで一様に延びるようになり、また第1の実施形
態と同様にガードリング領域18に起因する電流はガー
ドリング領域18上に形成された電極23に流れるの
で、受光領域17の暗電流は低く抑えることができる。
FIG. 4 shows lines of electric force when a high voltage is applied to the APD according to the second embodiment. In FIG. 4, the absolute value of the voltage applied between the guard ring region 18 and the light receiving region 17 is slightly larger or almost the same as that of the light receiving region 17. Also in this case, the electric field formed by the guard ring region 18 can suppress the generation of a high electric field extending in the lateral direction at the edge of the light receiving region 17, whereby the electric field from the light receiving portion pn junction is reduced from the avalanche multiplication layer. Since the current uniformly extends to the light absorption layer, and the current caused by the guard ring region 18 flows to the electrode 23 formed on the guard ring region 18 as in the first embodiment, the darkness of the light receiving region 17 is reduced. The current can be kept low.

【0023】(第3の実施形態)図5は、本発明の第3
の実施形態に係わるAPDの概略構造を示す断面図であ
る。なお、図1と同一部分には同一符号を付して、その
詳しい説明は省略する。
(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
It is sectional drawing which shows the schematic structure of APD which concerns on embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

【0024】この実施形態では、n+ −InP基板11
上に、各層12,〜,15を先の実施形態と同じ条件で
形成したのち、続いてキャリア濃度が1〜2×1015
-3のn- −InP層16を0.2μm厚に、キャリア
濃度が1×1018cm-3のp+ −InP層56を0.8
μm厚に、順次エピタキシャル成長により形成した。次
いで、SiO2 膜21を絶縁マスクとして、Hイオンを
100kVで1×1013cm-2注入し、受光領域17及
びガードリング領域18の分離のための絶縁部(高抵抗
層)58を形成した。このイオン注入されたp型InP
領域56は400℃程度の熱処理により抵抗率106 Ω
cm以上の半絶縁領域58となる。また、図5では水素
をイオン注入源として用いたが、この代わりにn型不純
物を用いてもよい。この場合、n型不純物をイオン注入
した後、活性化のための熱処理を行えば、p+ 型受光領
域17とイオン注入領域の界面では緩やかなpn接合が
形成されることになり、電界集中緩和が期待できる。
In this embodiment, the n + -InP substrate 11
After the layers 12, 15 are formed under the same conditions as in the previous embodiment, the carrier concentration is then reduced to 1-2 × 10 15 c.
The n -InP layer 16 of m −3 has a thickness of 0.2 μm, and the p + -InP layer 56 having a carrier concentration of 1 × 10 18 cm −3 has a thickness of 0.8 μm.
It was formed to a thickness of μm by epitaxial growth. Then, using the SiO 2 film 21 as an insulating mask, H ions were implanted at 1 × 10 13 cm −2 at 100 kV to form an insulating portion (high resistance layer) 58 for separating the light receiving region 17 and the guard ring region 18. . This ion-implanted p-type InP
The region 56 has a resistivity of 10 6 Ω by heat treatment at about 400 ° C.
cm or more. Although hydrogen is used as an ion implantation source in FIG. 5, an n-type impurity may be used instead. In this case, if heat treatment for activation is performed after ion implantation of the n-type impurity, a gentle pn junction is formed at the interface between the p + -type light receiving region 17 and the ion implantation region, and the electric field concentration is alleviated. Can be expected.

【0025】図6に、第3の実施形態によるAPDに高
電圧を印加した場合の電気力線を示す。図6において基
板との間に印加する電圧の絶対値は、受光領域17とガ
ードリング領域18とで同程度である。
FIG. 6 shows lines of electric force when a high voltage is applied to the APD according to the third embodiment. In FIG. 6, the absolute value of the voltage applied to the substrate is substantially the same in the light receiving region 17 and the guard ring region 18.

【0026】なお、本発明は上述した各実施形態に限定
されるものではない。実施形態ではInP/InGaA
sへテロ接合APDについて説明したが、他のへテロ接
合APDやホモ接合APD等に適用することもできる。
即ち、半導体多層膜を用いる代わりに、ゲルマニウムや
シリコン等の基板の表面層に直接、受光領域やガードリ
ング領域を形成することも可能である。その他、本発明
の要旨を逸脱しない範囲で、種々変形して実施すること
ができる。
The present invention is not limited to the above embodiments. In the embodiment, InP / InGaAs is used.
Although the s heterojunction APD has been described, the invention can be applied to other heterojunction APDs, homozygous APDs, and the like.
That is, instead of using a semiconductor multilayer film, it is also possible to form a light receiving region or a guard ring region directly on a surface layer of a substrate such as germanium or silicon. In addition, various modifications can be made without departing from the scope of the present invention.

【0027】[0027]

【発明の効果】以上詳述したように本発明によれば、ガ
ードリング部を受光部のpn接合の外周部分に重ねて形
成するのではなく、受光部の外周部と重ならない領域に
受光部のpn接合形成と同時に形成し、受光部及びガー
ドリング部をそれぞれ異なる電極に接続することによ
り、受光部上に形成された電極を通じて流れる暗電流は
低く抑えることができる。また、イオン注入によって受
光部とガードリング部を分離することにより、その後の
熱拡散プロセスを必要とせず、しかも1回のイオン注入
処理で受光部とガードリング部を同時に形成できるの
で、製造工程の簡略化をはかり得る。
As described above in detail, according to the present invention, the guard ring is not formed so as to be superposed on the outer peripheral portion of the pn junction of the light receiving portion, but is formed in a region not overlapping with the outer peripheral portion of the light receiving portion. By forming the pn junction at the same time as forming the pn junction and connecting the light receiving portion and the guard ring portion to different electrodes, the dark current flowing through the electrodes formed on the light receiving portion can be suppressed low. In addition, by separating the light receiving portion and the guard ring portion by ion implantation, a subsequent heat diffusion process is not required, and the light receiving portion and the guard ring portion can be formed simultaneously by one ion implantation process. It can be simplified.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施形態に係わるAPDの概略構造を示
す断面図。
FIG. 1 is a sectional view showing a schematic structure of an APD according to a first embodiment.

【図2】第1の実施形態のAPDに電圧を印加したとき
の電気力線を示す模式図。
FIG. 2 is a schematic diagram illustrating lines of electric force when a voltage is applied to the APD according to the first embodiment.

【図3】第2の実施形態の概略構造を示す断面図。FIG. 3 is a sectional view showing a schematic structure of a second embodiment.

【図4】第2の実施形態における電気力線を示す模式
図。
FIG. 4 is a schematic diagram illustrating electric lines of force according to a second embodiment.

【図5】第3の実施形態の概略構造を示す断面図。FIG. 5 is a sectional view showing a schematic structure of a third embodiment.

【図6】第3の実施形態における電気力線を示す模式
図。
FIG. 6 is a schematic diagram showing electric lines of force according to a third embodiment.

【図7】本発明のAPD及び従来のAPDの逆方向電圧
印加における暗電流特性を示す特性図。
FIG. 7 is a characteristic diagram showing dark current characteristics of an APD of the present invention and a conventional APD when a reverse voltage is applied.

【図8】従来のAPDの概略構造を示す断面図。FIG. 8 is a sectional view showing a schematic structure of a conventional APD.

【符号の説明】[Explanation of symbols]

11…n+ −InP基板 12…n−InPバッファ層 13…n−InGaAs光吸収層 14…n−InGaAsP中間層 15…n−InPアバランシェ増倍層 16…n- −InP層 17…p+ 型層(受光領域) 18…p+ 型層(第1のガードリング領域) 19…p+ 型層(第2のガードリング領域) 21…絶縁膜 22,23…p側電極 24…n側電極 56…p+ −InP層 58…絶縁部(高抵抗層)DESCRIPTION OF SYMBOLS 11 ... n + -InP board 12 ... n-InP buffer layer 13 ... n-InGaAs light absorption layer 14 ... n-InGaAsP intermediate layer 15 ... n-InP avalanche multiplication layer 16 ... n -- InP layer 17 ... p + type Layer (light receiving area) 18 p + -type layer (first guard ring area) 19 p + -type layer (second guard ring area) 21 insulating film 22, 23 p-side electrode 24 n-side electrode 56 ... p + -InP layer 58 ... insulating part (high resistance layer)

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭60−173882(JP,A) 特開 昭56−87380(JP,A) 特開 昭50−57785(JP,A) 特開 昭63−204666(JP,A) 特開 昭63−224268(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 31/10 - 31/113 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-173882 (JP, A) JP-A-56-87380 (JP, A) JP-A-50-57785 (JP, A) JP-A-63-1988 204666 (JP, A) JP-A-63-224268 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 31/10-31/113

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】第1導電型の半導体基板と、この半導体基
板上に積層形成された少なくとも光吸収層及びアバラン
シェ増倍層を含む第1導電型の半導体多層膜と、この半
導体多層膜上に形成された第2導電型の半導体膜と、こ
の半導体膜に表面から裏面に達するまで高抵抗領域又は
第1導電型領域をリング状に形成してなり、内側の受光
領域と外側のガードリング領域とを電気的に分離する
離領域とを具備し、前記受光領域及びガードリング領域
をそれぞれ異なる電極に接続してなることを特徴とする
半導体受光装置。
A semiconductor substrate of a first conductivity type, a semiconductor multilayer film of a first conductivity type including at least a light absorption layer and an avalanche multiplication layer laminated on the semiconductor substrate, and The formed second conductivity type semiconductor film, and a high resistance region or
A first conductive type region becomes formed in a ring shape, to electrically isolate the inner light receiving region and an outer guard ring region min
A semiconductor light receiving device comprising: a separation region ; wherein the light receiving region and the guard ring region are respectively connected to different electrodes.
【請求項2】n型半導体基板上に少なくともn型光吸収
層,n型アバランシェ増倍層及び該増倍層と同種のp型
半導体層を順次成長する工程と、前記p型半導体層の受
光部となる領域とガードリング部となる領域の間にH,
D,He,Li,Be,Ne,Ar又はn型不純物の少
なくとも一つをイオン注入して、p型の受光領域とp型
のガードリング領域とを分離する工程と、前記n型半導
体基板,p型受光領域及びp型ガードリング領域のそれ
ぞれに異なる電極を接続する工程とを含むことを特徴と
する半導体受光装置の製造方法。
2. A step of sequentially growing at least an n-type light absorbing layer, an n-type avalanche multiplication layer and a p-type semiconductor layer of the same kind as the multiplication layer on an n-type semiconductor substrate; H, between the region to be the part and the region to be the guard ring part
Ion-implanting at least one of D, He, Li, Be, Ne, Ar, or an n-type impurity to separate a p-type light receiving region and a p-type guard ring region; connecting different electrodes to the p-type light receiving region and the p-type guard ring region, respectively.
JP10056687A 1998-03-09 1998-03-09 Semiconductor light receiving device and method of manufacturing the same Expired - Fee Related JP2996943B2 (en)

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Application Number Priority Date Filing Date Title
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Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP1083556A Division JP2793238B2 (en) 1989-03-31 1989-03-31 Semiconductor light receiving device and method of manufacturing the same

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Publication Number Publication Date
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JP2996943B2 true JP2996943B2 (en) 2000-01-11

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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