JPS5830160A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the breakdown of elements due to parasitic charges, in the MIS type semiconductor device having a multilayered wiring structure, by connecting a part of a lower layer wiring which is connected to a gate to a substrate through a reverse direction junction having a lower breakdown voltage than that of a gate insulating film. CONSTITUTION:On a P<-> type Si substrate 11, a field oxide film 14, which has windows in a transistor forming region 12 and a protecting connection forming region 13, is provided. A thin gate oxide film 15 is deposited on the region 12 in the window, and an oxide film 15' having the same thickness is provided on the region 13. Then a polycrystal Si gate electrode 16 is provided on a film 15. With the electrode 16 and the film 14 as a mask, P<+> ions are implanted. Then, an N<+> type source region 17a and a drain region 17b are yielded in the substrate 11 on both sides of the electrode 16. A diffused protecting region 17c is yielded beneath the film 15'. Thereafter a PSG film 18 is deposited on the entire surface, windows are opened, the wirings 20a and 20b are attached to the regions 17a and 17b, and the same wiring 20c is attached to the electrode 16 and the region 17c.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an MI811 semiconductor device, and more particularly to a structure for protecting a gate insulating film in a MI8I1 semiconductor device having a multilayer wiring structure.

When applying a multilayer wiring structure to an MI8m semiconductor integrated circuit device, the lower wiring connected to the gate of the semiconductor element becomes electrically floating (70-ting) during the multilayer wiring formation process, and the core If the underlying wiring is charged up for some reason (for example, when a wiring connection window is formed in the interlayer insulating film by dry etching), there is no place for this charge to escape, so the voltage exceeds the withstand voltage of the gate insulating film. When the voltage reaches , radiation is generated through the gate insulating film and the device is destroyed by &1.

An object of the present invention is to provide a structure that prevents element destruction due to the parasitic charges described above, and to improve the manufacturing yield of MIS type semiconductor devices having a multilayer wiring structure.・In other words, the present invention provides an MIS type semiconductor device with a multilayer wiring structure in which a part of the lower wiring connected to the gate is disconnected from the gate.
It is characterized in that it is connected to a semiconductor substrate via a reverse junction or Schittky barrier having a breakdown voltage lower than the withstand voltage of JII.

Hereinafter, the present invention will be explained in detail by way of examples using figures.

Note that FIG. 1 is an equivalent circuit diagram (a) and a planar structural diagram (b) of the first embodiment of the present invention, and FIG. 2 is a diagram of the second embodiment of the present invention.
Pricing circuit diagram (81) and planar structural diagram Φ in the example of
), FIGS. 3(1) to 3(f) are cross-sectional views of the manufacturing process in the first embodiment, and FIGS. 4(a) to (f) are sectional views of the manufacturing process in the second embodiment.
It is a manufacturing process sectional view in an Example.

In the MIa type semiconductor device according to the first aspect of the present invention, for example, as shown in the equivalent circuit diagram of FIG. It has a structure in which it is connected to the semiconductor substrate E via a protective PN junction J1 in the opposite direction. In the figure, 8 indicates a source, and D indicates a drain.

The planar structure of the MI8g semiconductor device is shown in FIG. A polycrystalline 8i gate electrode 2 is provided through the gate electrode 2, and P″″! is exposed on both sides of the skeleton gate electrode 2. !
181 The first . Second N+m diffusion region 3
m, 3b, that is, the furnace 1 source/drain regions are formed. In addition, P″″ defined and expressed by the field oxide film 1
WiSt″ A third N+ type diffusion region 3 is formed on the WiSt substrate surface.
C is formed. and the diffusion regions 3a, 3b,
Parts of the first, second, and 30th) N+ type diffusion regions 3a, 3b, and 3c are exposed in the first insulating film (lower layer insulating film) covering the substrate on which the gate electrode 2 and the gate electrode 2 are formed. First, second and third contact windows 4a, 4b, 4c and polycrystalline S [a fourth contact window 4d exposing a part of the gate electrode 2 is provided n1 on the first insulating film. A lower source layer made of aluminum (A4) or the like is in contact with the first N+ type diffusion region 3a or the second N'' type diffusion region 3b in the contact window 4a or 4b, respectively.
Drain arrangement 5a, 5b and the contact window 4d
A lower layer gate wiring 5C made of A4 or the like is formed to be connected to the polycrystalline 8i gate electrode 2 at the contact window 4C and to the third N+ type diffusion region 3C at the contact window 4C. And the history (this lower layer wiring 5a, 5b, 5
A second substrate having a wiring connection window (through hole) 6 that exposes a part of the surface of the lower layer gate wiring 5C is formed on the substrate having a
An insulating film, that is, an interlayer insulating film is provided, and an upper layer interconnect 7 made of At or the like is formed on the interlayer insulating film to connect to the lower gate interconnect 5C in the interconnect connection window 6.

Further, the MIa type semiconductor device falling under the second aspect of the present invention has a gate G as shown in the equivalent circuit diagram of FIG. 2(a), for example.
The wiring connected to the semiconductor substrate E has a structure in which the wiring connected to the semiconductor substrate E is connected to the semiconductor substrate E through the semiconductor substrate E, which has a breakdown voltage lower than the withstand voltage of the insulating film. The source and D indicate the drain.As shown in FIG. 2(b), the planar structure of the MIS type semiconductor device is as shown in FIG. , a polycrystalline Si gate electrode 2 is provided through a gate oxide film, and the N-type 8i substrate surface exposed on both sides of the gate electrode 2 has eleventh second P+ type diffusion regions ga, 3b, that is, P − type source/drain regions are formed.The first insulating film (lower layer insulating film) covering the substrate on which the diffusion regions 8g and 8b and the gate electrode 2 are formed has first and second P+ type regions. First and second contact windows 4a+4b exposing portions of diffusion regions ga and gb, respectively
sNm8i Third contact that exposes a part of the slow plate surface)
f14c, and a fourth contact window 4d exposing a part of the polycrystalline St gate w pole 2, and the first P + Diffusion region 8a and second P+ type diffusion region 8b
Lower layer source/drain wirings 5a, 5b made of A4 or the like are connected to the polycrystalline S1 gate electrode 2 at the contact 1134d, and a -t wiring 5C is formed. Furthermore, the lower layer distribution Msat5
On the substrate having b+sc, the lower gate wiring 50
A second insulating film, that is, a glabella insulating film having a wiring connection window (through hole) 6 that exposes a part of the surface is provided, and the lower gate wiring 5C is formed on the interlayer insulating film at the wiring connection window 6. It has a structure in which an upper layer wiring 7 made of At or the like is formed to be connected to.

Next, the above 1. MO having the structure shown in the second embodiment
A method for manufacturing an a-type semiconductor device will be explained. As shown in M08 having the structure of the first embodiment [When forming a semiconductor device, first use a normal method, as shown in Chapter 39], for example, A field oxide layer having a window exposing the transistor formation region 12 and the protective connection diffusion region 13 on the P″″fi8i substrate 11 having a resistivity of about -am)! After forming the gate oxide 1[15], a gate oxide 1 [15] having a thickness of, for example, about 500(1) is formed on the surface of the transistor formation region 13 by a normal thermal oxidation method. At this time, a thin oxide M15' of 500 (131i degree) is also formed on the protective connection forming region 13 surface.
.

A polycrystalline 81 layer with a thickness of Then, using the polycrystalline Si gate electrode 16 and the field oxide film 14 as a mask, selective coating is applied to the surface of the P-type 81 substrate 11 (for example, 5x10" Catm/cn?).
Phosphorus ions (P
”), the implanted region is activated,
In the transistor formation region 12, a first . The second N+ type expansion region, that is, the N+ type source/drain region 17m, 17b is also placed in the protective connection forming region 13 by 1C.
A third N+ type diffusion region with a depth of about μm3, that is, an N+ type diffusion region 5i1i! : Form a subsequent diffusion region 17C. Next, the substrate is coated with phosphorus silicate glass (pS) by a conventional OVD method.
G) He who formed the first insulating film of the cape, that is, the lower insulating film,
Using the usual wet etching method etc.,
), source/drain regions 171.1 are formed in the lower layer insulation mis and the gate oxide films 15, 15'.
7b side, the first side exposing the protective connection diffusion region 170 side. Second. Third=r7 tact windows 19a, 19b 119C and a fourth contact window 19d exposing the surface of the polycrystalline 8i gate electrode 16 are formed on the substrate by a method such as ordinary vapor deposition. ] is deposited and turned by a normal method to form the contact window 1 on the lower insulating film 18, as shown in FIG. 3(d).
Source/drain regions 11.17 in 9a and 19b
Source-drain arrangement 1120m each connected to b
, 20b, and a gate wiring *ZOC connected to the gate electrode 16 and the protective connection diffusion region 13 in the contact windows 19d and 190. Note that the gate wiring #20C on the gate electrode 16 and the gate wiring 20c on the protective connection diffusion region 17C are a series of wirings connected in a region not shown. After the wiring is formed, a normal 7a ing process is performed to make each connection part an open connection. Next, a second insulating film, that is, a glabellar insulating film made of PSG or the like, is formed on the substrate by the OVD method or the like, and then, as shown in FIG. 3(ei), the glabellar insulating film 21 is coated with the Wiring connection window (through hole) that exposes a part of gate wiring 20C
22 is formed using a normal dry etching method etc.
Next, a layer of 1 [μm) II is deposited on the substrate by a method such as vapor deposition.
Form an At layer with a thickness of K, and use the usual method such as Ichibantsuchiygta to create a layer of butter! Then, as shown in FIG. 3(f), an upper layer wiring 238 is formed on the interlayer insulating film 21 to connect to the lower layer gate wiring 20c in the wiring connection window 22.

In the method of the above embodiment, the PN formed between the N+ type protection connection diffusion region 17C and the P- type Si substrate
Since the junction has a reverse breakdown voltage of about 20 to 30 (V), which is lower than the breakdown voltage of about 40 (V) of the gate oxide film 15,
When forming the wiring connection window 22 on the interlayer insulating film 21 by dry etching, such as active ion etching @-j! 1. Charges accumulated in the gate wiring 20C in excess of the reverse breakdown voltage of the PN junction are released to the P''98i substrate 11 via the protective connection diffusion region 17c.
The gate oxide film 15 will not be destroyed. In addition, the reverse breakdown voltage of the nuclear PN junction is sufficiently higher than the % original voltage of the semiconductor device, so it does not affect the operation of the device.Next, a Mo5M semiconductor device having the structure of the second embodiment is formed. To explain in detail, as shown in Section 4VA(a), for example, the transistor formation region 12 and the protective connection region 13 are formed on an N-type 81 substrate 31 having a specific resistance of about 1 [0-1]. After forming a field oxide film 14 having a window, a gate oxide film 15 with a thickness of about 500 mm (JL) is formed on the transistor forming region 12 by a method similar to that of the first embodiment. Formation area 1
A thin oxide film 15' of about 500 (4) is formed on three sides,
Furthermore, a polycrystalline Si gate electrode 16 having a thickness of about 4000 (X) is formed on the gate oxide film 15. Then Fig. 4 6)
As shown in FIG. 1, after covering the insulation layer 13 with a photoresist film 32, using the field oxide film 14 and gate electrode 16 as a mask, a layer of IX 10" (at
m/cll? ), boron ions (B+) are selectively implanted to a depth of approximately 1 (am), and then the photo-resist film 32 is removed and a desired activation process is performed to form a fourth Transistor formation region 1 as shown in Figure (C)
2 to 1 to a depth of about 1 [μm]. A second P+ type diffusion region, that is, a P+ type source/drain region 33m, 33b is formed, and then the source/drain region aaa, 33b surface and the N type 8
The first plate exposes the Il connection forming region 13 surface of the i-substrate 31.
゜2nd, ff13 contact windows 19a, 19b, 1
9c and a fourth surface exposing the polycrystalline Si gate electrode 16 surface.
A first insulating film, that is, a lower insulation film 111 [1g] having a contact window 19d is formed. Next, as shown in FIG. 4(d), the lower layer insulation M2 is formed using the same method as in the first embodiment.
On S, 1st. Source/drain regions 33a in second contact windows 19m, 19b.

Source/drain wirings 20a, 20b made of At and connected to the fourth contact window 19d, respectively.
and connect to the gate electrode 16 through the third contact window 1.
A gate wiring 20C made of At and directly in contact with the N-type 81 substrate 31 is formed at 9c. In addition, there is a gate turtle in the figure! Gate wiring #20c on 16 and line film connection formation region 1
The gate wiring 20C on 3 is a series of wiring connected in a region not shown. Next, a glabellar insulating film such as P2O is formed on the substrate by OVD, and then a wiring connection window is formed in the glabellar insulating film 21 to expose a part of the gate wiring 20C, as shown in FIG. (Through hole) 2
2 is formed using a normal dry bone etching method, etc., and then, using the same method as in the first embodiment, as shown in FIG. Upper layer wiring 23 connected to the gate wiring 20C in the connection window 22
form.

In addition, in the method of the above embodiment, the static barrier between the N-type St substrate 31 formed in the third contact window 19C and the gate arrangement/520C made of kA is formed during the formation of the interlayer insulating film. By heating, At is alloyed with the N-type 8i substrate. The breakdown voltage of the Shitsuki barrier is lower than the breakdown voltage of the gate oxide film 15 (15 (
V), the charge accumulated in the gate wiring 20C in the multilayer wiring formation step f in excess of the breakdown voltage is released to the N-type SI substrate 31 via the SI barrier. Ru. Therefore, the gate oxide film 15 is not destroyed by accumulated charges. Further, since the breakdown voltage of the shuttling barrier is sufficiently higher than the power supply voltage of the semiconductor device, it does not interfere with the operation of the device.

In the above embodiment, the gate protection structure using a PN junction was explained as N-MO8, and the gate protection structure using a shield barrier was explained as P-MO8.
It can be applied to 8 and N-MO8 as well as 0-MO8.

In addition, the protection structure based on the shield barrier connection is
It is not limited to At. For example, titanium (Ti) or molybdenum (MO) can be used for the lower wiring connected to the gate electrode.

Furthermore, the silica barrier is coated with platinum silicide (PtSt).
) and then vapor-depositing aluminum on top of it to form a PTSI wiring.
becomes. In this case, the breakdown voltage is 10 (V) 1i[.

Further, it goes without saying that the semiconductor substrate side is not limited to silicon (8i).

As explained above, if the structure of the present invention is applied to a MIS type semiconductor device with a multilayer wiring structure, the charge l accumulated in the lower layer wiring connected to the gate electrode during the multilayer wiring formation process, etc. will no longer be destroyed. Therefore, the manufacturing yield of MIS type semiconductor devices with multilayer wiring structure is improved.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram (a
) and a planar structural diagram φ), FIG. 2 is an equivalent circuit diagram (a) and a planar structural diagram (b) in the second embodiment of the present invention, and FIG.
Figures (a) to (0) are sectional views of the manufacturing process in the first embodiment, and Figures 4(a) to (f) are sectional views of the manufacturing process in the second embodiment. , G is the gate, JB is the protective reverse junction,
S side is a seal barrier, E is a semiconductor substrate, 1 is a field oxide film, 2 is a polycrystalline silicon gate electrode, 3a
, 3b is the first and second N+ reduced diffusion region (N+ type drain region), 3C is the third N4m diffusion region, 4g, 4
b, 4c, 4d are contact windows of the lower layer insulating film, 5a, 5
b is the source/drain wiring, 5C is the lower layer wiring connected to the gate, 6 is the wiring connection window (through hole), 7 is the upper first wiring, ga, 8b is the first and second P''ll diffusion region (P+ type source・Drain region). Fig. 1 Section 6) (8) 2r2J <Q
(Xiang No. 3 Port No. 4 Figure

Claims (1)

[Claims] 1. In the MI8111"?' conductor device with a multilayer wiring structure, a part of the lower wiring connected to the gate is connected via a reverse junction having a breakdown voltage lower than the breakdown voltage of the gate insulating film. MIal characterized by being connected to a semiconductor substrate
In an MI8m1 semiconductor device with a conductor-packed conductor device layer wiring structure, a part of the lower layer wiring connected to the gate is connected to the semiconductor substrate through a shut-off barrier having a breakdown voltage lower than the withstand voltage of the gate insulating film. MI8 characterized by being connected
111 Semiconductor device.