JPS5830142A - Mamufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize an effective dielectric isolation by a method wherein a P type Si substrate is provided with some V-shaped grooves reaching an N epitaxial layer and an insulating film is broken into openings at the groove pointed bottoms, the grooves are filled with P type polycrystalline Si, and the pointed bottoms are provided with channel cut regions by heat oxidation. CONSTITUTION:A two layer mask of an SiO2 layer 23 and Si3N4 layer 24 is laid down on an N epitaxial layer 22 on a P<-> type Si substrate 21 provided with an N<+> buried layer and is anisotropically etched for the formation of V-shaped grooves 27 with their pointed bottoms reaching the substrate 21, and is subjected to heat oxidation wherein an SiO2 film 28 is formed to cover the entire surface. An HF-base etchant is applied to etch the film 28 approximately into half, whereby holes 29 are created at the pointed bottoms. An undoped polycrystalline Si layer 30 approximately two times the depth of the V-shaped grooves 27 is built by CVD and is abraded until the Si3N4 layer 24 is exposed, when the top of the polycrystalline Si layer 30 is lower than the top of the Si3N4 layer 24. BF2 ion implantation followed by annealing results in the creation of P<+> channel cuts 3 at the pointed bottoms. Then, wet oxidation is performed at approximately 950 deg.C whereby an SiO2 thick film 32 is formed on the surface of the P<+> polycrystalline Si layer 30'. In this way, the width of the bird's beak 33 is approximately one third a beak expected in a conventional method, integration is enhanced, the region 31 is in some degree enlarged, resulting in an NPN bipolar device without device capacitance increase and parasitic pnp combinations.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
The present invention relates to a method for forming an isolation region in a semiconductor device.

In a semiconductor integrated circuit device, circuit elements arranged around transistors are formed on a common substrate, but at this time, it is necessary to isolate and insulate these circuit elements so that they are not affected electrically by each other. There is. One of the methods often used for this separation is l0P (isolation).
There is an insulator inlay film called bioxide-and-poly7 silicon.The conventional method for forming an insulator inlay film is, for example, the first
As shown in Figure (a), a thin layer of silicon dioxide (SiOt) 13 is formed by thermal oxidation on the surface of the N-type SI layer 2 formed on the P-type Sj substrate 1, and silicon nitride is deposited on top of it. (S!sN+) film 4 is formed, and then the 5IaN, film 4 and 8i0. N on membrane 3
A window is formed to expose the 6 sides of the V-shaped groove formation region of the fi8i epitaxial layer 2, and then, as shown in FIG. A 7-shaped groove 7 is formed by penetrating the N-type Si epitaxial layer 2 and reaching into the Si substrate 1 by etching, and then, as shown in FIG. 1(d), using the Si, N, film 4 as a mask, The first S is formed on the inner surface of the 7-shaped groove 7 by selective thermal oxidation.
In, an insulating film 8 is formed, and then, as shown in FIG. The polycrystalline silicon layer 9 is grown and then polished to form a residual polycrystalline silicon layer 9 only in the V-shaped #II7 as shown in FIG. 1(f), and then the SL .

N, selective thermal oxidation is performed using the film 4 as a mask to form the figure 7 groove 7.
Usually 0.8 to 1 [μm] on the surface of the polycrystalline silicon layer 9 within
), a method of forming the second insulating film 10 with a floating second Si layer has been used. However, in the conventional method described above, since the oxidation rates of the non-doped polycrystalline silicon layer and the single-crystalline silicon layer are about the same, the selective oxidation of the polycrystalline silicon layer 9 as shown in FIG. 8i, N, M4
8i0 is also applied from the side to the lower N-type Si epitaxial layer 2.
．． The film grows to a thickness of 1.5 to 2 (
, am), the bird's beak 12 is formed with a wide width. Therefore, if a functional area overlaps the bird's beak when forming an element, the element characteristics will change and the manufacturing yield will decrease. Therefore, in order to prevent a drop in the element yield, it is necessary to form a wide element forming area in advance. However, in order to reduce the junction capacitance and increase the speed, the use of such an insulator isolation structure has led to the problem of lowering the degree of integration. If an attempt is made to maintain the impurity concentration low, the interface of the P-type 8i substrate in contact with the sio film at the tip of the V-shaped groove tends to be reversed to Nll, resulting in phenomena such as a decrease in isolation voltage and an increase in leakage current. Therefore, there is a problem in that increasing the resistance of the substrate is restricted. Therefore, as a means to prevent the above-mentioned inversion, a method was attempted in which a channel cut region was formed by introducing P-type impurities into the 7-groove region of the P-type S1 substrate in advance, but in this case, the element capacitance increased. This was undesirable because it caused the occurrence of parasitic PNP and parasitic PNP.

In view of the above-mentioned problems, the present invention provides a manufacturing method that minimizes the reduction in the area of the element formation region and eliminates the increase in element capacitance and the generation of the PNP effect when performing insulator separation of bipolar semiconductor devices. provide.

That is, in a method for manufacturing a semiconductor device, the present invention forms a V-shaped groove reaching into the semiconductor substrate from the surface of the epitaxial layer of the second conductivity type 41 formed on the semiconductor substrate of the first conductivity type, and An insulating film is selectively formed on the inner surface of the V-shaped groove, and a hole is formed in the insulating film in a region surrounding the tip of the V-shaped groove by thickness control etching. A crystalline silicon layer is formed, a deaf impurity is selectively introduced into the polycrystalline silicon layer at a high concentration, and silicon dioxide insulation is selectively applied to the upper surface of the polycrystalline silicon layer by a thermal oxidation method. At the same time as forming the film, the first conductivity type impurity introduced into the polycrystalline silicon layer is introduced into the semiconductor substrate through the hole in the insulating film at the tip of the V-shaped groove, and The method is characterized by a step of forming a channel cut region in the vicinity.

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2(a) to 0).
This will be explained in detail using the process cross-sectional diagram shown in FIG.

To form, for example, an NPN type Ibora IO using the method of the present invention, first, as shown in FIG. N
On the substrate to be processed on which the type 8i pitaxial layer 22 has been formed, a sio film with a thickness of about 1000 [again] is formed by thermal oxidation.
A film 23 is formed, and a film 81 having a thickness of, for example, about 1000 to 2000 [^] is formed thereon by chemical vapor deposition (OVD).
．． N4 film 24 is formed. Next, as shown in FIG. A window 26 for processing a separation region is formed on two sides of the layer 22. Next, after removing the photoresist pattern 25,
Using the 8i, N, film 24, and Sin film 23 as masks, selective etching is performed by an anisotropic etching method using potassium hydroxide (KOH), etc., as shown in FIG. 2(C). In the window 26 for processing the isolation region, the N-type S1 pittaxial layer 22 is used to form a 7-shaped groove 27 that reaches the inside of the P-type S1 substrate 21 . Next, selective thermal oxidation is performed using the Si, N4 film 24 as an oxidation-resistant mask, and a second
As shown in Figure (d), a first Sin insulating film 28 having a thickness of, for example, 5000 (A) or more is formed on the inner surface of the 7-shaped groove 27, and then the 8 i 0. The insulating film 28 is controlled and etched to about 1/2 the thickness using a fluoric acid-based etching solution.The state after this control-etching is shown in FIG. 2(e), as shown in the figure. In the etching pot, a hole 29 is formed on the discontinuous surface of the StO insulating film 28 at the tip of the 7-shaped groove 27 where the etching rate is high. Next, as shown in FIG. 2 (D), a depth of 2 [
A non-doped polycrystalline S1 layer 30 is formed to have a thickness of about 1.5 times the thickness of the above. Note that the mosquito polycrystalline Si layer 30 is made of Sin.

In order to improve adhesion with the membrane, the first 500 to 1
000 (A) by the reduced pressure OVD method. Next, the polycrystalline Si layer 30 on the substrate is sequentially borsted from the top surface to expose the entire surface of the SIs N4J[24] as shown in FIG. 2Q). Note that polycrystalline Si is softer than S-imported N4, so in this case, the 7-shaped groove 2
The upper surface of the polycrystalline Si layer 30 in 7 is 81. It is lower than the upper surface of the N4 film 24. Then, as shown in FIG. 2(h), "5
Polycrystalline S in the figure 7 groove 27 using Nal[24 as a mask
For example, boron difluoride ions (BFlt) are deposited 2X on the top surface of the i-layer 30 with an acceleration energy of about 50 (Key).
The P-type impurity B was implanted at a high concentration of about 10'. 84 polycrystalline layers (P+ type polycrystalline Si layer) 30' are formed. Note that the ion implantation of the P-type impurity is performed using boron ion/(B
), acceleration energy 20 (Key)
Conditions for the implantation amount to be approximately 2 x 10" (atm/, / ) are appropriate. Also, by this annealing process, the highly manipulated boron B contained in the P+ya polycrystalline 84 layer 30' is transferred to the figure 7 groove 2.
Heat is diffused into the P'' type Si substrate 21 through the hole 29 of the insulating film 28, and a P+ type region, that is, a P+ type channel cut region 3 is formed near the tip of the V-shaped groove 27. be done. Next, the substrate is heated in humidified oxygen (0,) to form an oxidation-resistant film of Si, N4, as shown in FIG.
The surface of the P-type polycrystalline Si layer 30' in the 7-shaped groove 27 that is not covered by the 111j24 is selectively thermally oxidized, and a second Si layer with a thickness of about aooo [X], for example, and an insulating M32 are applied to the area. form. In this selective thermal oxidation, the polycrystalline Si layer doped with impurities at a high concentration, that is, the P-enhanced crystalline Si layer doped with boron to a high degree, is formed by a single crystal 81
That is, it exhibits a higher oxidation rate than the N-type 8i pitaxial layer, and the difference becomes larger as the thermal oxidation temperature becomes lower. Furthermore, at a temperature of about 950 (C), the oxidation rate of the polycrystalline 84 layer with a high impurity concentration is about twice as slow as that of the single crystal Si layer. Therefore, in the selective thermal oxidation described above, pressure oxidation at a temperature of about 950 (c) is appropriate in consideration of the oxidation rate. Since there is a large difference in oxidation rate between the polycrystalline S1 layer with high impurity concentration of 111°C and the single crystal Si layer, in the selective thermal oxidation of the above example,
8'lN4 film 24 lower N type SN Ebitakiguyal layer 22
The amount of oxidation from the sides has been significantly reduced compared to the conventional one, and the width of the bird's beak 33 is about 1/3 that of the conventional one, or 0.5 [
μm]. By the selective thermal oxidation step, the P
The +-type channel-cut region 31 is slightly enlarged.

After the formation of the insulator isolation region in this manner, the substrate to be processed consists of the Si, N, film 24 on the shallow surface of the substrate, and the Si film 24 on the shallow surface of the substrate.
o, the film 23 is removed, and the N! of the element forming region 34 is removed as shown in FIG. After exposing the surface of the 8i epitaxial layer 22, a functional region of a circuit element such as a transistor is formed in the pattern region according to a conventional method. In the figure, 3
5 is an N+ type collector contact region, 36 is a P type base region, 37 is an N+ type vine region, and 38 is a Sin film. Although not shown, an insulating film, a wiring pattern, etc. are then formed using normal methods to form the NP.
N-type piborae 0 is provided.

In the above embodiments, the present invention was explained with respect to an NPN type Pivot semiconductor device, but the method of the present invention is applicable to a PNP type
It can also be applied to fJ semiconductor devices.

As explained above, according to the method of the present invention, when forming an insulator isolation region having a V-shaped groove structure in a bipolar semiconductor device, the bird's beak of the oxidizer that is formed by penetrating into the element formation region Since the width of the bipolar semiconductor device can be kept extremely narrow, the integration density of the bipolar semiconductor device can be improved.

Since it can be formed in a narrow region near the tip of the shape, there is no increase in element capacitance or generation of PNP, and the operating speed of the bipolar semiconductor device can be improved.

[Brief explanation of drawings]

Figures 1g1 (a) to 10) are process cross-sectional views of the conventional method,
FIGS. 2(a) to 2(a) are cross-sectional views of the process of the method of the present invention. In the figure, 21 is a P'''' silicon substrate, 22 is an N-type silicon epitaxial layer, 23 is a silicon dioxide film, 24 is a silicon nitride film, 25 is a 7-hole resist pattern, 26 is an isolation region processing window, 27 is a V-shaped groove, 28
29 is a first silicon dioxide insulation film, 29 is a hole, 30 is a non-doped polycrystalline silicon layer, 30' is a P+ type polycrystalline silicon layer, 31 is a P+ type channel cut region, and 32 is a second silicon dioxide insulation film. Membrane, 33 is Bird's Beak, B
P and + represent boron difluoride ions. Single 1 times Qin 2 mouths

Claims (1)

[Claims] A V-shaped groove reaching into the semiconductor substrate is formed from the second conductivity type semiconductor epitaxial layer formed on the first conductivity type conductive substrate (its surface force), and selectively An insulating film is formed in the V-shaped groove, a region of the hole covering the tip of the V-shaped groove is formed by thickness control etching, a polycrystalline silicon layer is formed in the V-shaped groove, and a polycrystalline silicon layer is formed in the V-shaped groove. selectively introducing high concentration first conductivity type impurities into the polycrystalline silicon layer;
A silicon dioxide insulating film is selectively formed on the upper surface of the polycrystalline silicon layer by a thermal oxidation method, and the first conductivity type impurity introduced into the polycrystalline silicon layer is added to the insulating film at the tip of the V-shaped groove. 1. A method of manufacturing a semiconductor device, comprising the step of introducing a semiconductor substrate into a semiconductor substrate through a hole and forming a channel cut region near the tip of a V-shaped groove.