JPS5828957B2 - memory switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplex distribution and convergence unit (MDU) in a memory switch type time division switching system.

In general, the function of a multiplex distribution and convergence device (MDIJ) is as shown in FIG. ... and the time slot ij on the inbound highway,
It is required to focus (focus) each data of tk, t6, . . . on the time slot ti on the outgoing highway.

These (distribution) and (convergence) are used when sending the same data to multiple terminals at the same time in a communication system, or when making it possible to receive data from any one terminal among multiple terminals. The present invention aims to make it possible to apply this technology to simple broadcast communication, pseudo-loop communication, or multi-drop communication.

To generally realize this function, it is possible to apply a time slot converter that is often used in the time division switching system.

However, in that case, a disadvantage was that a dedicated device was required as the MDU.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory switch type time-division switching system that can serve both the general switching function and the multiplex distribution/focusing function.

In order to achieve the above object, the memory switch system of the present invention uses a data bus memory for general switching connection of each line and a dedicated bus memory for concentrating and connecting data of a plurality of lines in a memory switch type time division switching system. A sub-data bus memory is provided, and the address control holding memories of both memories hold identification information for multiplex distribution/convergence connections and general connections for multiplex distribution of one line data to multiple lines or convergence of the reverse. It is characterized in that it enables both connection and multiplex distribution convergence connection.

The present invention will be described in detail below with reference to examples.

FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention.

In the figure, a data bus memo IJ (
DPM) 3 and a sub-data bus memo IJ (SDPM) that collects and stores subscriber data are provided in parallel, while a holding memory 10 that stores address information and alerts for the data path memories 3 and 4 and controls their operations is provided. The address information is stored in the data path memory (
Data bus memory (DPM) 3.4 is controlled by data path memory control bit 11.

Sub data bus memo IJ branched from input highway 1
The OR game r-7 inserted in the circuit of (SDPM) 4 is the data of input highway 1 and the sub data memory (SDPM) 4.
The data input gate 8 connected in series performs an OR operation on the values read from the sub data bus memory IJ (
This is for clearing the contents of SDPM)4.

Data bus memory (DPM) 3 and sub data memory arrangement (
A gate combination circuit 9 uses the output of SDPM) 4 as an input to each one of a pair of AND gates, uses the aforementioned data bus control bit 11 as an input to each other, and extracts the output of these pairs of AND gates through an OR gate. The data path control bit 11 allows switching between a general time slot conversion function and a multiplex distribution/convergence function.

FIG. 3 shows the state when the data bus memory control bit 11 of the holding memory 10 in FIG. 2 represents a general time slot conversion function. Taking out only the memo J10, its operation will be outlined using the time chart of FIG.

That is, data Dim of time slot tm on inbound highway 1 is transferred to time slot tn of outbound highway 2, and data D of time slot in of human highway 1 is transferred to time slot tn of outbound highway 2.
A case will be described in which each of tn is converted to a time slot Lm of the outgoing highway 2.

To perform this conversion, the address mj of the data bus memory J (DPM) 3 is written in the 1m address of the holding memory 10, and the address mj of the data bus memory (DPM) 3 is written in the tn address.

Data D for 1m time slot of input highway 1
im is written to the address mj of the data bus memory 3 indicated by the contents of the 1m address of the holding memory 10, as shown by the arrow W in the figure.

The written data Dim is read out at the time slot tn of the output highway 2 by the address mj of the data bus memory 3 indicated by the contents of the tn7 address of the holding memory 10 as shown by the arrow R in the figure.

Data D of time slot tn of highway 1 entering at the same time
tn is the arrow W in the figure at the address mj of the data path memory 3.
It is written as shown in .

Similarly, the written data Dtn is
The data is read out at time slot Lm of iway 2 as shown by the arrow R in the figure.

In this way, time slot Lm of input highway 1
The data Dim is the time slot tn of Out Highway 2.
Also, the time slot tn on Highway 1
The output Dtn can be converted into the output highway 2 time slot Lm.

5a and 5b show the state in which the data path memory control bit 11 of the holding memory 10 indicates the multiplex distribution and focus function in order to explain the multiplex distribution and focus function in the embodiment of FIG. , data bus memo IJ (D
PM) 3.4 and the holding memory 10 are taken out, and FIG.

The operation will be explained below in 1) using the time chart of FIG. 6 while referring to FIGS. 5a and 5b.

In the figure, the date Dti of time slot ti on inbound highway 1 is changed to the time slot tj of outbound highway 2.
, tk, time slot i j of person highway 1
, ik is converted into the time slot ti of the outgoing highway 2 by logical ORing of the data Dtj and Dtk.

Here, the time slot t-i of the outgoing highway 2 will be called a convergence time slot, and the time slots t j and tk of the outgoing highway 2 will be called a distribution time slot.

The condition at the time of the focusing quim slot is shown in FIG. 5a,
The data Dti of time slot ti on the incoming highway is
It is written to the DPM address mi written to the address ti of the holding memory 10.

At the same time, time slots tj and t of input highway 1 are input from address mi of sub data bus memory IJ (SDPM) 4.
Data obtained by ORing data Dtj and Dtk at time k is read out to the output highway 2, and at the same time, the mi address of the sub data pulse memory (SDPM) 4 is erased.

Next, the state at distribution time slots ti and tk is the fifth
As shown in the figure, data Dtj at time slot tj of input highway 1 is written to mi address of sub data bus memory (SDPM) 4 according to address mi of data bus memory written to tj address of holding memory 10. It will be done.

At the same time, data Dti written to the mi address of the sub data bus memory (SDPM) 4 during the ti time slot is read out to the output highway 2.

Data D at time slot ik on input highway 1
tk is ORed with data Dtj read from the mi address of the sub data bus memory (SDPM) 4 indicated by the tk address of the holding memory 10, and then written to the same mi address.

In this way, the time slots ti-+tj, tk and tj, and tk→ti of the incoming highway 1 and the outgoing highway 2 can be converted.

By the way, it is clear from the above description that the data bus memory IJ (DPM) and sub data bus memory (SDPM) only need to have the number of words corresponding to the number of time slots to be focused.

This allows the memory to be expanded depending on the functional needs of the multiplexing distribution unit (MDU).

As described above, the multiplex distribution and convergence device in the memory switch system according to the present invention can serve both the general time slot conversion function and the multiplex distribution and convergence function.

[Brief explanation of drawings]

FIG. 1 is a general explanatory diagram of multiplex distribution and convergence, FIG. 2 is an explanatory diagram showing the configuration of a multiplex distribution and convergence device according to an embodiment of the present invention, and FIG. 3 is a general time slot conversion function of the embodiment of FIG. 2. FIG. 4 is a time chart thereof; FIGS. 5 a and b are explanatory diagrams of a state showing the multiplex distribution and focusing function in the embodiment of FIG. 2; FIG. 6 is a time chart thereof; In the figure,
1 is input highway, 2 is output highway, 3 is data bus memory, 4 is sub data bus memory, 5 is clock, 6
is a counter, 7 is an OR gate, 8 is an AND gate, 9 is a gate combination circuit, 10 is a holding memory, and 11 is a data bus memory control bit.

Claims (1)

[Claims] 1 In the memory switch type time division switching system, a data bus memory is provided for general switching connection of each line, and a dedicated sub data bus memory is provided for concentrating and connecting multiple line data into one, and a data bus memory is provided for controlling the addresses of both memories. The holding memory holds identification information of a multiplex distribution convergence connection and a general connection that multiplex distributes one line data to multiple lines or vice versa, and enables both general connection and multiplex distribution convergence connection. A memory switch method featuring