JPS5255408A - Memory switch system - Google Patents

Memory switch system

Info

Publication number
JPS5255408A
JPS5255408A JP13164475A JP13164475A JPS5255408A JP S5255408 A JPS5255408 A JP S5255408A JP 13164475 A JP13164475 A JP 13164475A JP 13164475 A JP13164475 A JP 13164475A JP S5255408 A JPS5255408 A JP S5255408A
Authority
JP
Japan
Prior art keywords
switch system
memory switch
function
roder
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13164475A
Other languages
Japanese (ja)
Other versions
JPS5828957B2 (en
Inventor
Shunichi Naito
Takuto Kojima
Hiroaki Sato
Hideaki Yumiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP13164475A priority Critical patent/JPS5828957B2/en
Publication of JPS5255408A publication Critical patent/JPS5255408A/en
Publication of JPS5828957B2 publication Critical patent/JPS5828957B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:In the time division coversion system, sub-data pass memory is provided in roder to make it possible to combine general switchboard function with multiple distribution converging function.
JP13164475A 1975-10-31 1975-10-31 memory switch Expired JPS5828957B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13164475A JPS5828957B2 (en) 1975-10-31 1975-10-31 memory switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13164475A JPS5828957B2 (en) 1975-10-31 1975-10-31 memory switch

Publications (2)

Publication Number Publication Date
JPS5255408A true JPS5255408A (en) 1977-05-06
JPS5828957B2 JPS5828957B2 (en) 1983-06-18

Family

ID=15062863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13164475A Expired JPS5828957B2 (en) 1975-10-31 1975-10-31 memory switch

Country Status (1)

Country Link
JP (1) JPS5828957B2 (en)

Also Published As

Publication number Publication date
JPS5828957B2 (en) 1983-06-18

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