JPS5826396A - Refresh system for dynamic random access memory - Google Patents

Abstract

PURPOSE:To perform refresh without decreasing the processing efficiency of a CPU, by performing refresh at the 1st half of one machine cycle and performing access at the latter half. CONSTITUTION:One cycle of the machine cycle is divided into a refresh mode for the prior half and a normal mode for the latter half at refresh and this time of division is controlled with normal/refresh switching signals NOR/REF. When the level of the signals NOR/REF is at L, RAS and CAS signals are risen at the same time, and when the RAS signal drops, a refresh address is given at a switching circuit ADSW as a system address, the row of an RAM only is designated for refresh operation. In the normal mode, a memory control circuit MEM.CONT controls leading and trailing of the RAS signal again.

Description

[Detailed description of the invention]
Refresh times of random access memory that can be refreshed only with ('F or rear part) Tj]
t9j T le.

The memory cell of a dynamic random access memory (hereinafter referred to as DYNAζTSUKRAν and H1T in the present invention) consists of a power supply, a capacitor, and two circuits connected in parallel to each other. The presence or absence of Yi Huan corresponds to the bits "1" and "0", y 1 Htl sum n; For this reason, Wako 'iE+' and -i must be refreshed within 1111 at a certain time, which is called a stiff refresh. Usually around 2 ms JiJ+
I'm refreshing. RA'M is the amount of array material in rows and columns, and it is necessary to select one memory cell and specify the refresh T and column T. In integrated circuit RAM, the memory TJ cell selection
[The number of λ bins of delusional addresses is necessary for memory selection.The number of λ bins of delusional addresses is input to the row/column addresses in the same manual bin by the number of F addresses. The size of the rows and columns varies depending on the soil, 128 rows x 128 columns with 16 bits and 1 bit with 64 bits.
It has 28 rows x 512 columns. For cells with a constant initial number of 1, rr7I:' are also commonly connected, and 17 retries are made at once. Otherwise, in the above-mentioned integrated circuit, in the case of 64 rows, the refresh operation for 7 rows 7j is 32 microseconds (1/64 of 2ξ seconds) t, and in the case of 12B rows, once every 16 microseconds.The 1st N is 70n/OLK is a refresh clock generation circuit, which has a clock generation circuit of 32 microseconds or 16 microseconds, and has a frequency of 32 microseconds or 16 microseconds. It is asynchronous with clocks φ1 and φ2.

F・OI, 1 circuit of refresher control PKF・C0
NT fresh address counter FT-(!0UI
It is input to J'T. refresh? III control circuit n
Ey-cONT is the refresh clock REF-(
! After receiving the LX, output the refresh Houkikyukage P/EKQ. )l-REQ is the CPU clock generation circuit MPI
Human power is applied to l-CLK. Clock start circuit MPσ-0L
At the falling edge of memory clock Ir4% MatK, F
Detection of l-BKQ signal Lm) and g-REQ
(h4WWr, H'i3゛R-()RAM7 4 outputs fall.R-GRANT No. 48 is H"ノJill l
The "H" IFJy interval of φ1 is extended by 'd1.' (The period becomes a scary fresh gourd cycle.F-GRANT
The signal is manually input to R11; F-CONT.

The other R-REQ is reset. Therefore, at the falling edge of the next MOLK (memo+7 clock) signal, R-
1'1EQ Detects "H" and returns to cycle. RFP-CLK also connects with the input of the refresh row address counter B-00UNT to count up the row address. The limit value of the counter is set to 64 or 12B.

The serial output is input to the address switching circuit ADEIW.

The memory address from the next device is input to the address circuit. What is R-GRANT? Normal/refresh switching signal NOR/RE
Due to F, the memory address is output in the j attendance cycle, and the refresh address is output as the system address bus in the refresh cycle. FIG. 2 is an operation time chart. In a normal cycle, the memory address 7 is time-divided and outputted to the 7th row address and the column address by the selection Gj WTf'W/COL of the row address and the 11th address.

Please indicate the system address in the box below.T09TAFL
/Sstrope signal FAB and column address strobe signal CA8 are signals for latching the row address input to FtAl and the column address input to 1S1!, respectively.
Falling to li where the RABIJ row address is certain,
Timing is assigned so that the CABLd column address falls in a stable song. Only '51' or fresh Togitake is specified, and 0AEI is controlled so that it does not fall during the refresh cycle. WK4y
No. J can be inserted (Ro No.) Jllchi readout signal, C
B is the number that selects the RAM 5 product circuit. These RAM 11IIJ numbers are generated from the memory clock signal. The refresh cycle used to be 161, but the power generated was 1 out of 32 normal cycles), and the power that was generated was 161. i! From the point of view of tOPU, this becomes an impossible dead time, which causes a decrease in the rate of death.

The purpose of the present invention is to improve the shortcomings of the previous di5, without reducing the effectiveness of the central design, and to refresh the 11
11 As usual, it is possible to create a dynamic RAM (without obtaining a refresh circuit). Embodiments of the invention 1 block lfi't Ij
l l! /J, refresh clock generation circuit or T
If x <, the clock pulse is received by the CPTJ clock generation circuit MPU-CLK, and the memory fj
ii Control circuit 1 [DM-CONT also requires E ← Example operation Go 6° Refresh! 1st; Creation (Finally, as shown in the T operation time chart shown in Figure 4, one cycle of the machine cycle is divided into a refresh mode part of the front cow and a normal mode part of the rear part.

This division timing is controlled by the normal/refresh switching number VOR/RBF as in FIG.

In the memory control circuit MKM-0ONT, the rising and falling edges of the FIAS and OAS signals are controlled and outputted by the normal η refresh switching signal.

ffl Assuming that one samurai whose normal/refresh switching signal is “L” is in refresh mode, RAEI, CA
When both s signals rise at the same time and the 2nd FAR falls, the refresh address is set to the address switching circuit AD.
Since it is given as a system address in 8W, the refresh operation is performed by moving only seven rows of RAM. Next, when the normal mode is entered, the memory h circuit 1 will return to RAS!
i1i control of stopping and falling. When the signal falls, the row address of the memory address is specified, and when CAB also falls next, the column address is specified, so the FAM visit/fill operation is performed. At this time, the painter's slope of wE, as is the same as that shown in FIG.

Next, Fig. 5 shows the 4KB memory of a 6800-thread 8-bit microcomputer. . In the figure, the mark is placed on Idozaki Nabayashi's head to indicate that it is an inverted signal of the slow signal. Figure 5 I
A or memory control 1 circuit Mll in Fig. 3: M-CoλT
Approximately corresponding to , the lower CNT in FIG. 5B is applied to the refresh counter R-COU'NT in FIG. In each figure, A15 to AO indicate memory addresses.

Corresponding to the memory control/circuit T Name 1 Partition diagram T In Figure 5 A, the significant 4 bits A1g to A12 of the memory address, their inverted numbers A15 to A12, and the decode T6゜Next, the processor Inverted yellow R/W of read/write signal from R/W and memory clock MCL K ($1 is I
From M = frequency I Mlz ), -XCS (chip select number), Yoshi W" (v, F included - ol) stop and apply to RAM. Also, memory clock MOLK O
> Obtain clock r7 with double/quadruple frequency (21
1,41A and T), those! Synthesize RAS, CAB
Get the best results. Then in the 51st US B 0) JTl,
Memory clock with 0NT2 and T counter! Count and output 6 bits. BEL indicates the selector, and the 6-bit output of the 77 counter! Two bits each are input to three selectors. And normal/refresh switching signal NOR/
Since it is the refresh mode when RBF and the row/column address selection signal 1/COL are both low, the above-mentioned counter output becomes the output of each selector to form the system address MA5 to MADN.Next. When NOI?/Hanging is "H", PoWlool, Kabi L", the selector EJiI operates to give the row address, and the second NO
The selector 8KL operates so that R/FtEF and the old man 100L both give a stitching column address of "H". The system address indicates the refresh address and the village/column address by the signal extracted from the memory clock in this manner, and the refresh mode and normal mode are effectively switched.

'In the refresh mode of the IC or machine cycle, contrary to what is shown in the illustration, it is also possible to use the refresh mode in normal mode.

In this way, according to the present invention, the special refresh cycle, viewed from the central lJ + push device, is completed.
111 will not occur again, so there will be no reduction in efficiency. It also has the effect of reducing the external iR mounting circuit as a refresh [6+ path].

Figure 4 shows the conventional refresh circuit.

Figure 2 shows the operation time chart of 1. lyI, and 3.
The figure is a block diagram of the 44th embodiment of the present invention, and FIG.
The operation time chart in the figure, Figure 5 shows the concrete refresh path 1 by the beam axis 1111 path ■1 T0 R-OLK...Refresh clock generation circuit CP
U...Kofujo j4! Device RBF-(!ONT...Refresh storage 1x1 [1
1st route R bow 11Q... Refreshment request I female MCLK
...Memory clock signal RAB--Row address strobe signal CAS...Column address strobe signal WK...1 inclusion signal CS...Integrated circuit selection signal Patent applicant: Fujitsu Ltd. Eisuke Suzuki

Claims (1)

[Claims] Address input is divided into rows and columns for memory cells configured in a dynamic random access memory. - (or the second half) outputs the refresh address and row address strobe (i), and the second half (or the first half) outputs the system address, row address strobe signal, and two column address strobe signals.
A circuit is provided, and a lock is used for the pushing device.
Refresh yourself in the first half (or rear) of the machine cycle! The feature is that the ir0 dynamic random access memory is accessed in the second half (or the first half).