JPH11306753A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor storage that is a DRAM and at the same time requires no control regarding refreshing operation at a memory user side. SOLUTION: A refresh control circuit 12 being provided in a DRAM 1 with a plurality of sub arrays 2 has a refresh activation counter 12a for generating a refresh period based on an external clock, a refresh address counter 12b for generating the refresh column address of the sub array 2, and the like. The refresh control circuit 12 controls refresh operation according to the counters 12a and 12b. At the same time, when the sub array 2 for performing the refreshing operation becomes the same as the sub array 2 during normal access, the refreshing operation is made by once changing to other sub arrays 2. At that time, the refreshing operation is controlled in parallel with normal memory access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor memory device, and more particularly to a refresh technique for a dynamic random access memory.

[0002]

2. Description of the Related Art Conventionally, refresh control of a dynamic random access memory (hereinafter simply referred to as DRAM) is performed by a user of a DRAM (system creator or the like) separately on a system board as shown in FIG. This is performed by creating a control circuit and inputting a refresh control signal (address signal, command signal, etc.) from the refresh control circuit to the DRAM. As the specific refresh control method, for example, the following method is known. In the following description, the logical negation of a signal is represented by adding "/" in front of the name of the target signal.

(1) ROR (/ RAS (Row Address Str
obe) Only refreshing method which supplies refresh address to DRAM from outside. (2) CBR (/ CAS (Column Address Strobe) before / RAS refresh) system A refresh counter is built in and the DRAM automatically generates a refresh address. During the refresh operation, the timings of / RAS and / CAS are reversed from those in the normal operation. In many cases, this CBR method is used.

(3) Self-refresh system In addition to the above-mentioned CBR refresh function, a self-refresh system is provided which has a built-in refresh timer so that refresh can be automatically performed when time is up. In particular, it is used at the time of battery backup.

As a technique for controlling the refresh operation from outside the DRAM as described above, for example, Japanese Unexamined Patent Application Publication No.
-Refresh control method for memory system described in Japanese Unexamined Patent Publication No.
"Refresh circuit and refresh method of DRAM" described in JP-A-6-84356, "Refresh method of DRAM" described in JP-A-6-84356, and "Memory access method" described in JP-A-6-309870. Control devices "are also known.

However, in any of these systems, devices, and methods, in controlling the refresh operation of the DRAM, it is necessary to input a refresh control signal from outside the DRAM to the DRAM.

[0007]

By the way, as described above, the DRA must be input by inputting a required signal from the outside.
In the M refresh control, the following restrictions cannot be ignored.

[0010] (a) It is necessary to prepare a refresh control circuit in the user side circuit, and it is necessary to secure a mounting area for the circuit on a system board or the like. [B] The user must design the refresh control circuit in accordance with the specification of the DRAM to be used, such as the number of control signals and their timing.

[C] In order to perform a refresh operation,
There are time periods when the DRAM cannot be accessed regularly,
Performance degradation on the system is inevitable. That is, there is a performance loss (busy rate) accompanying the refresh operation.

(D) In order to avoid a decrease in system performance due to the busy rate of the DRAM, it is necessary to take measures for improving the processing speed of parallel processing and the like. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device which is a DRAM and does not require any control of a refresh operation on a memory user side. It is in.

[0011]

According to a first aspect of the present invention, a refresh operation of a memory cell is performed without requiring an external refresh control signal. This is the gist.

According to a second aspect of the present invention, there is provided a semiconductor memory device requiring a refresh control operation of a memory cell, wherein the self-excited refresh means for internally performing the refresh control operation is provided. The point is to prepare.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the self-excited refreshing means is provided between the memory cell array and a sense amplifier for amplifying data read from the memory cell array. The gist of the present invention is to provide a transfer gate transistor provided and a control circuit capable of controlling the sense amplifier, the transfer gate transistor, and row decoding of a memory cell array independently of a normal read / write operation. I do.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the control circuit performs a read / write operation when refreshing the same memory cell array as the activated memory cell array. The essential point is that another memory cell array is refreshed once while avoiding the memory cell array being performed, and in a later refresh cycle, a refresh is performed on a memory cell array that has not been refreshed first.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the second aspect, the self-excited refreshing means includes a latch for latching an output of a sense amplifier for amplifying data read from the memory cell array. Circuit, a transfer gate transistor provided between the sense amplifier and the latch circuit, and control of the sense amplifier, the transfer gate transistor, the latch circuit, and row decoding of the memory cell array independently of a normal read / write operation. And a possible control circuit.

According to a sixth aspect of the present invention, in the semiconductor memory device according to the fifth aspect, the control circuit corresponds to an activated word line in parallel with a refresh operation of an arbitrary memory cell array. The gist of the present invention is to selectively turn on the transfer gate transistor, latch the data in the latch circuit, and then turn off the transfer gate transistor that has been turned on and activate a word line other than the word line. .

According to a seventh aspect of the present invention, in the semiconductor memory device according to the fifth or sixth aspect, the control circuit is activated when refreshing the same memory cell array as the activated memory cell array. The transfer gate transistor corresponding to the word line being turned on is selectively turned on to latch the data in the latch circuit. Thereafter, the transfer gate transistor which has been turned on is turned off and the word lines other than the word line are activated. The main point is to do.

Further, in the semiconductor memory device according to the present invention, the self-excited refreshing means may output read data from a pair of data lines output in two directions of the memory cell array. A sense amplifier for separately amplifying, a transfer gate transistor provided between each sense amplifier and the memory cell array, and a row decode of the sense amplifier, the transfer gate transistor, and the memory cell array independently of a normal read / write operation. And a control circuit that is controllable.

According to a ninth aspect of the present invention, in the semiconductor memory device of the eighth aspect, the control circuit corresponds to an activated word line in parallel with a refresh operation of an arbitrary memory cell array. The gist of the present invention is to selectively turn off the transfer gate transistor, confine the data to one of the sense amplifiers, and then activate a word line other than the word line.

According to a tenth aspect of the present invention, in the semiconductor memory device according to the eighth or ninth aspect, the control circuit is activated when refreshing the same memory cell array as the activated memory cell array. The gist of the present invention is to selectively turn off the transfer gate transistor corresponding to the word line to be turned off, confine the data to one of the sense amplifiers, and then activate a word line other than the word line.

According to the eleventh aspect of the present invention, in the semiconductor memory device according to any one of the third to tenth aspects, the word line of the memory cell array to be read is activated to restore the bit line potential. The gist is to inactivate the word line based on reaching a sufficient potential.

According to a twelfth aspect of the present invention, in the semiconductor memory device according to any one of the second to eleventh aspects, the self-excited refresh means includes an internal timer or a counter for counting an external clock. The gist is to activate the refresh operation based on the timer value of the internal timer or the count value of the counter.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of a semiconductor memory device according to the present invention will now be described with reference to FIG.
3 will be described in detail.

FIG. 1 shows a DRA according to the first embodiment.
FIG. 2 is a glock circuit diagram schematically showing an internal configuration of M. D
The RAM 1 has a memory cell array section (not shown) composed of a plurality of memory cells. This memory cell array section is composed of N sub-arrays divided by a predetermined division number N, and FIG. 1 shows one sub-array 2 (memory cell array). This sub-array 2 is composed of a plurality of memory cells 2A arranged in a matrix of, for example, m × n pieces. Each memory cell 2A has m
And a folded bit line pair (BL, / B) for writing / reading stored data.
L). Although n pairs of bit lines (BL, / BL) are provided in the sub-array 2, only one pair is shown in FIG. Each word line WL is connected to n memory cells 2A, and each bit line pair (BL, / BL) is connected to m memory cells 2A. Each bit line pair (BL, / BL)
Are also connected to a dummy cell, a precharge circuit, etc., but are not shown in FIG.

A transfer gate transistor (hereinafter simply referred to as a transistor) TG is connected to one end of each bit line pair (BL, / BL). A sense amplifier 3 for sensing read data of the memory cell 2A is connected to each bit line pair (BL, / BL) via these transistors TG. A write circuit 5 and a read circuit 6 are connected to the sense amplifier 3 via an input / output (I / O) / column control circuit 4, and these circuits 5, 6, etc., write data to the memory cell 2A, Data reading from 2A is performed.

The write circuit 5 and the read circuit 6 are connected to an input / output (I / O) pad 8 via an input / output (I / O) buffer 7. Note that the I
The / O / column control circuit 4 is provided with a column selection line, a column decoder, and the like, and controls the selection of the sense amplifier 3, etc., but details thereof are omitted. The type of the activation signal input to the transistor TG is switched by the switch 13 in the transistor TG.

A row decoder 9 for decoding the row address and selecting one word line WL is connected to the sub-array 2, and a row address buffer 10 is connected to the row decoder 9. I have. In the present embodiment, a predetermined number of bits from the most significant bit of the row address signal input to row address buffer 10 is
It is used as the selection signal Sa for the array 2. For example, if the upper two bits are the sub-array selection signal Sa, four sub-arrays 2 can be selected by the sub-array selection signal Sa. Then, the word line WL of each sub-array 2 is selected by the remaining bits of the row address signal.

As shown in FIG. 1, a control circuit 11 is provided in each section of the DRAM 1 such as the sense amplifier 3, the transistor TG, the I / O / column control circuit 4, the row decoder 9, and the row address buffer 10. , Various control signals are input from the memory, and normal memory access, that is, write / read control of memory data is performed.

Further, a refresh control circuit 12 is provided which controls each section of the DRAM 1 independently of the normal memory data write / read control to perform a refresh operation of all memory cells 2A constituting the DRAM 1. . Therefore, as shown in FIG. 1, the sense amplifier 3, the transistor TG, the row decoder 9, etc.
Various control signals are input to the respective units of the AM 1 from the refresh control circuit 12, similarly to the control circuit 11.

The refresh control circuit 12 includes a refresh start counter 12a, a refresh address counter 12b, and the like. The refresh activation counter 12a counts an external clock such as a system clock input to the DRAM 1 and measures the activation timing of the refresh operation. The refresh address counter 12b generates a refresh row address for each sub-array 2 and generates a refresh sub-array selection signal Sr for selecting the sub-array 2 to be refreshed. The refresh sub-array selection signal Sr is generated from a predetermined number of bits from the top of the refresh row address, for example, like the selection signal Sa of the sub-array 2. The control circuit 11 and the refresh control circuit 12 have the / RAS and / C
An external synchronization clock such as an AS or an address signal is input.

Next, the refresh operation of the DRAM 1 thus configured will be described with reference to FIGS. FIG. 2 is a flowchart showing the procedure of the refresh control process according to the first embodiment. These processes are performed autonomously under the control of the refresh control circuit 12. Here, “self-excited” means that no special refresh control signal is required from outside the DRAM 1 and
This means that the refresh control operation is performed only by the internal configuration of the RAM 1. This refresh control is performed by the DR
It is started after the power is turned on to AM1.

First, in step S1 shown in FIG. 2, the time when the DRAM 1 is not accessed, that is, DR
The time Tst during which the AM 1 is in the standby state (hereinafter simply referred to as standby time) is the self-refresh cycle Tse.
A determination is made whether lf has been exceeded. The measurement of the standby time Tst is performed, for example, by providing the refresh control circuit 12 with a standby time counter (not shown). The self-refresh cycle Tself is a cycle interval at which the normal self-refresh cycle is executed, for example, 100 microseconds (μS).

If it is determined in step S1 that the standby time Tst has exceeded the self-refresh cycle Tself, the process proceeds to step S7, where a normal self-refresh cycle is executed only by the internal control of the DRAM 1. The internal control of this self-refresh cycle is well known, and a description thereof will be omitted. Further, the self-refresh cycle of step S7 is repeatedly executed while the standby state is continued. On the other hand, if the standby time Tst does not exceed the self-refresh cycle Tself, that is, if the DRAM 1 is in the access state, the process proceeds to step S2. That is, in step S1, it is determined whether to enter a self-refresh cycle or an automatic refresh cycle described below. The transition to the normal self-refresh cycle here is because the self-refresh cycle Tself is longer than the execution cycle of the automatic refresh cycle described below. This is because power consumption can be reduced.

In step S2, it is determined whether or not the count value Nr of the refresh start counter 12a has reached a predetermined value A. This predetermined value A is DRA
It is determined based on the data holding characteristics of each memory cell 2A of M1. During the standby period in which the DRAM 1 is not accessed, the count value Nr of the refresh activation counter 12a is invalidated, and the DRAM 1 is accessed and starts counting. The refresh activation counter 12a has a count value Nr
Is reset to zero when it reaches the predetermined value A, starts counting again, and repeats this operation. Here, the period during which the count value Nr reaches the predetermined value A from zero is the automatic refresh cycle Tauto. Therefore, the automatic refresh cycle Tauto is arbitrarily set by changing the count value Nr arbitrarily.

That is, the automatic refresh operation according to the present embodiment is started and executed in a distributed manner for each period Tauto. At that time, only an external clock (system clock) is required, and no special refresh control signal is required from outside the DRAM 1.

When the data retention characteristic of the memory cell 2A is good and the automatic refresh cycle Tauto is longer than the self refresh cycle Tself, the steps S1 and S2 may be changed so that the self refresh is always performed. Good.

If the count value Nr has not reached the predetermined value A in step S2, that is, if it is determined that it is not the automatic refresh start timing, the operation does not shift to the automatic refresh operation. On the other hand, when it is determined that the count value Nr has reached the predetermined value A, the flow shifts to step S3 to shift to the automatic refresh operation.

In step S3, before the automatic refresh operation is started, it is determined whether or not the sub-array 2 to be refreshed is currently accessing data writing or the like. If the sub-array 2 is not being accessed, the process proceeds to step S6, and the memory cell 2A connected to the predetermined word line WL of the sub-array 2 is refreshed. On the other hand, if the sub-array 2 for which the refresh operation is to be performed is currently being accessed, the process proceeds to step S4. This step S3
For example, in the refresh control circuit 12, a match detection circuit (not shown) for the current sub-array selection signal Sa and refresh sub-array selection signal Sr is provided, and the determination is made based on the detection result of the match detection circuit. To do it.

Subsequently, in step S4, the data of the memory cell 2A connected to the currently selected word line WL in the sub-array 2 to be refreshed is stored in the sense amplifier 3. Then, the refresh operation is avoided in the currently selected sub-array 2, and the refresh sub-array selection signal Sr is incremented by, for example, one (+1), and the sub-array 2 to be refreshed is temporarily accessed. Change to another sub-array 2 that has not been changed. Then, the process proceeds to step S5 to perform the refresh operation of the other sub-array 2. Thereafter, for example, the refresh / sub-array selection signal Sr is decremented by one (-1).
Then, the refresh operation of the sub-array 2 avoiding the refresh operation is performed.

Next, the automatic refresh operation will be described with reference to FIGS. 3 (a) and 3 (b). FIG. 3 (a)
Are two sub-arrays 2 in the first embodiment.
3 (a), the sub-arrays 2i, 2j are connected to input / output (I / O) columns via sense amplifiers 3i, 3j. It is connected to the control circuit 4. FIG. 3B shows a DRAM.
A time chart when an automatic refresh operation is performed in addition to one normal access is shown. Note that FIG. 3B shows a mode in which only normal access is performed before time t0 shown in FIG. 3B, and normal access and automatic refresh operation are performed in parallel after time t0.

Next, various signals shown in FIGS. 3A and 3B will be described. In the time chart of FIG. 3B, the refresh signal is indicated by REF. When the refresh signal is activated, that is, when the count value Nr reaches a predetermined value A, the refresh signal rises to a logic high level. The automatic refresh operation is started with the rise. Note that this refresh signal REF is output from the automatic refresh cycle T
Activated (logic high) for each auto.

The word line activation signal of the sub-array 2i shown in FIG. 3A is WLi, the activation signal of the sense amplifier 3i is φSAi, and the transistor T
The Gi activation signal is φi. Here, the fall (inactivation) timing of the word line activation signal WLi at the time of the read operation shown in FIG. 3B is the same as that of the conventional inactivation shown by the broken line A in FIG. It is performed earlier than the conversion timing. This is because when the word line WL is activated and the bit line potential reaches a potential sufficient to restore data, the word line WL is immediately deactivated (reset the row address) and the refresh-only row address is changed. This is done to make it selectable and to expedite the transition to the refresh operation. Similarly, the word line activation signal of sub-array 2j shown in FIG.
The activation signal of j is φSAj, and the activation signal of the transistor TGj is φj.

The activation of the sub-arrays 2i and 2j, the transistors TGi and TGj, and the sense amplifiers 3i and 3j is based on the sub-array selection signal Sa (row address).
It shall be performed based on.

At the time t0, the refresh signal R
When the EF rises and the sub-array 2i is in the normal access state at this time, the refresh control circuit 12 recognizes this by the coincidence detection circuit, and (+1) sets the sub-array selection signal Sa to (+1). Select the array 2j. Then, as indicated by the arrow in FIG. 3B, the word line activation signal WLj of the sub-array 2j is activated, and then the sense amplifier 3j is activated by the activation signal φSAj. Thereafter, the activation signal φj of the transistor TGj falls, and the data of the memory cell 2A connected to the word line WLj is confined in the sense amplifier 3j. In FIG. 3B, during the refresh operation (after time t0), the / CAS signal shows a signal waveform in a so-called high-speed page read mode, which corresponds to the sub-array 2 other than the sub-array 2j. Indicates that the reading of the memory data is performed simultaneously. That is, refresh control by the refresh control circuit 12 is performed separately and independently of normal memory access. Therefore, it is possible to reduce the performance loss (busy rate) of the system due to the refresh operation.

When a normal memory access request is issued to the sub-array 2 during the refresh operation, the control is performed such that the refresh operation is shifted to another sub-array 2 so as to give priority to the normal memory access. Then, the busy rate can be reduced to zero.

As described above, according to the semiconductor memory device of the first embodiment, the following effects can be obtained. (1) According to the present embodiment, an automatic refresh operation is performed based on the count value Nr of the refresh activation counter 12a.
The cycle is started. Therefore, only an external clock (system clock) is required to activate the automatic refresh cycle, and no special refresh control signal is required from outside the DRAM 1. as a result,
There is no need to prepare a refresh control circuit in the user side circuit, and it is not necessary to secure a mounting area for the circuit on a system board or the like. Further, the user can specify the DR to be used, such as the number of refresh control signals and their timing.
There is no need to design a refresh control circuit corresponding to the AM specifications. That is, while being a DRAM,
It is not necessary for the memory user to perform any control related to the refresh operation.

(2) According to the present embodiment, since the refresh control by the refresh control circuit 12 is performed separately from the normal memory access, the performance loss (busy rate) of the system accompanying the refresh operation is reduced. It is possible to reduce the performance, thereby avoiding the performance degradation on the system due to the busy rate. For this reason, in order to avoid performance degradation on the system, there is no need to take measures for improving the processing speed of parallel processing and the like.

(3) According to the present embodiment, the deactivation of the word line activation signal WLi at the time of the read operation is performed earlier than before. Therefore, when the bit line potential reaches a potential sufficient for data to be sufficiently restored, the word line WL is immediately inactivated (row address is reset), and a row address exclusively for refreshing can be selected. As a result, the transition to the refresh operation is speeded up.

(4) According to the present embodiment, the DRAM 1
Since the normal self-refresh operation is performed in the standby state, the power consumption of the DRAM 1 can be reduced.

[Second Embodiment] Next, a second embodiment of the semiconductor memory device according to the present invention will be described with reference to FIGS. 4 to 6, focusing on the differences from the first embodiment. Will be described. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The differences between the second embodiment and the first embodiment are as follows. [1] Specifically, as shown in FIG. 4, a latch circuit 2 capable of holding data of a memory cell 2A via a transistor TG is supplied to a sense amplifier 3 connected to a sub-array 2.
0 is newly provided.

[2] In terms of control, as shown in FIG. 6B, the TG activation signal φ is normally set to a logic low level. Even when the sub-array 2 performing the refresh operation is the same as the sub-array 2 being accessed,
The refresh operation is performed within the same sub-array 2 without once changing the sub-array 2 that performs the refresh operation. The latch circuit 20 is controlled by the refresh control circuit 12 independently of the control circuit 11.

Hereinafter, the refresh operation of the second embodiment will be described with reference to FIGS. FIG. 5 is a flowchart showing a procedure of a refresh control process according to the second embodiment. These processes are performed based on the control of the refresh control circuit 12 as in the first embodiment, and the power supply to the DRAM 1 is performed. It is started after is input. In addition, in the flowchart shown in FIG. 5, the processing in steps S1, S2, and S7 is the same as the processing in the flowchart shown in FIG. 2, so that the processing from step S8 shown in FIG. explain.

In step S2 of FIG. 5, the count value Nr of the refresh start counter 12a is set to a predetermined value A.
Is reached, the process proceeds to step S8 regardless of whether the sub-array 2 performing the refresh operation is the same as the sub-array 2 being accessed, and enters the automatic refresh operation. In this step S8, the data of the memory cell 2A connected to the currently selected word line WL in the sub-array 2 is latched by the latch circuit 20 before the automatic refresh operation is started.
Then, the process proceeds to step S9, where the automatic refresh operation is performed.

Next, in step S2, step S8,
The transition of step S9 will be described with reference to a time chart shown in FIG. The time chart shows a case where a refresh operation and a normal access are performed in the same sub-array 2i shown in FIG.

Now, suppose that the refresh signal REF rises at time t0 shown in FIG. Then, in synchronization with this, the activation signal φi of the transistor TGi rises, and the data of the memory cell 2A connected to the word line WLi via the sense amplifier 3i is confined in the latch circuit 20. Thereafter, another word line WL (i + x) in the sub-array 2i is activated, and this word line WL (i + x) is activated.
The refresh operation of the memory cell 2A connected to x) is performed. At this time, as in the first embodiment,
In the high-speed page read mode, reading of the memory data confined in the latch circuit 20 is performed simultaneously.

As described above, according to the semiconductor memory device of the second embodiment, the effects (1) to (4) of the first embodiment can be obtained, and the following effects can be obtained. The effect can be obtained.

(5) According to the present embodiment, since the latch circuit 20 is provided, the refresh operation is performed even when the sub-array 2 performing the refresh operation is the same as the sub-array 2 during the normal access. The refresh operation within the same sub-array 2 can be performed without changing the sub-array 2 to be performed.

Third Embodiment Next, a third embodiment of the semiconductor memory device according to the present invention will be described with reference to FIGS. 7 to 9, with a focus on the differences from the first embodiment. Will be described. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The differences between the third embodiment and the first embodiment are as follows. [1] In configuration, as shown in FIG. 7, a refresh sense amplifier 30 for refreshing is additionally provided in the sub-array 2 via the transistor TGR in addition to the normal sense amplifier 3.

[2] In terms of control, even when the sub-array 2 performing the refresh operation is the same as the sub-array 2 during the normal access, the sub-array performing the refresh operation is controlled.
The refresh operation is performed in the same sub-array 2 without changing the array 2. The refresh sense amplifier 30 is connected to the refresh control circuit 12.
Is controlled independently of the control circuit 11.

Hereinafter, a refresh operation according to the third embodiment will be described with reference to FIGS. FIG. 8 is a flowchart showing the procedure of the refresh control process according to the third embodiment. These processes are performed under the control of the refresh control circuit 12 as in the first embodiment, and the power supply to the DRAM 1 is performed. It is started after is input. Further, in the flowchart shown in FIG. 8, the processing in steps S1, S2, and S7 is the same as the processing in the flowchart shown in FIG. explain.

In step S2 of FIG. 8, the count value Nr of the refresh activation counter 12a is set to a predetermined value A.
Is reached, the process proceeds to step S10 to start the automatic refresh operation regardless of whether the sub-array 2 performing the refresh operation is the same as the sub-array 2 under normal access. In this step S10, before starting the automatic refresh operation, the data of the memory cell 2A connected to the currently selected word line WL in the sub-array 2i is confined to the sense amplifier 3i. Then, the process proceeds to step S11, where the automatic refresh operation is performed.

Next, step S2, step S1
0, the transition of step S11 will be described with reference to a time chart shown in FIG. Note that the time chart shows a case where a refresh operation and a normal access are performed in the same sub-array 2i shown in FIG. 9A.

Now, assume that the refresh signal REF rises at time t0 shown in FIG. 9B. Then, in synchronization with this, the activation signal φi of the transistor TGi falls, the sense amplifier 3i is separated from the sub-array 2i, and the data of the memory cell 2A connected to the word line WLi is confined in the same sense amplifier 3i. . Thereafter, another word line WL (i + x) in the sub-array 2i is activated, and the refresh operation of the memory cell 2A connected to the word line WL (i + x) uses the transistor TGR and the refresh sense amplifier 30i. Done. At this time, as in the first embodiment, reading of memory data confined in the sense amplifier 3i is performed simultaneously in the high-speed page read mode.

As described above, according to the semiconductor memory device of the third embodiment, the effects (1) to (4) of the first embodiment can be obtained, and the following effects can be obtained. The effect can be obtained.

(6) According to the present embodiment, in addition to the normal sense amplifier 3, the refresh sense amplifier 30 for refresh is separately provided in the sub array 2 via the transistor TGR.
Even when the array 2 is the same as the sub-array 2 under normal access, the refresh operation in the same sub-array 2 can be performed without changing the sub-array 2 performing the refresh operation. Become.

[Fourth Embodiment] Next, a fourth embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG. 10, focusing on differences from the third embodiment. Note that the same components as those in the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

The differences between the fourth embodiment and the third embodiment are as follows. [1] As shown in FIG. 10A, the refresh sense amplifiers 40h and 40i for the refresh shown in FIG. 9A are omitted.

[2] In terms of control, the sense amplifier 3 is commonly used for normal access and refresh operation. Next, transition of the refresh operation in the fourth embodiment will be described with reference to a time chart shown in FIG. In the same time chart, FIG.
5 shows a case where a refresh operation and a normal access are performed in the same sub-array 2i shown in FIG.

Assume that the refresh signal REF rises at time t0 shown in FIG. Then, in synchronization with this, the activation signal φi of the transistor TG falls, the sense amplifier 3i is separated from the sub-array 2i, and the data of the memory cell 2A connected to the word line WLi is confined in the same sense amplifier 3i. . Thereafter, another word line WL (i + x) in the sub-array 2i is activated, and the refresh operation of the memory cell 2A connected to the word line WL (i + x) uses the transistor TGR and the (refresh) sense amplifier 3j. It is done. That is, here, the sense amplifier 3j is used for refresh. At this time, the I / O / column control circuit 20
Are appropriately controlled, and, similarly to the first embodiment, the reading of the memory data confined in the sense amplifier 3i is performed simultaneously in the high-speed page read mode.

As described above, according to the semiconductor memory device of the fourth embodiment, the effects (1) to (4) of the first embodiment can be obtained, and the following effects can be obtained. The effect can be obtained.

(7) According to the present embodiment, the sense amplifier 3 is shared for normal access and refresh operation. Therefore, when the sub-array 2 performing the refresh operation and the sub-array 2 during the normal access are the same without changing the sub-array 2 performing the refresh operation without providing a refresh sense amplifier separately. A refresh operation in the array 2 can be performed.

Each of the above embodiments can be implemented by changing the configuration as follows. In the above embodiments, an example in which the normal self-refresh operation is performed at the time of standby of the DRAM 1 has been described. However, the automatic self-refresh operation may be performed at the time of the standby.

In each of the above embodiments, the DRA
An example of an algorithm for performing the above-mentioned automatic self-refresh operation at the time of M1 access and performing normal self-refresh at the time of standby has been described. When the cycle Tauto≫the self-refresh cycle Tself, the DRAM 1
An algorithm for performing the above-mentioned automatic self-refresh operation at a certain timing regardless of whether or not there is access to the device may be adopted.

In the above embodiments, the automatic refresh cycle Tauto is set to
Although an example of generation based on the count value Nr of a has been described,
The automatic refresh cycle Tauto may be generated by a timer (internal reference time generating means) built in the DRAM 1. According to this configuration, all external signals related to the refresh operation become unnecessary.

In each of the above embodiments, the DR is controlled independently of the normal memory data write / read control.
A control circuit for controlling each part of the AM 1 to perform a refresh operation is provided separately from the control circuit 11 by the refresh control circuit 1.
Although the example in which the control circuit is constituted by 2 is shown, this may be constituted by one control circuit. In short, any form may be used as long as it is a control circuit configured to control each part of the DRAM 1 independently of normal memory access when performing the refresh operation.

In each of the above embodiments,
The configuration of the bit line pair (BL, / BL) in the array 2 is a folded type, but is not limited thereto. For example, the configuration of the bit line pair may be an open type.

In the first embodiment, at the time of refresh operation, the word line is activated, the potential of the data line reaches the rewrite potential, and the word line is inactivated. We did, but this is not necessary. The sub-array performing the refresh operation and the sub-array
In the case where the arrays are the same, an example has been shown in which the sub-array for performing the refresh operation is changed by incrementing the refresh sub-array selection signal Sr by one (+1). Any of the sub arrays may be selected to perform the refresh operation.

Next, technical ideas other than those described in the claims, which can be understood from the above embodiments, will be described below together with their effects. (1) The semiconductor memory device according to any one of claims 8 to 10, wherein the sense amplifier is shared between normal memory access and refresh operation.

According to the configuration described in (1), it is possible to perform a refresh operation in the same memory array without providing a refresh-only sense amplifier.

[0082]

According to the invention described in any one of the first to twelfth aspects, it is possible to control the refresh operation on the memory user side without requiring any special external refresh control signal. The refresh operation can be performed without any change.

According to the invention described in any one of the third to twelfth aspects, the normal memory access and the refresh operation can be performed in parallel. Any one of claims 5 to 10
According to the invention described in the paragraph, the normal memory access and the refresh operation can be performed in parallel in the same memory array.

According to the eleventh aspect of the present invention, the selection timing of the row address dedicated to refresh is advanced, and the transition to the refresh operation is speeded up. According to the twelfth aspect, it is possible to reduce the performance loss (busy rate) of the system due to the refresh operation.

[Brief description of the drawings]

FIG. 1 is a schematic block circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of refresh control according to the first embodiment.

FIG. 3 is an explanatory diagram showing a refresh control mode according to the first embodiment;

FIG. 4 is a schematic block circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention;

FIG. 5 is a flowchart showing a refresh control procedure according to the second embodiment;

FIG. 6 is an explanatory diagram showing a refresh control mode according to the second embodiment.

FIG. 7 is a schematic block circuit diagram showing a third embodiment of the semiconductor memory device according to the present invention;

FIG. 8 is a flowchart showing a refresh control procedure according to the third embodiment;

FIG. 9 is an explanatory diagram showing a refresh control mode according to the third embodiment.

FIG. 10 is an explanatory diagram showing a refresh control mode of a semiconductor memory device according to a fourth embodiment of the present invention;

FIG. 11 is an explanatory diagram showing a state of refresh control of a conventional DRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... DRAM 2 ... Sub array (memory cell array) 3 ... Sense amplifier 4 ... Input / output and column control circuit 9 ... Row decoder 10 ... Row address buffer 11 ... Control circuit 12 ... Refresh control circuit 12a ... Refresh start counter 12b ... Refresh address counter 20 Latch circuit 30 Refresh sense amplifier TR Transfer gate transistor

Claims (12)

[Claims] 1. A semiconductor memory device which performs a refresh operation of a memory cell without requiring an external refresh control signal. 2. A semiconductor memory device requiring a refresh control operation of a memory cell, comprising: a self-excited refresh means for internally self-exciting the refresh control operation. 3. The transfer gate transistor provided between a memory cell array and a sense amplifier for amplifying data read from the memory cell array, wherein the self-excited refresh means includes: a transfer gate transistor provided between the memory cell array and a sense amplifier for amplifying data read from the memory cell array; 3. The semiconductor memory device according to claim 2, further comprising: a control circuit capable of controlling the row decode of the control signal independently of a normal read / write operation. 4. 4. The control circuit, when refreshing the same memory cell array as the activated memory cell array, temporarily refreshes another memory cell array while avoiding a memory cell array in which a read / write operation is being performed. 4. The semiconductor memory device according to claim 3, wherein refresh is performed on the memory cell array that has not been refreshed earlier in said refresh cycle. 5. A latch circuit for latching an output of a sense amplifier for amplifying read data from a memory cell array, a transfer gate transistor provided between the sense amplifier and the latch circuit. 3. The semiconductor memory according to claim 2, comprising: a control circuit capable of controlling the sense amplifier, the transfer gate transistor, the latch circuit, and row decoding of a memory cell array independently of a normal read / write operation. apparatus. 6. The control circuit selectively turns on a transfer gate transistor corresponding to an activated word line and latches the data in the latch circuit in parallel with a refresh operation of an arbitrary memory cell array. 6. The semiconductor memory device according to claim 5, wherein said turned-on transfer gate transistor is turned off and a word line other than said word line is activated. 7. When refreshing the same memory cell array as the activated memory cell array, the control circuit selectively turns on a transfer gate transistor corresponding to an activated word line to latch the data. 7. The semiconductor memory device according to claim 5, wherein the latch is latched in a circuit, and thereafter, the transfer gate transistor that is turned on is turned off and a word line other than the word line is activated. 8. The self-excited refresh means includes sense amplifiers for individually amplifying read data from a pair of data lines output in two directions of the memory cell array, and a sense amplifier provided between each of the sense amplifiers and the memory cell array. 3. The semiconductor according to claim 2, comprising: a transfer gate transistor; and a control circuit capable of controlling the sense amplifier, the transfer gate transistor, and row decoding of a memory cell array independently of a normal read / write operation. Storage device. 9. The control circuit selectively turns off a transfer gate transistor corresponding to an activated word line to confine the data to one of the sense amplifiers in parallel with a refresh operation of an arbitrary memory cell array. 9. The semiconductor memory device according to claim 8, wherein a word line other than said word line is activated thereafter. 10. The control circuit, when refreshing the same memory cell array as the activated memory cell array, selectively turns off a transfer gate transistor corresponding to an activated word line to sense the data. 10. The device according to claim 8, wherein the signal is confined in one of the amplifiers, and thereafter a word line other than the word line is activated.
The semiconductor memory device according to claim 1. 11. The control circuit according to claim 3, wherein the word line of the memory cell array to be read is activated and the word line is deactivated based on reaching a potential sufficient to restore the bit line potential. 11. The semiconductor memory device according to any one of 10. 12. The self-excited refresh means includes an internal timer or a counter for counting an external clock, and activates a refresh operation based on the timer value of the internal timer or the count value of the counter.
2. The semiconductor memory device according to claim 1.